tree 9dd547a600631708e82db7f4626e960924bafe0e
parent cd016cb01835e0b9f62fb675b336fbded912dcb6
author Omri Itach <omrii@marvell.com> 1564999388 +0200
committer Stephen Boyd <sboyd@kernel.org> 1568783741 -0700

clk: mvebu: ap806: add AP-DCLK (hclk) to system controller driver

Add dynamic AP-DCLK clock (hclk) to system controller driver. AP-DCLK
is half the rate of DDR clock, so its derrived from Sample At Reset
configuration. The clock frequency is required for AP806 AXI monitor
profiling feature.

Signed-off-by: Omri Itach <omrii@marvell.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Link: https://lkml.kernel.org/r/20190805100310.29048-7-miquel.raynal@bootlin.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>