| &l4_wkup { /* 0x44c00000 */ |
| compatible = "ti,am4-l4-wkup", "simple-bus"; |
| reg = <0x44c00000 0x800>, |
| <0x44c00800 0x800>, |
| <0x44c01000 0x400>, |
| <0x44c01400 0x400>; |
| reg-names = "ap", "la", "ia0", "ia1"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0x00000000 0x44c00000 0x100000>, /* segment 0 */ |
| <0x00100000 0x44d00000 0x100000>, /* segment 1 */ |
| <0x00200000 0x44e00000 0x100000>; /* segment 2 */ |
| |
| segment@0 { /* 0x44c00000 */ |
| compatible = "simple-bus"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ |
| <0x00000800 0x00000800 0x000800>, /* ap 1 */ |
| <0x00001000 0x00001000 0x000400>, /* ap 2 */ |
| <0x00001400 0x00001400 0x000400>; /* ap 3 */ |
| }; |
| |
| segment@100000 { /* 0x44d00000 */ |
| compatible = "simple-bus"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0x00000000 0x00100000 0x004000>, /* ap 4 */ |
| <0x00004000 0x00104000 0x001000>, /* ap 5 */ |
| <0x00080000 0x00180000 0x002000>, /* ap 6 */ |
| <0x00082000 0x00182000 0x001000>, /* ap 7 */ |
| <0x000f0000 0x001f0000 0x010000>; /* ap 8 */ |
| |
| target-module@0 { /* 0x44d00000, ap 4 28.0 */ |
| compatible = "ti,sysc"; |
| status = "disabled"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0x0 0x0 0x4000>; |
| }; |
| |
| target-module@80000 { /* 0x44d80000, ap 6 10.0 */ |
| compatible = "ti,sysc"; |
| status = "disabled"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0x0 0x80000 0x2000>; |
| }; |
| |
| target-module@f0000 { /* 0x44df0000, ap 8 58.0 */ |
| compatible = "ti,sysc-omap4", "ti,sysc"; |
| reg = <0xf0000 0x4>; |
| reg-names = "rev"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0x0 0xf0000 0x10000>; |
| |
| prcm: prcm@0 { |
| compatible = "ti,am4-prcm", "simple-bus"; |
| reg = <0x0 0x11000>; |
| interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0 0 0x11000>; |
| |
| prcm_clocks: clocks { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| }; |
| |
| prcm_clockdomains: clockdomains { |
| }; |
| }; |
| }; |
| }; |
| |
| segment@200000 { /* 0x44e00000 */ |
| compatible = "simple-bus"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0x00000000 0x00200000 0x001000>, /* ap 9 */ |
| <0x00003000 0x00203000 0x001000>, /* ap 10 */ |
| <0x00004000 0x00204000 0x001000>, /* ap 11 */ |
| <0x00005000 0x00205000 0x001000>, /* ap 12 */ |
| <0x00006000 0x00206000 0x001000>, /* ap 13 */ |
| <0x00007000 0x00207000 0x001000>, /* ap 14 */ |
| <0x00008000 0x00208000 0x001000>, /* ap 15 */ |
| <0x00009000 0x00209000 0x001000>, /* ap 16 */ |
| <0x0000a000 0x0020a000 0x001000>, /* ap 17 */ |
| <0x0000b000 0x0020b000 0x001000>, /* ap 18 */ |
| <0x0000c000 0x0020c000 0x001000>, /* ap 19 */ |
| <0x0000d000 0x0020d000 0x001000>, /* ap 20 */ |
| <0x0000f000 0x0020f000 0x001000>, /* ap 21 */ |
| <0x00010000 0x00210000 0x010000>, /* ap 22 */ |
| <0x00030000 0x00230000 0x001000>, /* ap 23 */ |
| <0x00031000 0x00231000 0x001000>, /* ap 24 */ |
| <0x00032000 0x00232000 0x001000>, /* ap 25 */ |
| <0x00033000 0x00233000 0x001000>, /* ap 26 */ |
| <0x00034000 0x00234000 0x001000>, /* ap 27 */ |
| <0x00035000 0x00235000 0x001000>, /* ap 28 */ |
| <0x00036000 0x00236000 0x001000>, /* ap 29 */ |
| <0x00037000 0x00237000 0x001000>, /* ap 30 */ |
| <0x00038000 0x00238000 0x001000>, /* ap 31 */ |
| <0x00039000 0x00239000 0x001000>, /* ap 32 */ |
| <0x0003a000 0x0023a000 0x001000>, /* ap 33 */ |
| <0x0003e000 0x0023e000 0x001000>, /* ap 34 */ |
| <0x0003f000 0x0023f000 0x001000>, /* ap 35 */ |
| <0x00040000 0x00240000 0x040000>, /* ap 36 */ |
| <0x00080000 0x00280000 0x001000>, /* ap 37 */ |
| <0x00088000 0x00288000 0x008000>, /* ap 38 */ |
| <0x00092000 0x00292000 0x001000>, /* ap 39 */ |
| <0x00086000 0x00286000 0x001000>, /* ap 40 */ |
| <0x00087000 0x00287000 0x001000>, /* ap 41 */ |
| <0x00090000 0x00290000 0x001000>, /* ap 42 */ |
| <0x00091000 0x00291000 0x001000>; /* ap 43 */ |
| |
| target-module@3000 { /* 0x44e03000, ap 10 0a.0 */ |
| compatible = "ti,sysc"; |
| status = "disabled"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0x0 0x3000 0x1000>; |
| }; |
| |
| target-module@5000 { /* 0x44e05000, ap 12 30.0 */ |
| compatible = "ti,sysc"; |
| status = "disabled"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0x0 0x5000 0x1000>; |
| }; |
| |
| target-module@7000 { /* 0x44e07000, ap 14 20.0 */ |
| compatible = "ti,sysc-omap2", "ti,sysc"; |
| reg = <0x7000 0x4>, |
| <0x7010 0x4>, |
| <0x7114 0x4>; |
| reg-names = "rev", "sysc", "syss"; |
| ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | |
| SYSC_OMAP2_SOFTRESET | |
| SYSC_OMAP2_AUTOIDLE)>; |
| ti,sysc-sidle = <SYSC_IDLE_FORCE>, |
| <SYSC_IDLE_NO>, |
| <SYSC_IDLE_SMART>, |
| <SYSC_IDLE_SMART_WKUP>; |
| ti,syss-mask = <1>; |
| /* Domains (P, C): wkup_pwrdm, l4_wkup_clkdm */ |
| clocks = <&l4_wkup_clkctrl AM4_L4_WKUP_GPIO1_CLKCTRL 0>, |
| <&l4_wkup_clkctrl AM4_L4_WKUP_GPIO1_CLKCTRL 8>; |
| clock-names = "fck", "dbclk"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0x0 0x7000 0x1000>; |
| |
| gpio0: gpio@0 { |
| compatible = "ti,am4372-gpio","ti,omap4-gpio"; |
| reg = <0x0 0x1000>; |
| interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| status = "disabled"; |
| }; |
| }; |
| |
| target-module@9000 { /* 0x44e09000, ap 16 04.0 */ |
| compatible = "ti,sysc-omap2", "ti,sysc"; |
| reg = <0x9050 0x4>, |
| <0x9054 0x4>, |
| <0x9058 0x4>; |
| reg-names = "rev", "sysc", "syss"; |
| ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | |
| SYSC_OMAP2_SOFTRESET | |
| SYSC_OMAP2_AUTOIDLE)>; |
| ti,sysc-sidle = <SYSC_IDLE_FORCE>, |
| <SYSC_IDLE_NO>, |
| <SYSC_IDLE_SMART>, |
| <SYSC_IDLE_SMART_WKUP>; |
| /* Domains (P, C): wkup_pwrdm, l4_wkup_clkdm */ |
| clocks = <&l4_wkup_clkctrl AM4_L4_WKUP_UART1_CLKCTRL 0>; |
| clock-names = "fck"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0x0 0x9000 0x1000>; |
| |
| uart0: serial@0 { |
| compatible = "ti,am4372-uart","ti,omap2-uart"; |
| reg = <0x0 0x2000>; |
| interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; |
| }; |
| }; |
| |
| target-module@b000 { /* 0x44e0b000, ap 18 48.0 */ |
| compatible = "ti,sysc-omap2", "ti,sysc"; |
| reg = <0xb000 0x8>, |
| <0xb010 0x8>, |
| <0xb090 0x8>; |
| reg-names = "rev", "sysc", "syss"; |
| ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | |
| SYSC_OMAP2_ENAWAKEUP | |
| SYSC_OMAP2_SOFTRESET | |
| SYSC_OMAP2_AUTOIDLE)>; |
| ti,sysc-sidle = <SYSC_IDLE_FORCE>, |
| <SYSC_IDLE_NO>, |
| <SYSC_IDLE_SMART>, |
| <SYSC_IDLE_SMART_WKUP>; |
| ti,syss-mask = <1>; |
| /* Domains (P, C): wkup_pwrdm, l4_wkup_clkdm */ |
| clocks = <&l4_wkup_clkctrl AM4_L4_WKUP_I2C1_CLKCTRL 0>; |
| clock-names = "fck"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0x0 0xb000 0x1000>; |
| |
| i2c0: i2c@0 { |
| compatible = "ti,am4372-i2c","ti,omap4-i2c"; |
| reg = <0x0 0x1000>; |
| interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| }; |
| |
| target-module@d000 { /* 0x44e0d000, ap 20 38.0 */ |
| compatible = "ti,sysc-omap4", "ti,sysc"; |
| reg = <0xd000 0x4>, |
| <0xd010 0x4>; |
| reg-names = "rev", "sysc"; |
| ti,sysc-sidle = <SYSC_IDLE_FORCE>, |
| <SYSC_IDLE_NO>, |
| <SYSC_IDLE_SMART>, |
| <SYSC_IDLE_SMART_WKUP>; |
| /* Domains (P, C): wkup_pwrdm, l3s_tsc_clkdm */ |
| clocks = <&l3s_tsc_clkctrl AM4_L3S_TSC_ADC_TSC_CLKCTRL 0>; |
| clock-names = "fck"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0x0 0xd000 0x1000>; |
| |
| tscadc: tscadc@0 { |
| compatible = "ti,am3359-tscadc"; |
| reg = <0x0 0x1000>; |
| interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&adc_tsc_fck>; |
| clock-names = "fck"; |
| status = "disabled"; |
| dmas = <&edma 53 0>, <&edma 57 0>; |
| dma-names = "fifo0", "fifo1"; |
| |
| tsc { |
| compatible = "ti,am3359-tsc"; |
| }; |
| |
| adc { |
| #io-channel-cells = <1>; |
| compatible = "ti,am3359-adc"; |
| }; |
| |
| }; |
| }; |
| |
| target-module@10000 { /* 0x44e10000, ap 22 0c.0 */ |
| compatible = "ti,sysc-omap4", "ti,sysc"; |
| reg = <0x10000 0x4>; |
| reg-names = "rev"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0x0 0x10000 0x10000>; |
| |
| scm: scm@0 { |
| compatible = "ti,am4-scm", "simple-bus"; |
| reg = <0x0 0x4000>; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0 0 0x4000>; |
| |
| am43xx_pinmux: pinmux@800 { |
| compatible = "ti,am437-padconf", |
| "pinctrl-single"; |
| reg = <0x800 0x31c>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| #pinctrl-cells = <1>; |
| #interrupt-cells = <1>; |
| interrupt-controller; |
| pinctrl-single,register-width = <32>; |
| pinctrl-single,function-mask = <0xffffffff>; |
| }; |
| |
| scm_conf: scm_conf@0 { |
| compatible = "syscon", "simple-bus"; |
| reg = <0x0 0x800>; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| |
| phy_gmii_sel: phy-gmii-sel { |
| compatible = "ti,am43xx-phy-gmii-sel"; |
| reg = <0x650 0x4>; |
| #phy-cells = <2>; |
| }; |
| |
| scm_clocks: clocks { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| }; |
| }; |
| |
| wkup_m3_ipc: wkup_m3_ipc@1324 { |
| compatible = "ti,am4372-wkup-m3-ipc"; |
| reg = <0x1324 0x44>; |
| interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; |
| ti,rproc = <&wkup_m3>; |
| mboxes = <&mailbox &mbox_wkupm3>; |
| }; |
| |
| edma_xbar: dma-router@f90 { |
| compatible = "ti,am335x-edma-crossbar"; |
| reg = <0xf90 0x40>; |
| #dma-cells = <3>; |
| dma-requests = <64>; |
| dma-masters = <&edma>; |
| }; |
| |
| scm_clockdomains: clockdomains { |
| }; |
| }; |
| }; |
| |
| timer1_target: target-module@31000 { /* 0x44e31000, ap 24 40.0 */ |
| compatible = "ti,sysc-omap2-timer", "ti,sysc"; |
| reg = <0x31000 0x4>, |
| <0x31010 0x4>, |
| <0x31014 0x4>; |
| reg-names = "rev", "sysc", "syss"; |
| ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | |
| SYSC_OMAP2_SOFTRESET | |
| SYSC_OMAP2_AUTOIDLE)>; |
| ti,sysc-sidle = <SYSC_IDLE_FORCE>, |
| <SYSC_IDLE_NO>, |
| <SYSC_IDLE_SMART>; |
| ti,syss-mask = <1>; |
| /* Domains (P, C): wkup_pwrdm, l4_wkup_clkdm */ |
| clocks = <&l4_wkup_clkctrl AM4_L4_WKUP_TIMER1_CLKCTRL 0>; |
| clock-names = "fck"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0x0 0x31000 0x1000>; |
| |
| timer1: timer@0 { |
| compatible = "ti,am4372-timer-1ms","ti,am335x-timer-1ms"; |
| reg = <0x0 0x400>; |
| interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; |
| ti,timer-alwon; |
| clocks = <&timer1_fck>; |
| clock-names = "fck"; |
| }; |
| }; |
| |
| target-module@33000 { /* 0x44e33000, ap 26 18.0 */ |
| compatible = "ti,sysc"; |
| status = "disabled"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0x0 0x33000 0x1000>; |
| }; |
| |
| target-module@35000 { /* 0x44e35000, ap 28 50.0 */ |
| compatible = "ti,sysc-omap2", "ti,sysc"; |
| reg = <0x35000 0x4>, |
| <0x35010 0x4>, |
| <0x35014 0x4>; |
| reg-names = "rev", "sysc", "syss"; |
| ti,sysc-mask = <(SYSC_OMAP2_EMUFREE | |
| SYSC_OMAP2_SOFTRESET)>; |
| ti,sysc-sidle = <SYSC_IDLE_FORCE>, |
| <SYSC_IDLE_NO>, |
| <SYSC_IDLE_SMART>, |
| <SYSC_IDLE_SMART_WKUP>; |
| ti,syss-mask = <1>; |
| /* Domains (P, C): wkup_pwrdm, l4_wkup_clkdm */ |
| clocks = <&l4_wkup_clkctrl AM4_L4_WKUP_WD_TIMER2_CLKCTRL 0>; |
| clock-names = "fck"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0x0 0x35000 0x1000>; |
| |
| wdt: wdt@0 { |
| compatible = "ti,am4372-wdt","ti,omap3-wdt"; |
| reg = <0x0 0x1000>; |
| interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; |
| }; |
| }; |
| |
| target-module@37000 { /* 0x44e37000, ap 30 08.0 */ |
| compatible = "ti,sysc"; |
| status = "disabled"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0x0 0x37000 0x1000>; |
| }; |
| |
| target-module@39000 { /* 0x44e39000, ap 32 02.0 */ |
| compatible = "ti,sysc"; |
| status = "disabled"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0x0 0x39000 0x1000>; |
| }; |
| |
| target-module@3e000 { /* 0x44e3e000, ap 34 60.0 */ |
| compatible = "ti,sysc-omap4-simple", "ti,sysc"; |
| ti,hwmods = "rtc"; |
| reg = <0x3e074 0x4>, |
| <0x3e078 0x4>; |
| reg-names = "rev", "sysc"; |
| ti,sysc-sidle = <SYSC_IDLE_FORCE>, |
| <SYSC_IDLE_NO>, |
| <SYSC_IDLE_SMART>, |
| <SYSC_IDLE_SMART_WKUP>; |
| /* Domains (P, C): rtc_pwrdm, l4_rtc_clkdm */ |
| clocks = <&l4_rtc_clkctrl AM4_L4_RTC_RTC_CLKCTRL 0>; |
| clock-names = "fck"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0x0 0x3e000 0x1000>; |
| |
| rtc: rtc@0 { |
| compatible = "ti,am4372-rtc", "ti,am3352-rtc", |
| "ti,da830-rtc"; |
| reg = <0x0 0x1000>; |
| interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clk_32768_ck>; |
| clock-names = "int-clk"; |
| system-power-controller; |
| status = "disabled"; |
| }; |
| }; |
| |
| target-module@40000 { /* 0x44e40000, ap 36 68.0 */ |
| compatible = "ti,sysc"; |
| status = "disabled"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0x0 0x40000 0x40000>; |
| }; |
| |
| target-module@86000 { /* 0x44e86000, ap 40 70.0 */ |
| compatible = "ti,sysc-omap2", "ti,sysc"; |
| reg = <0x86000 0x4>, |
| <0x86004 0x4>; |
| reg-names = "rev", "sysc"; |
| ti,sysc-sidle = <SYSC_IDLE_FORCE>, |
| <SYSC_IDLE_NO>; |
| /* Domains (P, C): wkup_pwrdm, l4_wkup_aon_clkdm */ |
| clocks = <&l4_wkup_aon_clkctrl AM4_L4_WKUP_AON_COUNTER_32K_CLKCTRL 0>; |
| clock-names = "fck"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0x0 0x86000 0x1000>; |
| |
| counter32k: counter@0 { |
| compatible = "ti,am4372-counter32k","ti,omap-counter32k"; |
| reg = <0x0 0x40>; |
| }; |
| }; |
| |
| target-module@88000 { /* 0x44e88000, ap 38 12.0 */ |
| compatible = "ti,sysc"; |
| status = "disabled"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0x00000000 0x00088000 0x00008000>, |
| <0x00008000 0x00090000 0x00001000>, |
| <0x00009000 0x00091000 0x00001000>; |
| }; |
| }; |
| }; |
| |
| &l4_fast { /* 0x4a000000 */ |
| compatible = "ti,am4-l4-fast", "simple-bus"; |
| reg = <0x4a000000 0x800>, |
| <0x4a000800 0x800>, |
| <0x4a001000 0x400>; |
| reg-names = "ap", "la", "ia0"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0x00000000 0x4a000000 0x1000000>; /* segment 0 */ |
| |
| segment@0 { /* 0x4a000000 */ |
| compatible = "simple-bus"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ |
| <0x00000800 0x00000800 0x000800>, /* ap 1 */ |
| <0x00001000 0x00001000 0x000400>, /* ap 2 */ |
| <0x00100000 0x00100000 0x008000>, /* ap 3 */ |
| <0x00108000 0x00108000 0x001000>, /* ap 4 */ |
| <0x00400000 0x00400000 0x002000>, /* ap 5 */ |
| <0x00402000 0x00402000 0x001000>, /* ap 6 */ |
| <0x00200000 0x00200000 0x080000>, /* ap 7 */ |
| <0x00280000 0x00280000 0x001000>; /* ap 8 */ |
| |
| target-module@100000 { /* 0x4a100000, ap 3 04.0 */ |
| compatible = "ti,sysc-omap4-simple", "ti,sysc"; |
| reg = <0x101200 0x4>, |
| <0x101208 0x4>, |
| <0x101204 0x4>; |
| reg-names = "rev", "sysc", "syss"; |
| ti,sysc-mask = <0>; |
| ti,sysc-midle = <SYSC_IDLE_FORCE>, |
| <SYSC_IDLE_NO>; |
| ti,sysc-sidle = <SYSC_IDLE_FORCE>, |
| <SYSC_IDLE_NO>; |
| ti,syss-mask = <1>; |
| clocks = <&cpsw_125mhz_clkctrl AM4_CPSW_125MHZ_CPGMAC0_CLKCTRL 0>; |
| clock-names = "fck"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0x0 0x100000 0x8000>; |
| |
| mac: ethernet@0 { |
| compatible = "ti,am4372-cpsw","ti,cpsw"; |
| reg = <0x0 0x800 |
| 0x1200 0x100>; |
| interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| clocks = <&cpsw_125mhz_gclk>, <&cpsw_cpts_rft_clk>, |
| <&dpll_clksel_mac_clk>; |
| clock-names = "fck", "cpts", "50mclk"; |
| assigned-clocks = <&dpll_clksel_mac_clk>; |
| assigned-clock-rates = <50000000>; |
| status = "disabled"; |
| cpdma_channels = <8>; |
| ale_entries = <1024>; |
| bd_ram_size = <0x2000>; |
| mac_control = <0x20>; |
| slaves = <2>; |
| active_slave = <0>; |
| cpts_clock_mult = <0x80000000>; |
| cpts_clock_shift = <29>; |
| ranges = <0 0 0x8000>; |
| syscon = <&scm_conf>; |
| |
| davinci_mdio: mdio@1000 { |
| compatible = "ti,am4372-mdio","ti,cpsw-mdio","ti,davinci_mdio"; |
| reg = <0x1000 0x100>; |
| clocks = <&cpsw_125mhz_clkctrl AM4_CPSW_125MHZ_CPGMAC0_CLKCTRL 0>; |
| clock-names = "fck"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| bus_freq = <1000000>; |
| status = "disabled"; |
| }; |
| |
| cpsw_emac0: slave@200 { |
| /* Filled in by U-Boot */ |
| mac-address = [ 00 00 00 00 00 00 ]; |
| phys = <&phy_gmii_sel 1 0>; |
| }; |
| |
| cpsw_emac1: slave@300 { |
| /* Filled in by U-Boot */ |
| mac-address = [ 00 00 00 00 00 00 ]; |
| phys = <&phy_gmii_sel 2 0>; |
| }; |
| }; |
| }; |
| |
| target-module@200000 { /* 0x4a200000, ap 7 02.0 */ |
| compatible = "ti,sysc"; |
| status = "disabled"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0x0 0x200000 0x80000>; |
| }; |
| |
| target-module@400000 { /* 0x4a400000, ap 5 08.0 */ |
| compatible = "ti,sysc"; |
| status = "disabled"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0x0 0x400000 0x2000>; |
| }; |
| }; |
| }; |
| |
| &l4_per { /* 0x48000000 */ |
| compatible = "ti,am4-l4-per", "simple-bus"; |
| reg = <0x48000000 0x800>, |
| <0x48000800 0x800>, |
| <0x48001000 0x400>, |
| <0x48001400 0x400>, |
| <0x48001800 0x400>, |
| <0x48001c00 0x400>; |
| reg-names = "ap", "la", "ia0", "ia1", "ia2", "ia3"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0x00000000 0x48000000 0x100000>, /* segment 0 */ |
| <0x00100000 0x48100000 0x100000>, /* segment 1 */ |
| <0x00200000 0x48200000 0x100000>, /* segment 2 */ |
| <0x00300000 0x48300000 0x100000>, /* segment 3 */ |
| <0x46000000 0x46000000 0x400000>, /* l3 data port */ |
| <0x46400000 0x46400000 0x400000>; /* l3 data port */ |
| |
| segment@0 { /* 0x48000000 */ |
| compatible = "simple-bus"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ |
| <0x00000800 0x00000800 0x000800>, /* ap 1 */ |
| <0x00001000 0x00001000 0x000400>, /* ap 2 */ |
| <0x00001400 0x00001400 0x000400>, /* ap 3 */ |
| <0x00001800 0x00001800 0x000400>, /* ap 4 */ |
| <0x00001c00 0x00001c00 0x000400>, /* ap 5 */ |
| <0x00008000 0x00008000 0x001000>, /* ap 6 */ |
| <0x00009000 0x00009000 0x001000>, /* ap 7 */ |
| <0x00022000 0x00022000 0x001000>, /* ap 8 */ |
| <0x00023000 0x00023000 0x001000>, /* ap 9 */ |
| <0x00024000 0x00024000 0x001000>, /* ap 10 */ |
| <0x00025000 0x00025000 0x001000>, /* ap 11 */ |
| <0x0002a000 0x0002a000 0x001000>, /* ap 12 */ |
| <0x0002b000 0x0002b000 0x001000>, /* ap 13 */ |
| <0x00038000 0x00038000 0x002000>, /* ap 14 */ |
| <0x0003a000 0x0003a000 0x001000>, /* ap 15 */ |
| <0x0003c000 0x0003c000 0x002000>, /* ap 16 */ |
| <0x0003e000 0x0003e000 0x001000>, /* ap 17 */ |
| <0x00040000 0x00040000 0x001000>, /* ap 18 */ |
| <0x00041000 0x00041000 0x001000>, /* ap 19 */ |
| <0x00042000 0x00042000 0x001000>, /* ap 20 */ |
| <0x00043000 0x00043000 0x001000>, /* ap 21 */ |
| <0x00044000 0x00044000 0x001000>, /* ap 22 */ |
| <0x00045000 0x00045000 0x001000>, /* ap 23 */ |
| <0x00046000 0x00046000 0x001000>, /* ap 24 */ |
| <0x00047000 0x00047000 0x001000>, /* ap 25 */ |
| <0x00048000 0x00048000 0x001000>, /* ap 26 */ |
| <0x00049000 0x00049000 0x001000>, /* ap 27 */ |
| <0x0004c000 0x0004c000 0x001000>, /* ap 28 */ |
| <0x0004d000 0x0004d000 0x001000>, /* ap 29 */ |
| <0x00060000 0x00060000 0x001000>, /* ap 30 */ |
| <0x00061000 0x00061000 0x001000>, /* ap 31 */ |
| <0x00080000 0x00080000 0x010000>, /* ap 32 */ |
| <0x00090000 0x00090000 0x001000>, /* ap 33 */ |
| <0x00030000 0x00030000 0x001000>, /* ap 65 */ |
| <0x00031000 0x00031000 0x001000>, /* ap 66 */ |
| <0x0004a000 0x0004a000 0x001000>, /* ap 71 */ |
| <0x0004b000 0x0004b000 0x001000>, /* ap 72 */ |
| <0x000c8000 0x000c8000 0x001000>, /* ap 73 */ |
| <0x000c9000 0x000c9000 0x001000>, /* ap 74 */ |
| <0x000ca000 0x000ca000 0x001000>, /* ap 77 */ |
| <0x000cb000 0x000cb000 0x001000>, /* ap 78 */ |
| <0x00034000 0x00034000 0x001000>, /* ap 80 */ |
| <0x00035000 0x00035000 0x001000>, /* ap 81 */ |
| <0x00036000 0x00036000 0x001000>, /* ap 84 */ |
| <0x00037000 0x00037000 0x001000>, /* ap 85 */ |
| <0x46000000 0x46000000 0x400000>, /* l3 data port */ |
| <0x46400000 0x46400000 0x400000>; /* l3 data port */ |
| |
| target-module@8000 { /* 0x48008000, ap 6 10.0 */ |
| compatible = "ti,sysc"; |
| status = "disabled"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0x0 0x8000 0x1000>; |
| }; |
| |
| target-module@22000 { /* 0x48022000, ap 8 0a.0 */ |
| compatible = "ti,sysc-omap2", "ti,sysc"; |
| reg = <0x22050 0x4>, |
| <0x22054 0x4>, |
| <0x22058 0x4>; |
| reg-names = "rev", "sysc", "syss"; |
| ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | |
| SYSC_OMAP2_SOFTRESET | |
| SYSC_OMAP2_AUTOIDLE)>; |
| ti,sysc-sidle = <SYSC_IDLE_FORCE>, |
| <SYSC_IDLE_NO>, |
| <SYSC_IDLE_SMART>, |
| <SYSC_IDLE_SMART_WKUP>; |
| /* Domains (P, C): per_pwrdm, l4ls_clkdm */ |
| clocks = <&l4ls_clkctrl AM4_L4LS_UART2_CLKCTRL 0>; |
| clock-names = "fck"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0x0 0x22000 0x1000>; |
| |
| uart1: serial@0 { |
| compatible = "ti,am4372-uart","ti,omap2-uart"; |
| reg = <0x0 0x2000>; |
| interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; |
| status = "disabled"; |
| }; |
| }; |
| |
| target-module@24000 { /* 0x48024000, ap 10 1c.0 */ |
| compatible = "ti,sysc-omap2", "ti,sysc"; |
| reg = <0x24050 0x4>, |
| <0x24054 0x4>, |
| <0x24058 0x4>; |
| reg-names = "rev", "sysc", "syss"; |
| ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | |
| SYSC_OMAP2_SOFTRESET | |
| SYSC_OMAP2_AUTOIDLE)>; |
| ti,sysc-sidle = <SYSC_IDLE_FORCE>, |
| <SYSC_IDLE_NO>, |
| <SYSC_IDLE_SMART>, |
| <SYSC_IDLE_SMART_WKUP>; |
| /* Domains (P, C): per_pwrdm, l4ls_clkdm */ |
| clocks = <&l4ls_clkctrl AM4_L4LS_UART3_CLKCTRL 0>; |
| clock-names = "fck"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0x0 0x24000 0x1000>; |
| |
| uart2: serial@0 { |
| compatible = "ti,am4372-uart","ti,omap2-uart"; |
| reg = <0x0 0x2000>; |
| interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; |
| status = "disabled"; |
| }; |
| }; |
| |
| target-module@2a000 { /* 0x4802a000, ap 12 22.0 */ |
| compatible = "ti,sysc-omap2", "ti,sysc"; |
| reg = <0x2a000 0x8>, |
| <0x2a010 0x8>, |
| <0x2a090 0x8>; |
| reg-names = "rev", "sysc", "syss"; |
| ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | |
| SYSC_OMAP2_ENAWAKEUP | |
| SYSC_OMAP2_SOFTRESET | |
| SYSC_OMAP2_AUTOIDLE)>; |
| ti,sysc-sidle = <SYSC_IDLE_FORCE>, |
| <SYSC_IDLE_NO>, |
| <SYSC_IDLE_SMART>, |
| <SYSC_IDLE_SMART_WKUP>; |
| ti,syss-mask = <1>; |
| /* Domains (P, C): per_pwrdm, l4ls_clkdm */ |
| clocks = <&l4ls_clkctrl AM4_L4LS_I2C2_CLKCTRL 0>; |
| clock-names = "fck"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0x0 0x2a000 0x1000>; |
| |
| i2c1: i2c@0 { |
| compatible = "ti,am4372-i2c","ti,omap4-i2c"; |
| reg = <0x0 0x1000>; |
| interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| }; |
| |
| target-module@30000 { /* 0x48030000, ap 65 08.0 */ |
| compatible = "ti,sysc-omap2", "ti,sysc"; |
| reg = <0x30000 0x4>, |
| <0x30110 0x4>, |
| <0x30114 0x4>; |
| reg-names = "rev", "sysc", "syss"; |
| ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | |
| SYSC_OMAP2_SOFTRESET | |
| SYSC_OMAP2_AUTOIDLE)>; |
| ti,sysc-sidle = <SYSC_IDLE_FORCE>, |
| <SYSC_IDLE_NO>, |
| <SYSC_IDLE_SMART>; |
| ti,syss-mask = <1>; |
| /* Domains (P, C): per_pwrdm, l4ls_clkdm */ |
| clocks = <&l4ls_clkctrl AM4_L4LS_SPI0_CLKCTRL 0>; |
| clock-names = "fck"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0x0 0x30000 0x1000>; |
| |
| spi0: spi@0 { |
| compatible = "ti,am4372-mcspi","ti,omap4-mcspi"; |
| reg = <0x0 0x400>; |
| interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| }; |
| |
| target-module@34000 { /* 0x48034000, ap 80 56.0 */ |
| compatible = "ti,sysc"; |
| status = "disabled"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0x0 0x34000 0x1000>; |
| }; |
| |
| target-module@36000 { /* 0x48036000, ap 84 3e.0 */ |
| compatible = "ti,sysc"; |
| status = "disabled"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0x0 0x36000 0x1000>; |
| }; |
| |
| target-module@38000 { /* 0x48038000, ap 14 04.0 */ |
| compatible = "ti,sysc-omap4-simple", "ti,sysc"; |
| reg = <0x38000 0x4>, |
| <0x38004 0x4>; |
| reg-names = "rev", "sysc"; |
| ti,sysc-sidle = <SYSC_IDLE_FORCE>, |
| <SYSC_IDLE_NO>, |
| <SYSC_IDLE_SMART>; |
| /* Domains (P, C): per_pwrdm, l3s_clkdm */ |
| clocks = <&l3s_clkctrl AM4_L3S_MCASP0_CLKCTRL 0>; |
| clock-names = "fck"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0x0 0x38000 0x2000>, |
| <0x46000000 0x46000000 0x400000>; |
| |
| mcasp0: mcasp@0 { |
| compatible = "ti,am33xx-mcasp-audio"; |
| reg = <0x0 0x2000>, |
| <0x46000000 0x400000>; |
| reg-names = "mpu", "dat"; |
| interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "tx", "rx"; |
| status = "disabled"; |
| dmas = <&edma 8 2>, |
| <&edma 9 2>; |
| dma-names = "tx", "rx"; |
| }; |
| }; |
| |
| target-module@3c000 { /* 0x4803c000, ap 16 2a.0 */ |
| compatible = "ti,sysc-omap4-simple", "ti,sysc"; |
| reg = <0x3c000 0x4>, |
| <0x3c004 0x4>; |
| reg-names = "rev", "sysc"; |
| ti,sysc-sidle = <SYSC_IDLE_FORCE>, |
| <SYSC_IDLE_NO>, |
| <SYSC_IDLE_SMART>; |
| /* Domains (P, C): per_pwrdm, l3s_clkdm */ |
| clocks = <&l3s_clkctrl AM4_L3S_MCASP1_CLKCTRL 0>; |
| clock-names = "fck"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0x0 0x3c000 0x2000>, |
| <0x46400000 0x46400000 0x400000>; |
| |
| mcasp1: mcasp@0 { |
| compatible = "ti,am33xx-mcasp-audio"; |
| reg = <0x0 0x2000>, |
| <0x46400000 0x400000>; |
| reg-names = "mpu", "dat"; |
| interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "tx", "rx"; |
| status = "disabled"; |
| dmas = <&edma 10 2>, |
| <&edma 11 2>; |
| dma-names = "tx", "rx"; |
| }; |
| }; |
| |
| timer2_target: target-module@40000 { /* 0x48040000, ap 18 1e.0 */ |
| compatible = "ti,sysc-omap4-timer", "ti,sysc"; |
| reg = <0x40000 0x4>, |
| <0x40010 0x4>, |
| <0x40014 0x4>; |
| reg-names = "rev", "sysc", "syss"; |
| ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; |
| ti,sysc-sidle = <SYSC_IDLE_FORCE>, |
| <SYSC_IDLE_NO>, |
| <SYSC_IDLE_SMART>, |
| <SYSC_IDLE_SMART_WKUP>; |
| /* Domains (P, C): per_pwrdm, l4ls_clkdm */ |
| clocks = <&l4ls_clkctrl AM4_L4LS_TIMER2_CLKCTRL 0>; |
| clock-names = "fck"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0x0 0x40000 0x1000>; |
| |
| timer2: timer@0 { |
| compatible = "ti,am4372-timer","ti,am335x-timer"; |
| reg = <0x0 0x400>; |
| interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&timer2_fck>; |
| clock-names = "fck"; |
| }; |
| }; |
| |
| target-module@42000 { /* 0x48042000, ap 20 24.0 */ |
| compatible = "ti,sysc-omap4-timer", "ti,sysc"; |
| reg = <0x42000 0x4>, |
| <0x42010 0x4>, |
| <0x42014 0x4>; |
| reg-names = "rev", "sysc", "syss"; |
| ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; |
| ti,sysc-sidle = <SYSC_IDLE_FORCE>, |
| <SYSC_IDLE_NO>, |
| <SYSC_IDLE_SMART>, |
| <SYSC_IDLE_SMART_WKUP>; |
| /* Domains (P, C): per_pwrdm, l4ls_clkdm */ |
| clocks = <&l4ls_clkctrl AM4_L4LS_TIMER3_CLKCTRL 0>; |
| clock-names = "fck"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0x0 0x42000 0x1000>; |
| |
| timer3: timer@0 { |
| compatible = "ti,am4372-timer","ti,am335x-timer"; |
| reg = <0x0 0x400>; |
| interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; |
| status = "disabled"; |
| }; |
| }; |
| |
| target-module@44000 { /* 0x48044000, ap 22 26.0 */ |
| compatible = "ti,sysc-omap4-timer", "ti,sysc"; |
| reg = <0x44000 0x4>, |
| <0x44010 0x4>, |
| <0x44014 0x4>; |
| reg-names = "rev", "sysc", "syss"; |
| ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; |
| ti,sysc-sidle = <SYSC_IDLE_FORCE>, |
| <SYSC_IDLE_NO>, |
| <SYSC_IDLE_SMART>, |
| <SYSC_IDLE_SMART_WKUP>; |
| /* Domains (P, C): per_pwrdm, l4ls_clkdm */ |
| clocks = <&l4ls_clkctrl AM4_L4LS_TIMER4_CLKCTRL 0>; |
| clock-names = "fck"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0x0 0x44000 0x1000>; |
| |
| timer4: timer@0 { |
| compatible = "ti,am4372-timer","ti,am335x-timer"; |
| reg = <0x0 0x400>; |
| interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; |
| ti,timer-pwm; |
| status = "disabled"; |
| }; |
| }; |
| |
| target-module@46000 { /* 0x48046000, ap 24 28.0 */ |
| compatible = "ti,sysc-omap4-timer", "ti,sysc"; |
| reg = <0x46000 0x4>, |
| <0x46010 0x4>, |
| <0x46014 0x4>; |
| reg-names = "rev", "sysc", "syss"; |
| ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; |
| ti,sysc-sidle = <SYSC_IDLE_FORCE>, |
| <SYSC_IDLE_NO>, |
| <SYSC_IDLE_SMART>, |
| <SYSC_IDLE_SMART_WKUP>; |
| /* Domains (P, C): per_pwrdm, l4ls_clkdm */ |
| clocks = <&l4ls_clkctrl AM4_L4LS_TIMER5_CLKCTRL 0>; |
| clock-names = "fck"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0x0 0x46000 0x1000>; |
| |
| timer5: timer@0 { |
| compatible = "ti,am4372-timer","ti,am335x-timer"; |
| reg = <0x0 0x400>; |
| interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; |
| ti,timer-pwm; |
| status = "disabled"; |
| }; |
| }; |
| |
| target-module@48000 { /* 0x48048000, ap 26 1a.0 */ |
| compatible = "ti,sysc-omap4-timer", "ti,sysc"; |
| reg = <0x48000 0x4>, |
| <0x48010 0x4>, |
| <0x48014 0x4>; |
| reg-names = "rev", "sysc", "syss"; |
| ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; |
| ti,sysc-sidle = <SYSC_IDLE_FORCE>, |
| <SYSC_IDLE_NO>, |
| <SYSC_IDLE_SMART>, |
| <SYSC_IDLE_SMART_WKUP>; |
| /* Domains (P, C): per_pwrdm, l4ls_clkdm */ |
| clocks = <&l4ls_clkctrl AM4_L4LS_TIMER6_CLKCTRL 0>; |
| clock-names = "fck"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0x0 0x48000 0x1000>; |
| |
| timer6: timer@0 { |
| compatible = "ti,am4372-timer","ti,am335x-timer"; |
| reg = <0x0 0x400>; |
| interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; |
| ti,timer-pwm; |
| status = "disabled"; |
| }; |
| }; |
| |
| target-module@4a000 { /* 0x4804a000, ap 71 48.0 */ |
| compatible = "ti,sysc-omap4-timer", "ti,sysc"; |
| reg = <0x4a000 0x4>, |
| <0x4a010 0x4>, |
| <0x4a014 0x4>; |
| reg-names = "rev", "sysc", "syss"; |
| ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; |
| ti,sysc-sidle = <SYSC_IDLE_FORCE>, |
| <SYSC_IDLE_NO>, |
| <SYSC_IDLE_SMART>, |
| <SYSC_IDLE_SMART_WKUP>; |
| /* Domains (P, C): per_pwrdm, l4ls_clkdm */ |
| clocks = <&l4ls_clkctrl AM4_L4LS_TIMER7_CLKCTRL 0>; |
| clock-names = "fck"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0x0 0x4a000 0x1000>; |
| |
| timer7: timer@0 { |
| compatible = "ti,am4372-timer","ti,am335x-timer"; |
| reg = <0x0 0x400>; |
| interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; |
| ti,timer-pwm; |
| status = "disabled"; |
| }; |
| }; |
| |
| target-module@4c000 { /* 0x4804c000, ap 28 36.0 */ |
| compatible = "ti,sysc-omap2", "ti,sysc"; |
| reg = <0x4c000 0x4>, |
| <0x4c010 0x4>, |
| <0x4c114 0x4>; |
| reg-names = "rev", "sysc", "syss"; |
| ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | |
| SYSC_OMAP2_SOFTRESET | |
| SYSC_OMAP2_AUTOIDLE)>; |
| ti,sysc-sidle = <SYSC_IDLE_FORCE>, |
| <SYSC_IDLE_NO>, |
| <SYSC_IDLE_SMART>, |
| <SYSC_IDLE_SMART_WKUP>; |
| ti,syss-mask = <1>; |
| /* Domains (P, C): per_pwrdm, l4ls_clkdm */ |
| clocks = <&l4ls_clkctrl AM4_L4LS_GPIO2_CLKCTRL 0>, |
| <&l4ls_clkctrl AM4_L4LS_GPIO2_CLKCTRL 8>; |
| clock-names = "fck", "dbclk"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0x0 0x4c000 0x1000>; |
| |
| gpio1: gpio@0 { |
| compatible = "ti,am4372-gpio","ti,omap4-gpio"; |
| reg = <0x0 0x1000>; |
| interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| status = "disabled"; |
| }; |
| }; |
| |
| target-module@60000 { /* 0x48060000, ap 30 14.0 */ |
| compatible = "ti,sysc-omap2", "ti,sysc"; |
| reg = <0x602fc 0x4>, |
| <0x60110 0x4>, |
| <0x60114 0x4>; |
| reg-names = "rev", "sysc", "syss"; |
| ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | |
| SYSC_OMAP2_ENAWAKEUP | |
| SYSC_OMAP2_SOFTRESET | |
| SYSC_OMAP2_AUTOIDLE)>; |
| ti,sysc-sidle = <SYSC_IDLE_FORCE>, |
| <SYSC_IDLE_NO>, |
| <SYSC_IDLE_SMART>; |
| ti,syss-mask = <1>; |
| /* Domains (P, C): per_pwrdm, l4ls_clkdm */ |
| clocks = <&l4ls_clkctrl AM4_L4LS_MMC1_CLKCTRL 0>; |
| clock-names = "fck"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0x0 0x60000 0x1000>; |
| |
| mmc1: mmc@0 { |
| compatible = "ti,am437-sdhci"; |
| reg = <0x0 0x1000>; |
| ti,needs-special-reset; |
| dmas = <&edma 24 0>, |
| <&edma 25 0>; |
| dma-names = "tx", "rx"; |
| interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; |
| status = "disabled"; |
| }; |
| }; |
| |
| target-module@80000 { /* 0x48080000, ap 32 18.0 */ |
| compatible = "ti,sysc-omap2", "ti,sysc"; |
| reg = <0x80000 0x4>, |
| <0x80010 0x4>, |
| <0x80014 0x4>; |
| reg-names = "rev", "sysc", "syss"; |
| ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | |
| SYSC_OMAP2_SOFTRESET | |
| SYSC_OMAP2_AUTOIDLE)>; |
| ti,sysc-sidle = <SYSC_IDLE_FORCE>, |
| <SYSC_IDLE_NO>, |
| <SYSC_IDLE_SMART>; |
| ti,syss-mask = <1>; |
| /* Domains (P, C): per_pwrdm, l4ls_clkdm */ |
| clocks = <&l4ls_clkctrl AM4_L4LS_ELM_CLKCTRL 0>; |
| clock-names = "fck"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0x0 0x80000 0x10000>; |
| |
| elm: elm@0 { |
| compatible = "ti,am3352-elm"; |
| reg = <0x0 0x2000>; |
| interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&l4ls_gclk>; |
| clock-names = "fck"; |
| status = "disabled"; |
| }; |
| }; |
| |
| target-module@c8000 { /* 0x480c8000, ap 73 06.0 */ |
| compatible = "ti,sysc-omap4", "ti,sysc"; |
| reg = <0xc8000 0x4>, |
| <0xc8010 0x4>; |
| reg-names = "rev", "sysc"; |
| ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; |
| ti,sysc-sidle = <SYSC_IDLE_FORCE>, |
| <SYSC_IDLE_NO>, |
| <SYSC_IDLE_SMART>; |
| /* Domains (P, C): per_pwrdm, l4ls_clkdm */ |
| clocks = <&l4ls_clkctrl AM4_L4LS_MAILBOX_CLKCTRL 0>; |
| clock-names = "fck"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0x0 0xc8000 0x1000>; |
| |
| mailbox: mailbox@0 { |
| compatible = "ti,omap4-mailbox"; |
| reg = <0x0 0x200>; |
| interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; |
| #mbox-cells = <1>; |
| ti,mbox-num-users = <4>; |
| ti,mbox-num-fifos = <8>; |
| mbox_wkupm3: wkup_m3 { |
| ti,mbox-send-noirq; |
| ti,mbox-tx = <0 0 0>; |
| ti,mbox-rx = <0 0 3>; |
| }; |
| }; |
| }; |
| |
| target-module@ca000 { /* 0x480ca000, ap 77 38.0 */ |
| compatible = "ti,sysc-omap2", "ti,sysc"; |
| reg = <0xca000 0x4>, |
| <0xca010 0x4>, |
| <0xca014 0x4>; |
| reg-names = "rev", "sysc", "syss"; |
| ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | |
| SYSC_OMAP2_ENAWAKEUP | |
| SYSC_OMAP2_SOFTRESET | |
| SYSC_OMAP2_AUTOIDLE)>; |
| ti,sysc-sidle = <SYSC_IDLE_FORCE>, |
| <SYSC_IDLE_NO>, |
| <SYSC_IDLE_SMART>; |
| ti,syss-mask = <1>; |
| /* Domains (P, C): per_pwrdm, l4ls_clkdm */ |
| clocks = <&l4ls_clkctrl AM4_L4LS_SPINLOCK_CLKCTRL 0>; |
| clock-names = "fck"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0x0 0xca000 0x1000>; |
| |
| hwspinlock: spinlock@0 { |
| compatible = "ti,omap4-hwspinlock"; |
| reg = <0x0 0x1000>; |
| #hwlock-cells = <1>; |
| }; |
| }; |
| }; |
| |
| segment@100000 { /* 0x48100000 */ |
| compatible = "simple-bus"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0x0008c000 0x0018c000 0x001000>, /* ap 34 */ |
| <0x0008d000 0x0018d000 0x001000>, /* ap 35 */ |
| <0x0008e000 0x0018e000 0x001000>, /* ap 36 */ |
| <0x0008f000 0x0018f000 0x001000>, /* ap 37 */ |
| <0x0009c000 0x0019c000 0x001000>, /* ap 38 */ |
| <0x0009d000 0x0019d000 0x001000>, /* ap 39 */ |
| <0x000a6000 0x001a6000 0x001000>, /* ap 40 */ |
| <0x000a7000 0x001a7000 0x001000>, /* ap 41 */ |
| <0x000a8000 0x001a8000 0x001000>, /* ap 42 */ |
| <0x000a9000 0x001a9000 0x001000>, /* ap 43 */ |
| <0x000aa000 0x001aa000 0x001000>, /* ap 44 */ |
| <0x000ab000 0x001ab000 0x001000>, /* ap 45 */ |
| <0x000ac000 0x001ac000 0x001000>, /* ap 46 */ |
| <0x000ad000 0x001ad000 0x001000>, /* ap 47 */ |
| <0x000ae000 0x001ae000 0x001000>, /* ap 48 */ |
| <0x000af000 0x001af000 0x001000>, /* ap 49 */ |
| <0x000cc000 0x001cc000 0x002000>, /* ap 50 */ |
| <0x000ce000 0x001ce000 0x002000>, /* ap 51 */ |
| <0x000d0000 0x001d0000 0x002000>, /* ap 52 */ |
| <0x000d2000 0x001d2000 0x002000>, /* ap 53 */ |
| <0x000d8000 0x001d8000 0x001000>, /* ap 54 */ |
| <0x000d9000 0x001d9000 0x001000>, /* ap 55 */ |
| <0x000a0000 0x001a0000 0x001000>, /* ap 67 */ |
| <0x000a1000 0x001a1000 0x001000>, /* ap 68 */ |
| <0x000a2000 0x001a2000 0x001000>, /* ap 69 */ |
| <0x000a3000 0x001a3000 0x001000>, /* ap 70 */ |
| <0x000a4000 0x001a4000 0x001000>, /* ap 92 */ |
| <0x000a5000 0x001a5000 0x001000>, /* ap 93 */ |
| <0x000c1000 0x001c1000 0x001000>, /* ap 94 */ |
| <0x000c2000 0x001c2000 0x001000>; /* ap 95 */ |
| |
| target-module@8c000 { /* 0x4818c000, ap 34 0c.0 */ |
| compatible = "ti,sysc"; |
| status = "disabled"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0x0 0x8c000 0x1000>; |
| }; |
| |
| target-module@8e000 { /* 0x4818e000, ap 36 02.0 */ |
| compatible = "ti,sysc"; |
| status = "disabled"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0x0 0x8e000 0x1000>; |
| }; |
| |
| target-module@9c000 { /* 0x4819c000, ap 38 52.0 */ |
| compatible = "ti,sysc-omap2", "ti,sysc"; |
| reg = <0x9c000 0x8>, |
| <0x9c010 0x8>, |
| <0x9c090 0x8>; |
| reg-names = "rev", "sysc", "syss"; |
| ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | |
| SYSC_OMAP2_ENAWAKEUP | |
| SYSC_OMAP2_SOFTRESET | |
| SYSC_OMAP2_AUTOIDLE)>; |
| ti,sysc-sidle = <SYSC_IDLE_FORCE>, |
| <SYSC_IDLE_NO>, |
| <SYSC_IDLE_SMART>, |
| <SYSC_IDLE_SMART_WKUP>; |
| ti,syss-mask = <1>; |
| /* Domains (P, C): per_pwrdm, l4ls_clkdm */ |
| clocks = <&l4ls_clkctrl AM4_L4LS_I2C3_CLKCTRL 0>; |
| clock-names = "fck"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0x0 0x9c000 0x1000>; |
| |
| i2c2: i2c@0 { |
| compatible = "ti,am4372-i2c","ti,omap4-i2c"; |
| reg = <0x0 0x1000>; |
| interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| }; |
| |
| target-module@a0000 { /* 0x481a0000, ap 67 2c.0 */ |
| compatible = "ti,sysc-omap2", "ti,sysc"; |
| reg = <0xa0000 0x4>, |
| <0xa0110 0x4>, |
| <0xa0114 0x4>; |
| reg-names = "rev", "sysc", "syss"; |
| ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | |
| SYSC_OMAP2_SOFTRESET | |
| SYSC_OMAP2_AUTOIDLE)>; |
| ti,sysc-sidle = <SYSC_IDLE_FORCE>, |
| <SYSC_IDLE_NO>, |
| <SYSC_IDLE_SMART>; |
| ti,syss-mask = <1>; |
| /* Domains (P, C): per_pwrdm, l4ls_clkdm */ |
| clocks = <&l4ls_clkctrl AM4_L4LS_SPI1_CLKCTRL 0>; |
| clock-names = "fck"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0x0 0xa0000 0x1000>; |
| |
| spi1: spi@0 { |
| compatible = "ti,am4372-mcspi","ti,omap4-mcspi"; |
| reg = <0x0 0x400>; |
| interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| }; |
| |
| target-module@a2000 { /* 0x481a2000, ap 69 2e.0 */ |
| compatible = "ti,sysc-omap2", "ti,sysc"; |
| reg = <0xa2000 0x4>, |
| <0xa2110 0x4>, |
| <0xa2114 0x4>; |
| reg-names = "rev", "sysc", "syss"; |
| ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | |
| SYSC_OMAP2_SOFTRESET | |
| SYSC_OMAP2_AUTOIDLE)>; |
| ti,sysc-sidle = <SYSC_IDLE_FORCE>, |
| <SYSC_IDLE_NO>, |
| <SYSC_IDLE_SMART>; |
| ti,syss-mask = <1>; |
| /* Domains (P, C): per_pwrdm, l4ls_clkdm */ |
| clocks = <&l4ls_clkctrl AM4_L4LS_SPI2_CLKCTRL 0>; |
| clock-names = "fck"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0x0 0xa2000 0x1000>; |
| |
| spi2: spi@0 { |
| compatible = "ti,am4372-mcspi","ti,omap4-mcspi"; |
| reg = <0x0 0x400>; |
| interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| }; |
| |
| target-module@a4000 { /* 0x481a4000, ap 92 62.0 */ |
| compatible = "ti,sysc-omap2", "ti,sysc"; |
| reg = <0xa4000 0x4>, |
| <0xa4110 0x4>, |
| <0xa4114 0x4>; |
| reg-names = "rev", "sysc", "syss"; |
| ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | |
| SYSC_OMAP2_SOFTRESET | |
| SYSC_OMAP2_AUTOIDLE)>; |
| ti,sysc-sidle = <SYSC_IDLE_FORCE>, |
| <SYSC_IDLE_NO>, |
| <SYSC_IDLE_SMART>; |
| ti,syss-mask = <1>; |
| /* Domains (P, C): per_pwrdm, l4ls_clkdm */ |
| clocks = <&l4ls_clkctrl AM4_L4LS_SPI3_CLKCTRL 0>; |
| clock-names = "fck"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0x0 0xa4000 0x1000>; |
| |
| spi3: spi@0 { |
| compatible = "ti,am4372-mcspi","ti,omap4-mcspi"; |
| reg = <0x0 0x400>; |
| interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| }; |
| |
| target-module@a6000 { /* 0x481a6000, ap 40 16.0 */ |
| compatible = "ti,sysc-omap2", "ti,sysc"; |
| reg = <0xa6050 0x4>, |
| <0xa6054 0x4>, |
| <0xa6058 0x4>; |
| reg-names = "rev", "sysc", "syss"; |
| ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | |
| SYSC_OMAP2_SOFTRESET | |
| SYSC_OMAP2_AUTOIDLE)>; |
| ti,sysc-sidle = <SYSC_IDLE_FORCE>, |
| <SYSC_IDLE_NO>, |
| <SYSC_IDLE_SMART>, |
| <SYSC_IDLE_SMART_WKUP>; |
| /* Domains (P, C): per_pwrdm, l4ls_clkdm */ |
| clocks = <&l4ls_clkctrl AM4_L4LS_UART4_CLKCTRL 0>; |
| clock-names = "fck"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0x0 0xa6000 0x1000>; |
| |
| uart3: serial@0 { |
| compatible = "ti,am4372-uart","ti,omap2-uart"; |
| reg = <0x0 0x2000>; |
| interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; |
| status = "disabled"; |
| }; |
| }; |
| |
| target-module@a8000 { /* 0x481a8000, ap 42 20.0 */ |
| compatible = "ti,sysc-omap2", "ti,sysc"; |
| reg = <0xa8050 0x4>, |
| <0xa8054 0x4>, |
| <0xa8058 0x4>; |
| reg-names = "rev", "sysc", "syss"; |
| ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | |
| SYSC_OMAP2_SOFTRESET | |
| SYSC_OMAP2_AUTOIDLE)>; |
| ti,sysc-sidle = <SYSC_IDLE_FORCE>, |
| <SYSC_IDLE_NO>, |
| <SYSC_IDLE_SMART>, |
| <SYSC_IDLE_SMART_WKUP>; |
| /* Domains (P, C): per_pwrdm, l4ls_clkdm */ |
| clocks = <&l4ls_clkctrl AM4_L4LS_UART5_CLKCTRL 0>; |
| clock-names = "fck"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0x0 0xa8000 0x1000>; |
| |
| uart4: serial@0 { |
| compatible = "ti,am4372-uart","ti,omap2-uart"; |
| reg = <0x0 0x2000>; |
| interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; |
| status = "disabled"; |
| }; |
| }; |
| |
| target-module@aa000 { /* 0x481aa000, ap 44 12.0 */ |
| compatible = "ti,sysc-omap2", "ti,sysc"; |
| reg = <0xaa050 0x4>, |
| <0xaa054 0x4>, |
| <0xaa058 0x4>; |
| reg-names = "rev", "sysc", "syss"; |
| ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | |
| SYSC_OMAP2_SOFTRESET | |
| SYSC_OMAP2_AUTOIDLE)>; |
| ti,sysc-sidle = <SYSC_IDLE_FORCE>, |
| <SYSC_IDLE_NO>, |
| <SYSC_IDLE_SMART>, |
| <SYSC_IDLE_SMART_WKUP>; |
| /* Domains (P, C): per_pwrdm, l4ls_clkdm */ |
| clocks = <&l4ls_clkctrl AM4_L4LS_UART6_CLKCTRL 0>; |
| clock-names = "fck"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0x0 0xaa000 0x1000>; |
| |
| uart5: serial@0 { |
| compatible = "ti,am4372-uart","ti,omap2-uart"; |
| reg = <0x0 0x2000>; |
| interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; |
| status = "disabled"; |
| }; |
| }; |
| |
| target-module@ac000 { /* 0x481ac000, ap 46 30.0 */ |
| compatible = "ti,sysc-omap2", "ti,sysc"; |
| reg = <0xac000 0x4>, |
| <0xac010 0x4>, |
| <0xac114 0x4>; |
| reg-names = "rev", "sysc", "syss"; |
| ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | |
| SYSC_OMAP2_SOFTRESET | |
| SYSC_OMAP2_AUTOIDLE)>; |
| ti,sysc-sidle = <SYSC_IDLE_FORCE>, |
| <SYSC_IDLE_NO>, |
| <SYSC_IDLE_SMART>, |
| <SYSC_IDLE_SMART_WKUP>; |
| ti,syss-mask = <1>; |
| /* Domains (P, C): per_pwrdm, l4ls_clkdm */ |
| clocks = <&l4ls_clkctrl AM4_L4LS_GPIO3_CLKCTRL 0>, |
| <&l4ls_clkctrl AM4_L4LS_GPIO3_CLKCTRL 8>; |
| clock-names = "fck", "dbclk"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0x0 0xac000 0x1000>; |
| |
| gpio2: gpio@0 { |
| compatible = "ti,am4372-gpio","ti,omap4-gpio"; |
| reg = <0x0 0x1000>; |
| interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| status = "disabled"; |
| }; |
| }; |
| |
| target-module@ae000 { /* 0x481ae000, ap 48 32.0 */ |
| compatible = "ti,sysc-omap2", "ti,sysc"; |
| reg = <0xae000 0x4>, |
| <0xae010 0x4>, |
| <0xae114 0x4>; |
| reg-names = "rev", "sysc", "syss"; |
| ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | |
| SYSC_OMAP2_SOFTRESET | |
| SYSC_OMAP2_AUTOIDLE)>; |
| ti,sysc-sidle = <SYSC_IDLE_FORCE>, |
| <SYSC_IDLE_NO>, |
| <SYSC_IDLE_SMART>, |
| <SYSC_IDLE_SMART_WKUP>; |
| ti,syss-mask = <1>; |
| /* Domains (P, C): per_pwrdm, l4ls_clkdm */ |
| clocks = <&l4ls_clkctrl AM4_L4LS_GPIO4_CLKCTRL 0>, |
| <&l4ls_clkctrl AM4_L4LS_GPIO4_CLKCTRL 8>; |
| clock-names = "fck", "dbclk"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0x0 0xae000 0x1000>; |
| |
| gpio3: gpio@0 { |
| compatible = "ti,am4372-gpio","ti,omap4-gpio"; |
| reg = <0x0 0x1000>; |
| interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| status = "disabled"; |
| }; |
| }; |
| |
| target-module@c1000 { /* 0x481c1000, ap 94 68.0 */ |
| compatible = "ti,sysc-omap4-timer", "ti,sysc"; |
| reg = <0xc1000 0x4>, |
| <0xc1010 0x4>, |
| <0xc1014 0x4>; |
| reg-names = "rev", "sysc", "syss"; |
| ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; |
| ti,sysc-sidle = <SYSC_IDLE_FORCE>, |
| <SYSC_IDLE_NO>, |
| <SYSC_IDLE_SMART>, |
| <SYSC_IDLE_SMART_WKUP>; |
| /* Domains (P, C): per_pwrdm, l4ls_clkdm */ |
| clocks = <&l4ls_clkctrl AM4_L4LS_TIMER8_CLKCTRL 0>; |
| clock-names = "fck"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0x0 0xc1000 0x1000>; |
| |
| timer8: timer@0 { |
| compatible = "ti,am4372-timer","ti,am335x-timer"; |
| reg = <0x0 0x400>; |
| interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; |
| status = "disabled"; |
| }; |
| }; |
| |
| target-module@cc000 { /* 0x481cc000, ap 50 46.0 */ |
| compatible = "ti,sysc-omap4", "ti,sysc"; |
| reg = <0xcc020 0x4>; |
| reg-names = "rev"; |
| /* Domains (P, C): per_pwrdm, l4ls_clkdm */ |
| clocks = <&l4ls_clkctrl AM4_L4LS_D_CAN0_CLKCTRL 0>, |
| <&dcan0_fck>; |
| clock-names = "fck", "osc"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0x0 0xcc000 0x2000>; |
| |
| dcan0: can@0 { |
| compatible = "ti,am4372-d_can", "ti,am3352-d_can"; |
| reg = <0x0 0x2000>; |
| clocks = <&dcan0_fck>; |
| clock-names = "fck"; |
| syscon-raminit = <&scm_conf 0x644 0>; |
| interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; |
| status = "disabled"; |
| }; |
| }; |
| |
| target-module@d0000 { /* 0x481d0000, ap 52 3a.0 */ |
| compatible = "ti,sysc-omap4", "ti,sysc"; |
| reg = <0xd0020 0x4>; |
| reg-names = "rev"; |
| /* Domains (P, C): per_pwrdm, l4ls_clkdm */ |
| clocks = <&l4ls_clkctrl AM4_L4LS_D_CAN1_CLKCTRL 0>, |
| <&dcan1_fck>; |
| clock-names = "fck", "osc"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0x0 0xd0000 0x2000>; |
| |
| dcan1: can@0 { |
| compatible = "ti,am4372-d_can", "ti,am3352-d_can"; |
| reg = <0x0 0x2000>; |
| clocks = <&dcan1_fck>; |
| clock-name = "fck"; |
| syscon-raminit = <&scm_conf 0x644 1>; |
| interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; |
| status = "disabled"; |
| }; |
| }; |
| |
| target-module@d8000 { /* 0x481d8000, ap 54 5e.0 */ |
| compatible = "ti,sysc-omap2", "ti,sysc"; |
| reg = <0xd82fc 0x4>, |
| <0xd8110 0x4>, |
| <0xd8114 0x4>; |
| reg-names = "rev", "sysc", "syss"; |
| ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | |
| SYSC_OMAP2_ENAWAKEUP | |
| SYSC_OMAP2_SOFTRESET | |
| SYSC_OMAP2_AUTOIDLE)>; |
| ti,sysc-sidle = <SYSC_IDLE_FORCE>, |
| <SYSC_IDLE_NO>, |
| <SYSC_IDLE_SMART>; |
| ti,syss-mask = <1>; |
| /* Domains (P, C): per_pwrdm, l4ls_clkdm */ |
| clocks = <&l4ls_clkctrl AM4_L4LS_MMC2_CLKCTRL 0>; |
| clock-names = "fck"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0x0 0xd8000 0x1000>; |
| |
| mmc2: mmc@0 { |
| compatible = "ti,am437-sdhci"; |
| reg = <0x0 0x1000>; |
| ti,needs-special-reset; |
| dmas = <&edma 2 0>, |
| <&edma 3 0>; |
| dma-names = "tx", "rx"; |
| interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; |
| status = "disabled"; |
| }; |
| }; |
| }; |
| |
| segment@200000 { /* 0x48200000 */ |
| compatible = "simple-bus"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| }; |
| |
| segment@300000 { /* 0x48300000 */ |
| compatible = "simple-bus"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0x00000000 0x00300000 0x001000>, /* ap 56 */ |
| <0x00001000 0x00301000 0x001000>, /* ap 57 */ |
| <0x00002000 0x00302000 0x001000>, /* ap 58 */ |
| <0x00003000 0x00303000 0x001000>, /* ap 59 */ |
| <0x00004000 0x00304000 0x001000>, /* ap 60 */ |
| <0x00005000 0x00305000 0x001000>, /* ap 61 */ |
| <0x00018000 0x00318000 0x004000>, /* ap 62 */ |
| <0x0001c000 0x0031c000 0x001000>, /* ap 63 */ |
| <0x00010000 0x00310000 0x002000>, /* ap 64 */ |
| <0x00028000 0x00328000 0x001000>, /* ap 75 */ |
| <0x00029000 0x00329000 0x001000>, /* ap 76 */ |
| <0x00012000 0x00312000 0x001000>, /* ap 79 */ |
| <0x00020000 0x00320000 0x001000>, /* ap 82 */ |
| <0x00021000 0x00321000 0x001000>, /* ap 83 */ |
| <0x00026000 0x00326000 0x001000>, /* ap 86 */ |
| <0x00027000 0x00327000 0x001000>, /* ap 87 */ |
| <0x0002a000 0x0032a000 0x000400>, /* ap 88 */ |
| <0x0002c000 0x0032c000 0x001000>, /* ap 89 */ |
| <0x00013000 0x00313000 0x001000>, /* ap 90 */ |
| <0x00014000 0x00314000 0x001000>, /* ap 91 */ |
| <0x00006000 0x00306000 0x001000>, /* ap 96 */ |
| <0x00007000 0x00307000 0x001000>, /* ap 97 */ |
| <0x00008000 0x00308000 0x001000>, /* ap 98 */ |
| <0x00009000 0x00309000 0x001000>, /* ap 99 */ |
| <0x0000a000 0x0030a000 0x001000>, /* ap 100 */ |
| <0x0000b000 0x0030b000 0x001000>, /* ap 101 */ |
| <0x0003d000 0x0033d000 0x001000>, /* ap 102 */ |
| <0x0003e000 0x0033e000 0x001000>, /* ap 103 */ |
| <0x0003f000 0x0033f000 0x001000>, /* ap 104 */ |
| <0x00040000 0x00340000 0x001000>, /* ap 105 */ |
| <0x00041000 0x00341000 0x001000>, /* ap 106 */ |
| <0x00042000 0x00342000 0x001000>, /* ap 107 */ |
| <0x00045000 0x00345000 0x001000>, /* ap 108 */ |
| <0x00046000 0x00346000 0x001000>, /* ap 109 */ |
| <0x00047000 0x00347000 0x001000>, /* ap 110 */ |
| <0x00048000 0x00348000 0x001000>, /* ap 111 */ |
| <0x000f2000 0x003f2000 0x002000>, /* ap 112 */ |
| <0x000f4000 0x003f4000 0x001000>, /* ap 113 */ |
| <0x0004c000 0x0034c000 0x002000>, /* ap 114 */ |
| <0x0004e000 0x0034e000 0x001000>, /* ap 115 */ |
| <0x00022000 0x00322000 0x001000>, /* ap 116 */ |
| <0x00023000 0x00323000 0x001000>, /* ap 117 */ |
| <0x000f0000 0x003f0000 0x001000>, /* ap 118 */ |
| <0x0002a400 0x0032a400 0x000400>, /* ap 119 */ |
| <0x0002a800 0x0032a800 0x000400>, /* ap 120 */ |
| <0x0002ac00 0x0032ac00 0x000400>, /* ap 121 */ |
| <0x0002b000 0x0032b000 0x001000>, /* ap 122 */ |
| <0x00080000 0x00380000 0x020000>, /* ap 123 */ |
| <0x000a0000 0x003a0000 0x001000>, /* ap 124 */ |
| <0x000a8000 0x003a8000 0x008000>, /* ap 125 */ |
| <0x000b0000 0x003b0000 0x001000>, /* ap 126 */ |
| <0x000c0000 0x003c0000 0x020000>, /* ap 127 */ |
| <0x000e0000 0x003e0000 0x001000>, /* ap 128 */ |
| <0x000e8000 0x003e8000 0x008000>; /* ap 129 */ |
| |
| target-module@0 { /* 0x48300000, ap 56 40.0 */ |
| compatible = "ti,sysc-omap4", "ti,sysc"; |
| reg = <0x0 0x4>, |
| <0x4 0x4>; |
| reg-names = "rev", "sysc"; |
| ti,sysc-midle = <SYSC_IDLE_FORCE>, |
| <SYSC_IDLE_NO>, |
| <SYSC_IDLE_SMART>, |
| <SYSC_IDLE_SMART_WKUP>; |
| ti,sysc-sidle = <SYSC_IDLE_FORCE>, |
| <SYSC_IDLE_NO>, |
| <SYSC_IDLE_SMART>, |
| <SYSC_IDLE_SMART_WKUP>; |
| /* Domains (P, C): per_pwrdm, l4ls_clkdm */ |
| clocks = <&l4ls_clkctrl AM4_L4LS_EPWMSS0_CLKCTRL 0>; |
| clock-names = "fck"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0x0 0x0 0x1000>; |
| |
| epwmss0: epwmss@0 { |
| compatible = "ti,am4372-pwmss","ti,am33xx-pwmss"; |
| reg = <0x0 0x10>; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0 0 0x1000>; |
| status = "disabled"; |
| |
| ecap0: ecap@100 { |
| compatible = "ti,am4372-ecap", |
| "ti,am3352-ecap", |
| "ti,am33xx-ecap"; |
| #pwm-cells = <3>; |
| reg = <0x100 0x80>; |
| clocks = <&l4ls_gclk>; |
| clock-names = "fck"; |
| status = "disabled"; |
| }; |
| |
| ehrpwm0: pwm@200 { |
| compatible = "ti,am4372-ehrpwm", |
| "ti,am3352-ehrpwm", |
| "ti,am33xx-ehrpwm"; |
| #pwm-cells = <3>; |
| reg = <0x200 0x80>; |
| clocks = <&ehrpwm0_tbclk>, <&l4ls_gclk>; |
| clock-names = "tbclk", "fck"; |
| status = "disabled"; |
| }; |
| }; |
| }; |
| |
| target-module@2000 { /* 0x48302000, ap 58 4a.0 */ |
| compatible = "ti,sysc-omap4", "ti,sysc"; |
| reg = <0x2000 0x4>, |
| <0x2004 0x4>; |
| reg-names = "rev", "sysc"; |
| ti,sysc-midle = <SYSC_IDLE_FORCE>, |
| <SYSC_IDLE_NO>, |
| <SYSC_IDLE_SMART>, |
| <SYSC_IDLE_SMART_WKUP>; |
| ti,sysc-sidle = <SYSC_IDLE_FORCE>, |
| <SYSC_IDLE_NO>, |
| <SYSC_IDLE_SMART>, |
| <SYSC_IDLE_SMART_WKUP>; |
| /* Domains (P, C): per_pwrdm, l4ls_clkdm */ |
| clocks = <&l4ls_clkctrl AM4_L4LS_EPWMSS1_CLKCTRL 0>; |
| clock-names = "fck"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0x0 0x2000 0x1000>; |
| |
| epwmss1: epwmss@0 { |
| compatible = "ti,am4372-pwmss","ti,am33xx-pwmss"; |
| reg = <0x0 0x10>; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0 0 0x1000>; |
| status = "disabled"; |
| |
| ecap1: ecap@100 { |
| compatible = "ti,am4372-ecap", |
| "ti,am3352-ecap", |
| "ti,am33xx-ecap"; |
| #pwm-cells = <3>; |
| reg = <0x100 0x80>; |
| clocks = <&l4ls_gclk>; |
| clock-names = "fck"; |
| status = "disabled"; |
| }; |
| |
| ehrpwm1: pwm@200 { |
| compatible = "ti,am4372-ehrpwm", |
| "ti,am3352-ehrpwm", |
| "ti,am33xx-ehrpwm"; |
| #pwm-cells = <3>; |
| reg = <0x200 0x80>; |
| clocks = <&ehrpwm1_tbclk>, <&l4ls_gclk>; |
| clock-names = "tbclk", "fck"; |
| status = "disabled"; |
| }; |
| }; |
| }; |
| |
| target-module@4000 { /* 0x48304000, ap 60 44.0 */ |
| compatible = "ti,sysc-omap4", "ti,sysc"; |
| reg = <0x4000 0x4>, |
| <0x4004 0x4>; |
| reg-names = "rev", "sysc"; |
| ti,sysc-midle = <SYSC_IDLE_FORCE>, |
| <SYSC_IDLE_NO>, |
| <SYSC_IDLE_SMART>, |
| <SYSC_IDLE_SMART_WKUP>; |
| ti,sysc-sidle = <SYSC_IDLE_FORCE>, |
| <SYSC_IDLE_NO>, |
| <SYSC_IDLE_SMART>, |
| <SYSC_IDLE_SMART_WKUP>; |
| /* Domains (P, C): per_pwrdm, l4ls_clkdm */ |
| clocks = <&l4ls_clkctrl AM4_L4LS_EPWMSS2_CLKCTRL 0>; |
| clock-names = "fck"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0x0 0x4000 0x1000>; |
| |
| epwmss2: epwmss@0 { |
| compatible = "ti,am4372-pwmss","ti,am33xx-pwmss"; |
| reg = <0x0 0x10>; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0 0 0x1000>; |
| status = "disabled"; |
| |
| ecap2: ecap@100 { |
| compatible = "ti,am4372-ecap", |
| "ti,am3352-ecap", |
| "ti,am33xx-ecap"; |
| #pwm-cells = <3>; |
| reg = <0x100 0x80>; |
| clocks = <&l4ls_gclk>; |
| clock-names = "fck"; |
| status = "disabled"; |
| }; |
| |
| ehrpwm2: pwm@200 { |
| compatible = "ti,am4372-ehrpwm", |
| "ti,am3352-ehrpwm", |
| "ti,am33xx-ehrpwm"; |
| #pwm-cells = <3>; |
| reg = <0x200 0x80>; |
| clocks = <&ehrpwm2_tbclk>, <&l4ls_gclk>; |
| clock-names = "tbclk", "fck"; |
| status = "disabled"; |
| }; |
| }; |
| }; |
| |
| target-module@6000 { /* 0x48306000, ap 96 58.0 */ |
| compatible = "ti,sysc-omap4", "ti,sysc"; |
| reg = <0x6000 0x4>, |
| <0x6004 0x4>; |
| reg-names = "rev", "sysc"; |
| ti,sysc-midle = <SYSC_IDLE_FORCE>, |
| <SYSC_IDLE_NO>, |
| <SYSC_IDLE_SMART>, |
| <SYSC_IDLE_SMART_WKUP>; |
| ti,sysc-sidle = <SYSC_IDLE_FORCE>, |
| <SYSC_IDLE_NO>, |
| <SYSC_IDLE_SMART>, |
| <SYSC_IDLE_SMART_WKUP>; |
| /* Domains (P, C): per_pwrdm, l4ls_clkdm */ |
| clocks = <&l4ls_clkctrl AM4_L4LS_EPWMSS3_CLKCTRL 0>; |
| clock-names = "fck"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0x0 0x6000 0x1000>; |
| |
| epwmss3: epwmss@0 { |
| compatible = "ti,am4372-pwmss","ti,am33xx-pwmss"; |
| reg = <0x0 0x10>; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0 0 0x1000>; |
| status = "disabled"; |
| |
| ehrpwm3: pwm@200 { |
| compatible = "ti,am4372-ehrpwm", |
| "ti,am3352-ehrpwm", |
| "ti,am33xx-ehrpwm"; |
| #pwm-cells = <3>; |
| reg = <0x200 0x80>; |
| clocks = <&ehrpwm3_tbclk>, <&l4ls_gclk>; |
| clock-names = "tbclk", "fck"; |
| status = "disabled"; |
| }; |
| }; |
| }; |
| |
| target-module@8000 { /* 0x48308000, ap 98 54.0 */ |
| compatible = "ti,sysc-omap4", "ti,sysc"; |
| reg = <0x8000 0x4>, |
| <0x8004 0x4>; |
| reg-names = "rev", "sysc"; |
| ti,sysc-midle = <SYSC_IDLE_FORCE>, |
| <SYSC_IDLE_NO>, |
| <SYSC_IDLE_SMART>, |
| <SYSC_IDLE_SMART_WKUP>; |
| ti,sysc-sidle = <SYSC_IDLE_FORCE>, |
| <SYSC_IDLE_NO>, |
| <SYSC_IDLE_SMART>, |
| <SYSC_IDLE_SMART_WKUP>; |
| /* Domains (P, C): per_pwrdm, l4ls_clkdm */ |
| clocks = <&l4ls_clkctrl AM4_L4LS_EPWMSS4_CLKCTRL 0>; |
| clock-names = "fck"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0x0 0x8000 0x1000>; |
| |
| epwmss4: epwmss@0 { |
| compatible = "ti,am4372-pwmss","ti,am33xx-pwmss"; |
| reg = <0x0 0x10>; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0 0 0x1000>; |
| status = "disabled"; |
| |
| ehrpwm4: pwm@48308200 { |
| compatible = "ti,am4372-ehrpwm", |
| "ti,am3352-ehrpwm", |
| "ti,am33xx-ehrpwm"; |
| #pwm-cells = <3>; |
| reg = <0x200 0x80>; |
| clocks = <&ehrpwm4_tbclk>, <&l4ls_gclk>; |
| clock-names = "tbclk", "fck"; |
| status = "disabled"; |
| }; |
| }; |
| }; |
| |
| target-module@a000 { /* 0x4830a000, ap 100 60.0 */ |
| compatible = "ti,sysc-omap4", "ti,sysc"; |
| reg = <0xa000 0x4>, |
| <0xa004 0x4>; |
| reg-names = "rev", "sysc"; |
| ti,sysc-midle = <SYSC_IDLE_FORCE>, |
| <SYSC_IDLE_NO>, |
| <SYSC_IDLE_SMART>, |
| <SYSC_IDLE_SMART_WKUP>; |
| ti,sysc-sidle = <SYSC_IDLE_FORCE>, |
| <SYSC_IDLE_NO>, |
| <SYSC_IDLE_SMART>, |
| <SYSC_IDLE_SMART_WKUP>; |
| /* Domains (P, C): per_pwrdm, l4ls_clkdm */ |
| clocks = <&l4ls_clkctrl AM4_L4LS_EPWMSS5_CLKCTRL 0>; |
| clock-names = "fck"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0x0 0xa000 0x1000>; |
| |
| epwmss5: epwmss@0 { |
| compatible = "ti,am4372-pwmss","ti,am33xx-pwmss"; |
| reg = <0x0 0x10>; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0 0 0x1000>; |
| status = "disabled"; |
| |
| ehrpwm5: pwm@200 { |
| compatible = "ti,am4372-ehrpwm", |
| "ti,am3352-ehrpwm", |
| "ti,am33xx-ehrpwm"; |
| #pwm-cells = <3>; |
| reg = <0x200 0x80>; |
| clocks = <&ehrpwm5_tbclk>, <&l4ls_gclk>; |
| clock-names = "tbclk", "fck"; |
| status = "disabled"; |
| }; |
| }; |
| }; |
| |
| target-module@10000 { /* 0x48310000, ap 64 4e.1 */ |
| compatible = "ti,sysc-omap2", "ti,sysc"; |
| reg = <0x11fe0 0x4>, |
| <0x11fe4 0x4>; |
| reg-names = "rev", "sysc"; |
| ti,sysc-mask = <SYSC_OMAP2_AUTOIDLE>; |
| ti,sysc-sidle = <SYSC_IDLE_FORCE>, |
| <SYSC_IDLE_NO>; |
| /* Domains (P, C): per_pwrdm, l4ls_clkdm */ |
| clocks = <&l4ls_clkctrl AM4_L4LS_RNG_CLKCTRL 0>; |
| clock-names = "fck"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0x0 0x10000 0x2000>; |
| |
| rng: rng@0 { |
| compatible = "ti,omap4-rng"; |
| reg = <0x0 0x2000>; |
| interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; |
| }; |
| }; |
| |
| target-module@13000 { /* 0x48313000, ap 90 50.0 */ |
| compatible = "ti,sysc"; |
| status = "disabled"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0x0 0x13000 0x1000>; |
| }; |
| |
| target-module@18000 { /* 0x48318000, ap 62 4c.0 */ |
| compatible = "ti,sysc"; |
| status = "disabled"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0x0 0x18000 0x4000>; |
| }; |
| |
| target-module@20000 { /* 0x48320000, ap 82 34.0 */ |
| compatible = "ti,sysc-omap2", "ti,sysc"; |
| reg = <0x20000 0x4>, |
| <0x20010 0x4>, |
| <0x20114 0x4>; |
| reg-names = "rev", "sysc", "syss"; |
| ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | |
| SYSC_OMAP2_SOFTRESET | |
| SYSC_OMAP2_AUTOIDLE)>; |
| ti,sysc-sidle = <SYSC_IDLE_FORCE>, |
| <SYSC_IDLE_NO>, |
| <SYSC_IDLE_SMART>, |
| <SYSC_IDLE_SMART_WKUP>; |
| ti,syss-mask = <1>; |
| /* Domains (P, C): per_pwrdm, l4ls_clkdm */ |
| clocks = <&l4ls_clkctrl AM4_L4LS_GPIO5_CLKCTRL 0>, |
| <&l4ls_clkctrl AM4_L4LS_GPIO5_CLKCTRL 8>; |
| clock-names = "fck", "dbclk"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0x0 0x20000 0x1000>; |
| |
| gpio4: gpio@0 { |
| compatible = "ti,am4372-gpio","ti,omap4-gpio"; |
| reg = <0x0 0x1000>; |
| interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| status = "disabled"; |
| }; |
| }; |
| |
| target-module@22000 { /* 0x48322000, ap 116 64.0 */ |
| compatible = "ti,sysc-omap2", "ti,sysc"; |
| reg = <0x22000 0x4>, |
| <0x22010 0x4>, |
| <0x22114 0x4>; |
| reg-names = "rev", "sysc", "syss"; |
| ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | |
| SYSC_OMAP2_SOFTRESET | |
| SYSC_OMAP2_AUTOIDLE)>; |
| ti,sysc-sidle = <SYSC_IDLE_FORCE>, |
| <SYSC_IDLE_NO>, |
| <SYSC_IDLE_SMART>, |
| <SYSC_IDLE_SMART_WKUP>; |
| ti,syss-mask = <1>; |
| /* Domains (P, C): per_pwrdm, l4ls_clkdm */ |
| clocks = <&l4ls_clkctrl AM4_L4LS_GPIO6_CLKCTRL 0>, |
| <&l4ls_clkctrl AM4_L4LS_GPIO6_CLKCTRL 8>; |
| clock-names = "fck", "dbclk"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0x0 0x22000 0x1000>; |
| |
| gpio5: gpio@0 { |
| compatible = "ti,am4372-gpio","ti,omap4-gpio"; |
| reg = <0x0 0x1000>; |
| interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| status = "disabled"; |
| }; |
| }; |
| |
| target-module@26000 { /* 0x48326000, ap 86 66.0 */ |
| compatible = "ti,sysc-omap4", "ti,sysc"; |
| reg = <0x26000 0x4>, |
| <0x26104 0x4>; |
| reg-names = "rev", "sysc"; |
| ti,sysc-midle = <SYSC_IDLE_FORCE>, |
| <SYSC_IDLE_NO>, |
| <SYSC_IDLE_SMART>; |
| ti,sysc-sidle = <SYSC_IDLE_FORCE>, |
| <SYSC_IDLE_NO>, |
| <SYSC_IDLE_SMART>; |
| /* Domains (P, C): per_pwrdm, l3s_clkdm */ |
| clocks = <&l3s_clkctrl AM4_L3S_VPFE0_CLKCTRL 0>; |
| clock-names = "fck"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0x0 0x26000 0x1000>; |
| |
| vpfe0: vpfe@0 { |
| compatible = "ti,am437x-vpfe"; |
| reg = <0x0 0x2000>; |
| interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; |
| status = "disabled"; |
| }; |
| }; |
| |
| target-module@28000 { /* 0x48328000, ap 75 0e.0 */ |
| compatible = "ti,sysc-omap4", "ti,sysc"; |
| reg = <0x28000 0x4>, |
| <0x28104 0x4>; |
| reg-names = "rev", "sysc"; |
| ti,sysc-midle = <SYSC_IDLE_FORCE>, |
| <SYSC_IDLE_NO>, |
| <SYSC_IDLE_SMART>; |
| ti,sysc-sidle = <SYSC_IDLE_FORCE>, |
| <SYSC_IDLE_NO>, |
| <SYSC_IDLE_SMART>; |
| /* Domains (P, C): per_pwrdm, l3s_clkdm */ |
| clocks = <&l3s_clkctrl AM4_L3S_VPFE1_CLKCTRL 0>; |
| clock-names = "fck"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0x0 0x28000 0x1000>; |
| |
| vpfe1: vpfe@0 { |
| compatible = "ti,am437x-vpfe"; |
| reg = <0x0 0x2000>; |
| interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; |
| status = "disabled"; |
| }; |
| }; |
| |
| target-module@2a000 { /* 0x4832a000, ap 88 3c.0 */ |
| compatible = "ti,sysc-omap2", "ti,sysc"; |
| reg = <0x2a000 0x4>, |
| <0x2a010 0x4>, |
| <0x2a014 0x4>; |
| reg-names = "rev", "sysc", "syss"; |
| ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | |
| SYSC_OMAP2_AUTOIDLE)>; |
| ti,syss-mask = <1>; |
| /* Domains (P, C): per_pwrdm, dss_clkdm */ |
| clocks = <&dss_clkctrl AM4_DSS_DSS_CORE_CLKCTRL 0>; |
| clock-names = "fck"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0x00000000 0x0002a000 0x00000400>, |
| <0x00000400 0x0002a400 0x00000400>, |
| <0x00000800 0x0002a800 0x00000400>, |
| <0x00000c00 0x0002ac00 0x00000400>, |
| <0x00001000 0x0002b000 0x00001000>; |
| |
| dss: dss@0 { |
| compatible = "ti,omap3-dss"; |
| reg = <0 0x200>; |
| status = "disabled"; |
| clocks = <&disp_clk>; |
| clock-names = "fck"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0x00000000 0x00000000 0x00000400>, |
| <0x00000400 0x00000400 0x00000400>, |
| <0x00000800 0x00000800 0x00000400>, |
| <0x00000c00 0x00000c00 0x00000400>, |
| <0x00001000 0x00001000 0x00001000>; |
| |
| target-module@400 { |
| compatible = "ti,sysc-omap2", "ti,sysc"; |
| reg = <0x400 0x4>, |
| <0x410 0x4>, |
| <0x414 0x4>; |
| reg-names = "rev", "sysc", "syss"; |
| ti,sysc-sidle = <SYSC_IDLE_FORCE>, |
| <SYSC_IDLE_NO>, |
| <SYSC_IDLE_SMART>; |
| ti,sysc-midle = <SYSC_IDLE_FORCE>, |
| <SYSC_IDLE_NO>, |
| <SYSC_IDLE_SMART>; |
| ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | |
| SYSC_OMAP2_ENAWAKEUP | |
| SYSC_OMAP2_SOFTRESET | |
| SYSC_OMAP2_AUTOIDLE)>; |
| ti,syss-mask = <1>; |
| clocks = <&dss_clkctrl AM4_DSS_DSS_CORE_CLKCTRL 0>; |
| clock-names = "fck"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0 0x400 0x400>; |
| |
| dispc: dispc@0 { |
| compatible = "ti,omap3-dispc"; |
| reg = <0 0x400>; |
| interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&disp_clk>; |
| clock-names = "fck"; |
| |
| max-memory-bandwidth = <230000000>; |
| }; |
| }; |
| |
| target-module@800 { |
| compatible = "ti,sysc-omap2", "ti,sysc"; |
| reg = <0x800 0x4>, |
| <0x810 0x4>, |
| <0x814 0x4>; |
| reg-names = "rev", "sysc", "syss"; |
| ti,sysc-sidle = <SYSC_IDLE_FORCE>, |
| <SYSC_IDLE_NO>, |
| <SYSC_IDLE_SMART>; |
| ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | |
| SYSC_OMAP2_AUTOIDLE)>; |
| ti,syss-mask = <1>; |
| clocks = <&dss_clkctrl AM4_DSS_DSS_CORE_CLKCTRL 0>; |
| clock-names = "fck"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0 0x800 0x400>; |
| |
| rfbi: rfbi@0 { |
| compatible = "ti,omap3-rfbi"; |
| reg = <0 0x100>; |
| clocks = <&dss_clkctrl AM4_DSS_DSS_CORE_CLKCTRL 0>; |
| clock-names = "fck"; |
| status = "disabled"; |
| }; |
| }; |
| }; |
| }; |
| |
| target-module@3d000 { /* 0x4833d000, ap 102 6e.0 */ |
| compatible = "ti,sysc-omap4-timer", "ti,sysc"; |
| reg = <0x3d000 0x4>, |
| <0x3d010 0x4>, |
| <0x3d014 0x4>; |
| reg-names = "rev", "sysc", "syss"; |
| ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; |
| ti,sysc-sidle = <SYSC_IDLE_FORCE>, |
| <SYSC_IDLE_NO>, |
| <SYSC_IDLE_SMART>, |
| <SYSC_IDLE_SMART_WKUP>; |
| /* Domains (P, C): per_pwrdm, l4ls_clkdm */ |
| clocks = <&l4ls_clkctrl AM4_L4LS_TIMER9_CLKCTRL 0>; |
| clock-names = "fck"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0x0 0x3d000 0x1000>; |
| |
| timer9: timer@0 { |
| compatible = "ti,am4372-timer","ti,am335x-timer"; |
| reg = <0x0 0x400>; |
| interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>; |
| status = "disabled"; |
| }; |
| }; |
| |
| target-module@3f000 { /* 0x4833f000, ap 104 5c.0 */ |
| compatible = "ti,sysc-omap4-timer", "ti,sysc"; |
| reg = <0x3f000 0x4>, |
| <0x3f010 0x4>, |
| <0x3f014 0x4>; |
| reg-names = "rev", "sysc", "syss"; |
| ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; |
| ti,sysc-sidle = <SYSC_IDLE_FORCE>, |
| <SYSC_IDLE_NO>, |
| <SYSC_IDLE_SMART>, |
| <SYSC_IDLE_SMART_WKUP>; |
| /* Domains (P, C): per_pwrdm, l4ls_clkdm */ |
| clocks = <&l4ls_clkctrl AM4_L4LS_TIMER10_CLKCTRL 0>; |
| clock-names = "fck"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0x0 0x3f000 0x1000>; |
| |
| timer10: timer@0 { |
| compatible = "ti,am4372-timer","ti,am335x-timer"; |
| reg = <0x0 0x400>; |
| interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; |
| status = "disabled"; |
| }; |
| }; |
| |
| target-module@41000 { /* 0x48341000, ap 106 76.0 */ |
| compatible = "ti,sysc-omap4-timer", "ti,sysc"; |
| reg = <0x41000 0x4>, |
| <0x41010 0x4>, |
| <0x41014 0x4>; |
| reg-names = "rev", "sysc", "syss"; |
| ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; |
| ti,sysc-sidle = <SYSC_IDLE_FORCE>, |
| <SYSC_IDLE_NO>, |
| <SYSC_IDLE_SMART>, |
| <SYSC_IDLE_SMART_WKUP>; |
| /* Domains (P, C): per_pwrdm, l4ls_clkdm */ |
| clocks = <&l4ls_clkctrl AM4_L4LS_TIMER11_CLKCTRL 0>; |
| clock-names = "fck"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0x0 0x41000 0x1000>; |
| |
| timer11: timer@0 { |
| compatible = "ti,am4372-timer","ti,am335x-timer"; |
| reg = <0x0 0x400>; |
| interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; |
| status = "disabled"; |
| }; |
| }; |
| |
| target-module@45000 { /* 0x48345000, ap 108 6a.0 */ |
| compatible = "ti,sysc-omap2", "ti,sysc"; |
| reg = <0x45000 0x4>, |
| <0x45110 0x4>, |
| <0x45114 0x4>; |
| reg-names = "rev", "sysc", "syss"; |
| ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | |
| SYSC_OMAP2_SOFTRESET | |
| SYSC_OMAP2_AUTOIDLE)>; |
| ti,sysc-sidle = <SYSC_IDLE_FORCE>, |
| <SYSC_IDLE_NO>, |
| <SYSC_IDLE_SMART>; |
| ti,syss-mask = <1>; |
| /* Domains (P, C): per_pwrdm, l4ls_clkdm */ |
| clocks = <&l4ls_clkctrl AM4_L4LS_SPI4_CLKCTRL 0>; |
| clock-names = "fck"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0x0 0x45000 0x1000>; |
| |
| spi4: spi@0 { |
| compatible = "ti,am4372-mcspi","ti,omap4-mcspi"; |
| reg = <0x0 0x400>; |
| interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| }; |
| |
| target-module@47000 { /* 0x48347000, ap 110 70.0 */ |
| compatible = "ti,sysc-omap2", "ti,sysc"; |
| reg = <0x47000 0x4>, |
| <0x47014 0x4>, |
| <0x47018 0x4>; |
| reg-names = "rev", "sysc", "syss"; |
| ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | |
| SYSC_OMAP2_AUTOIDLE)>; |
| /* Domains (P, C): per_pwrdm, l4ls_clkdm */ |
| clocks = <&l4ls_clkctrl AM4_L4LS_HDQ1W_CLKCTRL 0>; |
| clock-names = "fck"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0x0 0x47000 0x1000>; |
| |
| hdq: hdq@0 { |
| compatible = "ti,am4372-hdq"; |
| reg = <0x0 0x1000>; |
| interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&func_12m_clk>; |
| clock-names = "fck"; |
| status = "disabled"; |
| }; |
| }; |
| |
| target-module@4c000 { /* 0x4834c000, ap 114 72.0 */ |
| compatible = "ti,sysc"; |
| status = "disabled"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0x0 0x4c000 0x2000>; |
| }; |
| |
| target-module@80000 { /* 0x48380000, ap 123 42.0 */ |
| compatible = "ti,sysc-omap4", "ti,sysc"; |
| ti,hwmods = "usb_otg_ss0"; |
| reg = <0x80000 0x4>, |
| <0x80010 0x4>; |
| reg-names = "rev", "sysc"; |
| ti,sysc-mask = <SYSC_OMAP4_DMADISABLE>; |
| ti,sysc-midle = <SYSC_IDLE_FORCE>, |
| <SYSC_IDLE_NO>, |
| <SYSC_IDLE_SMART>, |
| <SYSC_IDLE_SMART_WKUP>; |
| ti,sysc-sidle = <SYSC_IDLE_FORCE>, |
| <SYSC_IDLE_NO>, |
| <SYSC_IDLE_SMART>, |
| <SYSC_IDLE_SMART_WKUP>; |
| /* Domains (P, C): per_pwrdm, l3s_clkdm */ |
| clocks = <&l3s_clkctrl AM4_L3S_USB_OTG_SS0_CLKCTRL 0>; |
| clock-names = "fck"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0x0 0x80000 0x20000>; |
| |
| dwc3_1: omap_dwc3@0 { |
| compatible = "ti,am437x-dwc3"; |
| reg = <0x0 0x10000>; |
| interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| utmi-mode = <1>; |
| ranges = <0 0 0x20000>; |
| |
| usb1: usb@10000 { |
| compatible = "synopsys,dwc3"; |
| reg = <0x10000 0x10000>; |
| interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "peripheral", |
| "host", |
| "otg"; |
| phys = <&usb2_phy1>; |
| phy-names = "usb2-phy"; |
| maximum-speed = "high-speed"; |
| dr_mode = "otg"; |
| status = "disabled"; |
| snps,dis_u3_susphy_quirk; |
| snps,dis_u2_susphy_quirk; |
| }; |
| }; |
| }; |
| |
| target-module@a8000 { /* 0x483a8000, ap 125 6c.0 */ |
| compatible = "ti,sysc-omap4", "ti,sysc"; |
| reg = <0xa8000 0x4>; |
| reg-names = "rev"; |
| /* Domains (P, C): per_pwrdm, l4ls_clkdm */ |
| clocks = <&l4ls_clkctrl AM4_L4LS_OCP2SCP0_CLKCTRL 0>; |
| clock-names = "fck"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0x0 0xa8000 0x8000>; |
| |
| ocp2scp0: ocp2scp@0 { |
| compatible = "ti,am437x-ocp2scp", "ti,omap-ocp2scp"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0 0 0x8000>; |
| |
| usb2_phy1: phy@8000 { |
| compatible = "ti,am437x-usb2"; |
| reg = <0x0 0x8000>; |
| syscon-phy-power = <&scm_conf 0x620>; |
| clocks = <&usb_phy0_always_on_clk32k>, |
| <&l3s_clkctrl AM4_L3S_USB_OTG_SS0_CLKCTRL 8>; |
| clock-names = "wkupclk", "refclk"; |
| #phy-cells = <0>; |
| status = "disabled"; |
| }; |
| }; |
| }; |
| |
| target-module@c0000 { /* 0x483c0000, ap 127 7a.0 */ |
| compatible = "ti,sysc-omap4", "ti,sysc"; |
| ti,hwmods = "usb_otg_ss1"; |
| reg = <0xc0000 0x4>, |
| <0xc0010 0x4>; |
| reg-names = "rev", "sysc"; |
| ti,sysc-mask = <SYSC_OMAP4_DMADISABLE>; |
| ti,sysc-midle = <SYSC_IDLE_FORCE>, |
| <SYSC_IDLE_NO>, |
| <SYSC_IDLE_SMART>, |
| <SYSC_IDLE_SMART_WKUP>; |
| ti,sysc-sidle = <SYSC_IDLE_FORCE>, |
| <SYSC_IDLE_NO>, |
| <SYSC_IDLE_SMART>, |
| <SYSC_IDLE_SMART_WKUP>; |
| /* Domains (P, C): per_pwrdm, l3s_clkdm */ |
| clocks = <&l3s_clkctrl AM4_L3S_USB_OTG_SS1_CLKCTRL 0>; |
| clock-names = "fck"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0x0 0xc0000 0x20000>; |
| |
| dwc3_2: omap_dwc3@0 { |
| compatible = "ti,am437x-dwc3"; |
| reg = <0x0 0x10000>; |
| interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| utmi-mode = <1>; |
| ranges = <0 0 0x20000>; |
| |
| usb2: usb@10000 { |
| compatible = "synopsys,dwc3"; |
| reg = <0x10000 0x10000>; |
| interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "peripheral", |
| "host", |
| "otg"; |
| phys = <&usb2_phy2>; |
| phy-names = "usb2-phy"; |
| maximum-speed = "high-speed"; |
| dr_mode = "otg"; |
| status = "disabled"; |
| snps,dis_u3_susphy_quirk; |
| snps,dis_u2_susphy_quirk; |
| }; |
| }; |
| }; |
| |
| target-module@e8000 { /* 0x483e8000, ap 129 78.0 */ |
| compatible = "ti,sysc-omap4", "ti,sysc"; |
| reg = <0xe8000 0x4>; |
| reg-names = "rev"; |
| /* Domains (P, C): per_pwrdm, l4ls_clkdm */ |
| clocks = <&l4ls_clkctrl AM4_L4LS_OCP2SCP1_CLKCTRL 0>; |
| clock-names = "fck"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0x0 0xe8000 0x8000>; |
| |
| ocp2scp1: ocp2scp@0 { |
| compatible = "ti,am437x-ocp2scp", "ti,omap-ocp2scp"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0 0 0x8000>; |
| |
| usb2_phy2: phy@8000 { |
| compatible = "ti,am437x-usb2"; |
| reg = <0x0 0x8000>; |
| syscon-phy-power = <&scm_conf 0x628>; |
| clocks = <&usb_phy1_always_on_clk32k>, |
| <&l3s_clkctrl AM4_L3S_USB_OTG_SS1_CLKCTRL 8>; |
| clock-names = "wkupclk", "refclk"; |
| #phy-cells = <0>; |
| status = "disabled"; |
| }; |
| }; |
| }; |
| |
| target-module@f2000 { /* 0x483f2000, ap 112 5a.0 */ |
| compatible = "ti,sysc"; |
| status = "disabled"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0x0 0xf2000 0x2000>; |
| }; |
| }; |
| }; |
| |
