Merge tag 'pinctrl-v5.12-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl
Pull pin control updates from Linus Walleij:
"This is the bulk of pin control changes for the v5.12 kernel.
This time a calm set with no core changes.
New drivers/subdrivers:
- Renesas R8A7790A0 pin controller.
- Allwinner H616 and H616-R pin controllers.
- Qualcomm SM8350 and SC8180x pin controllers.
Improvements:
- Redo the DT bindings for Ralink RT2880.
- A common Qualcomm TLMM DT binding in YAML.
- Delete the unused drivers for U300, COH901, Sirf Atlas, and ZTE ZX"
* tag 'pinctrl-v5.12-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (71 commits)
pinctrl: mediatek: Fix trigger type setting follow for unexpected interrupt
dt-bindings: pinctrl: Group tuples in pin control properties
pinctrl: nuvoton: npcm7xx: Fix alignment of table header comment
pinctrl: at91-pio4: fix "Prefer 'unsigned int' to bare use of 'unsigned'"
pinctrl: at91-pio4: add support for slew-rate
dt-bindings: pinctrl: at91-pio4: add slew-rate
pinctrl: actions: Add depends on || COMPILE_TEST
pinctrl: single: set function name when adding function
pinctrl: qcom: Add sc8180x TLMM driver
dt-bindings: pinctrl: qcom: Add sc8180x binding
dt-bindings: pinctrl: qcom: Define common TLMM binding
pinctrl: qcom: Add SM8350 pinctrl driver
dt-bindings: pinctrl: qcom: Add SM8350 pinctrl bindings
pinctrl: samsung: use raw_spinlock for s3c64xx
dt-bindings: mediatek: mt8192: Fix dt_binding_check warning
pinctrl: qcom: spmi-mpp: Add PM8019 compatible
pinctrl: pinmux: add function selector to pinmux-functions
pinctrl: samsung: use raw_spinlock for locking
pinctrl: clarify #pinctrl-cells for pinctrl-single,pins
pinctrl: actions: Add the platform dependency to drivers
...
diff --git a/Documentation/devicetree/bindings/gpio/gpio-atlas7.txt b/Documentation/devicetree/bindings/gpio/gpio-atlas7.txt
deleted file mode 100644
index d7e123f..0000000
--- a/Documentation/devicetree/bindings/gpio/gpio-atlas7.txt
+++ /dev/null
@@ -1,50 +0,0 @@
-CSR SiRFatlas7 GPIO controller bindings
-
-Required properties:
-- compatible : "sirf,atlas7-gpio"
-- reg : Address range of the pinctrl registers
-- interrupts : Interrupts used by every GPIO group
-- gpio-banks : How many gpio banks on this controller
-- gpio-controller : Indicates this device is a GPIO controller
-- interrupt-controller : Marks the device node as an interrupt controller
-
-The GPIO controller also acts as an interrupt controller. It uses the default
-two cells specifier as described in Documentation/devicetree/bindings/
-interrupt-controller/interrupts.txt.
-
-Example:
-
- gpio_0: gpio_mediam@17040000 {
- compatible = "sirf,atlas7-gpio";
- reg = <0x17040000 0x1000>;
- interrupts = <0 13 0>, <0 14 0>;
-
- #gpio-cells = <2>;
- #interrupt-cells = <2>;
-
- gpio-controller;
- interrupt-controller;
-
- gpio-banks = <2>;
- gpio-ranges = <&pinctrl 0 0 0>,
- <&pinctrl 32 0 0>;
- gpio-ranges-group-names = "lvds_gpio_grp",
- "uart_nand_gpio_grp";
- };
-
- leds {
- compatible = "gpio-leds";
-
- led1 {
- gpios = <&gpio_1 15 0>;
- ...
- };
-
- led2 {
- gpios = <&gpio_2 34 0>;
- ...
- };
- };
-
-Please refer to gpio.txt in this directory for details of the common
-gpio properties used by devices.
diff --git a/Documentation/devicetree/bindings/gpio/gpio-stericsson-coh901.txt b/Documentation/devicetree/bindings/gpio/gpio-stericsson-coh901.txt
deleted file mode 100644
index fd665b4..0000000
--- a/Documentation/devicetree/bindings/gpio/gpio-stericsson-coh901.txt
+++ /dev/null
@@ -1,7 +0,0 @@
-ST-Ericsson COH 901 571/3 GPIO controller
-
-Required properties:
-- compatible: Compatible property value should be "stericsson,gpio-coh901"
-- reg: Physical base address of the controller and length of memory mapped
- region.
-- interrupts: the 0...n interrupts assigned to the different GPIO ports/banks.
diff --git a/Documentation/devicetree/bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml
index 5240487d..cce63c3 100644
--- a/Documentation/devicetree/bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml
@@ -53,6 +53,8 @@
- allwinner,sun50i-h5-pinctrl
- allwinner,sun50i-h6-pinctrl
- allwinner,sun50i-h6-r-pinctrl
+ - allwinner,sun50i-h616-pinctrl
+ - allwinner,sun50i-h616-r-pinctrl
- allwinner,suniv-f1c100s-pinctrl
- nextthing,gr8-pinctrl
@@ -61,7 +63,7 @@
interrupts:
minItems: 1
- maxItems: 7
+ maxItems: 8
description:
One interrupt per external interrupt bank supported on the
controller, sorted by bank number ascending order.
@@ -91,7 +93,7 @@
bank found in the controller
$ref: /schemas/types.yaml#/definitions/uint32-array
minItems: 1
- maxItems: 5
+ maxItems: 8
patternProperties:
# It's pretty scary, but the basic idea is that:
@@ -149,6 +151,17 @@
properties:
compatible:
enum:
+ - allwinner,sun50i-h616-pinctrl
+
+ then:
+ properties:
+ interrupts:
+ minItems: 8
+
+ - if:
+ properties:
+ compatible:
+ enum:
- allwinner,sun50i-a100-pinctrl
then:
diff --git a/Documentation/devicetree/bindings/pinctrl/atmel,at91-pio4-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/atmel,at91-pio4-pinctrl.txt
index 265015b..e2b861c 100644
--- a/Documentation/devicetree/bindings/pinctrl/atmel,at91-pio4-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/atmel,at91-pio4-pinctrl.txt
@@ -35,9 +35,11 @@
right representation of the pin.
Optional properties:
-- GENERIC_PINCONFIG: generic pinconfig options to use, bias-disable,
-bias-pull-down, bias-pull-up, drive-open-drain, input-schmitt-enable,
-input-debounce, output-low, output-high.
+- GENERIC_PINCONFIG: generic pinconfig options to use:
+ - bias-disable, bias-pull-down, bias-pull-up, drive-open-drain,
+ input-schmitt-enable, input-debounce, output-low, output-high.
+ - for microchip,sama7g5-pinctrl only:
+ - slew-rate: 0 - disabled, 1 - enabled (default)
- atmel,drive-strength: 0 or 1 for low drive, 2 for medium drive and 3 for
high drive. The default value is low drive.
diff --git a/Documentation/devicetree/bindings/pinctrl/brcm,ns2-pinmux.txt b/Documentation/devicetree/bindings/pinctrl/brcm,ns2-pinmux.txt
index e295dda..40e0a9a 100644
--- a/Documentation/devicetree/bindings/pinctrl/brcm,ns2-pinmux.txt
+++ b/Documentation/devicetree/bindings/pinctrl/brcm,ns2-pinmux.txt
@@ -39,7 +39,7 @@
<0x660009b0 0x40>;
pinctrl-names = "default";
- pinctrl-0 = <&nand_sel &uart3_rx &sdio0_d4>;
+ pinctrl-0 = <&nand_sel>, <&uart3_rx>, <&sdio0_d4>;
/* Select nand function */
nand_sel: nand_sel {
diff --git a/Documentation/devicetree/bindings/pinctrl/brcm,nsp-pinmux.txt b/Documentation/devicetree/bindings/pinctrl/brcm,nsp-pinmux.txt
index 603564e..dede11e 100644
--- a/Documentation/devicetree/bindings/pinctrl/brcm,nsp-pinmux.txt
+++ b/Documentation/devicetree/bindings/pinctrl/brcm,nsp-pinmux.txt
@@ -30,7 +30,7 @@
<0x1803f408 0x04>;
pinctrl-names = "default";
- pinctrl-0 = <&pwm &gpio_b &nand_sel>;
+ pinctrl-0 = <&pwm>, <&gpio_b>, <&nand_sel>;
pwm: pwm {
function = "pwm";
diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx7d-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/fsl,imx7d-pinctrl.txt
index 8ac1d08..bfab5ca 100644
--- a/Documentation/devicetree/bindings/pinctrl/fsl,imx7d-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/fsl,imx7d-pinctrl.txt
@@ -60,7 +60,7 @@
i2c1: i2c@30a20000 {
pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c1_1 &pinctrl_i2c1_2>;
+ pinctrl-0 = <&pinctrl_i2c1_1>, <&pinctrl_i2c1_2>;
};
iomuxc-lpsr@302c0000 {
diff --git a/Documentation/devicetree/bindings/pinctrl/microchip,sparx5-sgpio.yaml b/Documentation/devicetree/bindings/pinctrl/microchip,sparx5-sgpio.yaml
index df0c83c..4fe35e6 100644
--- a/Documentation/devicetree/bindings/pinctrl/microchip,sparx5-sgpio.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/microchip,sparx5-sgpio.yaml
@@ -99,8 +99,8 @@
'#interrupt-cells':
description:
- Specifies the pin (port and bit) and flags, as defined in
- defined in include/dt-bindings/interrupt-controller/irq.h
+ Specifies the pin (port and bit) and flags, as defined in
+ defined in include/dt-bindings/interrupt-controller/irq.h
const: 3
ngpios:
diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-atlas7.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-atlas7.txt
deleted file mode 100644
index fbdd1a7..0000000
--- a/Documentation/devicetree/bindings/pinctrl/pinctrl-atlas7.txt
+++ /dev/null
@@ -1,109 +0,0 @@
-CSR SiRFatlas7 pinmux controller
-
-Required properties:
-- compatible : "sirf,atlas7-ioc"
-- reg : Address range of the pinctrl registers
-
-For example, pinctrl might have properties like the following:
- pinctrl: ioc@18880000 {
- compatible = "sirf,atlas7-ioc";
- reg = <0x18880000 0x1000>;
-
- a_ac97_pmx: ac97@0 {
- ac97 {
- groups = "audio_ac97_grp";
- function = "audio_ac97";
- };
- };
-
- ...
-
- sd2_pmx: sd2@0 {
- sd2 {
- groups = "sd2_grp0";
- function = "sd2";
- };
- };
-
- ...
-
-
- sample0_cfg: sample0@0 {
- sample0 {
- pins = "ldd_0", "ldd_1";
- bias-pull-up;
- };
- };
-
- sample1_cfg: sample1@0 {
- sample1 {
- pins = "ldd_2", "ldd_3";
- input-schmitt-enable;
- };
- };
-
- sample2_cfg: sample2@0 {
- sample2 {
- groups = "uart4_nopause_grp";
- bias-pull-down;
- };
- };
-
- sample3_cfg: sample3@0 {
- sample3 {
- pins = "ldd_4", "ldd_5";
- drive-strength = <2>;
- };
- };
- };
-
-Please refer to pinctrl-bindings.txt in this directory for details of the common
-pinctrl bindings used by client devices.
-
-SiRFatlas7's pinmux nodes act as a container for an arbitrary number of subnodes.
-Each of these subnodes represents some desired configuration for a group of pins.
-
-Required subnode-properties:
-- groups : An array of strings. Each string contains the name of a group.
-- function: A string containing the name of the function to mux to the
- group.
-
- Valid values for group and function names can be found from looking at the
- group and function arrays in driver files:
- drivers/pinctrl/pinctrl-sirf.c
-
-For example, pinctrl might have subnodes like the following:
- sd0_pmx: sd0@0 {
- sd0 {
- groups = "sd0_grp";
- function = "sd0";
- };
- };
-
- sd1_pmx0: sd1@0 {
- sd1 {
- groups = "sd1_grp0";
- function = "sd1_m0";
- };
- };
-
- sd1_pmx1: sd1@1 {
- sd1 {
- groups = "sd1_grp1";
- function = "sd1_m1";
- };
- };
-
-For a specific board, if it wants to use sd1,
-it can add the following to its board-specific .dts file.
-sd1: sd@12340000 {
- pinctrl-names = "default";
- pinctrl-0 = <&sd1_pmx0>;
-}
-
-or
-
-sd1: sd@12340000 {
- pinctrl-names = "default";
- pinctrl-0 = <&sd1_pmx1>;
-}
diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
index 4613bb1..9dae60a 100644
--- a/Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
+++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
@@ -77,13 +77,13 @@
device {
pinctrl-names = "active", "idle";
pinctrl-0 = <&state_0_node_a>;
- pinctrl-1 = <&state_1_node_a &state_1_node_b>;
+ pinctrl-1 = <&state_1_node_a>, <&state_1_node_b>;
};
/* For the same device if using state IDs */
device {
pinctrl-0 = <&state_0_node_a>;
- pinctrl-1 = <&state_1_node_a &state_1_node_b>;
+ pinctrl-1 = <&state_1_node_a>, <&state_1_node_b>;
};
/*
diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-mcp23s08.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-mcp23s08.txt
index 8b94aa8..6ec3c8d 100644
--- a/Documentation/devicetree/bindings/pinctrl/pinctrl-mcp23s08.txt
+++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-mcp23s08.txt
@@ -134,7 +134,7 @@
#interrupt-cells = <0x2>;
microchip,irq-mirror;
pinctrl-names = "default";
- pinctrl-0 = <&i2cgpio0irq &gpio21pullups>;
+ pinctrl-0 = <&i2cgpio0irq>, <&gpio21pullups>;
gpio21pullups: pinmux {
pins = "gpio0", "gpio1", "gpio2", "gpio3",
diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-mt65xx.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-mt65xx.txt
index 931a18c..360e59c 100644
--- a/Documentation/devicetree/bindings/pinctrl/pinctrl-mt65xx.txt
+++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-mt65xx.txt
@@ -91,7 +91,7 @@
pinctrl@1c20800 {
compatible = "mediatek,mt8135-pinctrl";
reg = <0 0x1000B000 0 0x1000>;
- mediatek,pctl-regmap = <&syscfg_pctl_a &syscfg_pctl_b>;
+ mediatek,pctl-regmap = <&syscfg_pctl_a>, <&syscfg_pctl_b>;
pins-are-numbered;
gpio-controller;
#gpio-cells = <2>;
diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt
index f903eb4..bfd222b 100644
--- a/Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt
+++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt
@@ -8,7 +8,7 @@
- reg : offset and length of the register set for the mux registers
- #pinctrl-cells : number of cells in addition to the index, set to 1
- for pinctrl-single,pins and 2 for pinctrl-single,bits
+ or 2 for pinctrl-single,pins and set to 2 for pinctrl-single,bits
- pinctrl-single,register-width : pinmux register access width in bits
@@ -80,7 +80,7 @@
property.
/* pin base, nr pins & gpio function */
- pinctrl-single,gpio-range = <&range 0 3 0 &range 3 9 1>;
+ pinctrl-single,gpio-range = <&range 0 3 0>, <&range 3 9 1>;
- interrupt-controller : standard interrupt controller binding if using
interrupts for wake-up events for example. In this case pinctrl-single
@@ -185,10 +185,10 @@
pinctrl-single,function-mask = <7>;
/* sparse GPIO range could be supported */
- pinctrl-single,gpio-range = <&range 0 3 0 &range 3 9 1
- &range 12 1 0 &range 13 29 1
- &range 43 1 0 &range 44 49 1
- &range 94 1 1 &range 96 2 1>;
+ pinctrl-single,gpio-range = <&range 0 3 0>, <&range 3 9 1>,
+ <&range 12 1 0>, <&range 13 29 1>,
+ <&range 43 1 0>, <&range 44 49 1>,
+ <&range 94 1 1>, <&range 96 2 1>;
range: gpio-range {
#pinctrl-single,gpio-range-cells = <3>;
diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-zx.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-zx.txt
deleted file mode 100644
index 39170f3..0000000
--- a/Documentation/devicetree/bindings/pinctrl/pinctrl-zx.txt
+++ /dev/null
@@ -1,84 +0,0 @@
-* ZTE ZX Pin Controller
-
-The pin controller on ZTE ZX platforms is kinda of hybrid. It consists of
-a main controller and an auxiliary one. For example, on ZX296718 SoC, the
-main controller is TOP_PMM and the auxiliary one is AON_IOCFG. Both
-controllers work together to control pin multiplexing and configuration in
-the way illustrated as below.
-
-
- GMII_RXD3 ---+
- |
- DVI1_HS ---+----------------------------- GMII_RXD3 (TOP pin)
- |
- BGPIO16 ---+ ^
- | pinconf
- ^ |
- | pinmux |
- | |
-
- TOP_PMM (main) AON_IOCFG (aux)
-
- | | |
- | pinmux | |
- | pinmux v |
- v | pinconf
- KEY_ROW2 ---+ v
- PORT1_LCD_TE ---+ |
- | AGPIO10 ---+------ KEY_ROW2 (AON pin)
- I2S0_DOUT3 ---+ |
- |-----------------------+
- PWM_OUT3 ---+
- |
- VGA_VS1 ---+
-
-
-For most of pins like GMII_RXD3 in the figure, the pinmux function is
-controlled by TOP_PMM block only, and this type of pins are meant by term
-'TOP pins'. For pins like KEY_ROW2, the pinmux is controlled by both
-TOP_PMM and AON_IOCFG blocks, as the available multiplexing functions for
-the pin spread in both controllers. This type of pins are called 'AON pins'.
-Though pinmux implementation is quite different, pinconf is same for both
-types of pins. Both are controlled by auxiliary controller, i.e. AON_IOCFG
-on ZX296718.
-
-Required properties:
-- compatible: should be "zte,zx296718-pmm".
-- reg: the register physical address and length.
-- zte,auxiliary-controller: phandle to the auxiliary pin controller which
- implements pinmux for AON pins and pinconf for all pins.
-
-The following pin configuration are supported. Please refer to
-pinctrl-bindings.txt in this directory for more details of the common
-pinctrl bindings used by client devices.
-
-- bias-pull-up
-- bias-pull-down
-- drive-strength
-- input-enable
-- slew-rate
-
-Examples:
-
-iocfg: pin-controller@119000 {
- compatible = "zte,zx296718-iocfg";
- reg = <0x119000 0x1000>;
-};
-
-pmm: pin-controller@1462000 {
- compatible = "zte,zx296718-pmm";
- reg = <0x1462000 0x1000>;
- zte,auxiliary-controller = <&iocfg>;
-};
-
-&pmm {
- vga_pins: vga {
- pins = "KEY_COL1", "KEY_COL2", "KEY_ROW1", "KEY_ROW2";
- function = "VGA";
- };
-};
-
-&vga {
- pinctrl-names = "default";
- pinctrl-0 = <&vga_pins>;
-};
diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,pmic-mpp.txt b/Documentation/devicetree/bindings/pinctrl/qcom,pmic-mpp.txt
index 448d36a..0ba07bc 100644
--- a/Documentation/devicetree/bindings/pinctrl/qcom,pmic-mpp.txt
+++ b/Documentation/devicetree/bindings/pinctrl/qcom,pmic-mpp.txt
@@ -8,6 +8,7 @@
Value type: <string>
Definition: Should contain one of:
"qcom,pm8018-mpp",
+ "qcom,pm8019-mpp",
"qcom,pm8038-mpp",
"qcom,pm8058-mpp",
"qcom,pm8821-mpp",
diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sc8180x-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sc8180x-pinctrl.yaml
new file mode 100644
index 0000000..a82dab8
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/qcom,sc8180x-pinctrl.yaml
@@ -0,0 +1,152 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pinctrl/qcom,sc8180x-pinctrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Technologies, Inc. SC8180X TLMM block
+
+maintainers:
+ - Bjorn Andersson <bjorn.andersson@linaro.org>
+
+description: |
+ This binding describes the Top Level Mode Multiplexer block found in the
+ SC8180X platform.
+
+allOf:
+ - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
+
+properties:
+ compatible:
+ const: qcom,sc8180x-tlmm
+
+ reg:
+ maxItems: 3
+
+ reg-names:
+ items:
+ - const: "west"
+ - const: "east"
+ - const: "south"
+
+ interrupts: true
+ interrupt-controller: true
+ '#interrupt-cells': true
+ gpio-controller: true
+ gpio-reserved-ranges: true
+ '#gpio-cells': true
+ gpio-ranges: true
+ wakeup-parent: true
+
+required:
+ - compatible
+ - reg
+ - reg-names
+
+additionalProperties: false
+
+patternProperties:
+ '-state$':
+ oneOf:
+ - $ref: "#/$defs/qcom-sc8180x-tlmm-state"
+ - patternProperties:
+ ".*":
+ $ref: "#/$defs/qcom-sc8180x-tlmm-state"
+
+'$defs':
+ qcom-sc8180x-tlmm-state:
+ type: object
+ description:
+ Pinctrl node's client devices use subnodes for desired pin configuration.
+ Client device subnodes use below standard properties.
+ $ref: "qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state"
+
+ properties:
+ pins:
+ description:
+ List of gpio pins affected by the properties specified in this
+ subnode.
+ items:
+ oneOf:
+ - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-8][0-9])$"
+ - enum: [ sdc2_clk, sdc2_cmd, sdc2_data, ufs_reset ]
+ minItems: 1
+ maxItems: 16
+
+ function:
+ description:
+ Specify the alternative function to be configured for the specified
+ pins.
+
+ enum: [ adsp_ext, agera_pll, aoss_cti, atest_char, atest_tsens,
+ atest_tsens2, atest_usb0, atest_usb1, atest_usb2, atest_usb3,
+ atest_usb4, audio_ref, btfm_slimbus, cam_mclk, cci_async,
+ cci_i2c, cci_timer0, cci_timer1, cci_timer2, cci_timer3,
+ cci_timer4, cci_timer5, cci_timer6, cci_timer7, cci_timer8,
+ cci_timer9, cri_trng, dbg_out, ddr_bist, ddr_pxi, debug_hot,
+ dp_hot, edp_hot, edp_lcd, emac_phy, emac_pps, gcc_gp1, gcc_gp2,
+ gcc_gp3, gcc_gp4, gcc_gp5, gpio, gps, grfc, hs1_mi2s, hs2_mi2s,
+ hs3_mi2s, jitter_bist, lpass_slimbus, m_voc, mdp_vsync,
+ mdp_vsync0, mdp_vsync1, mdp_vsync2, mdp_vsync3, mdp_vsync4,
+ mdp_vsync5, mss_lte, nav_pps, pa_indicator, pci_e0, pci_e1,
+ pci_e2, pci_e3, phase_flag, pll_bist, pll_bypassnl, pll_reset,
+ pri_mi2s, pri_mi2s_ws, prng_rosc, qdss_cti, qdss_gpio, qlink,
+ qspi0, qspi0_clk, qspi0_cs, qspi1, qspi1_clk, qspi1_cs,
+ qua_mi2s, qup0, qup1, qup2, qup3, qup4, qup5, qup6, qup7, qup8,
+ qup9, qup10, qup11, qup12, qup13, qup14, qup15, qup16, qup17,
+ qup18, qup19, qup_l4, qup_l5, qup_l6, rgmii, sd_write, sdc4,
+ sdc4_clk, sdc4_cmd, sec_mi2s, sp_cmu, spkr_i2s, ter_mi2s, tgu,
+ tsense_pwm1, tsense_pwm2, tsif1, tsif2, uim1, uim2, uim_batt,
+ usb0_phy, usb1_phy, usb2phy_ac, vfr_1, vsense_trigger,
+ wlan1_adc, wlan2_adc, wmss_reset ]
+
+ bias-disable: true
+ bias-pull-down: true
+ bias-pull-up: true
+ drive-strength: true
+ input-enable: true
+ output-high: true
+ output-low: true
+
+ required:
+ - pins
+ - function
+
+ additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ pinctrl@3100000 {
+ compatible = "qcom,sc8180x-tlmm";
+ reg = <0x03100000 0x300000>,
+ <0x03500000 0x700000>,
+ <0x03d00000 0x300000>;
+ reg-names = "west", "east", "south";
+ interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ gpio-ranges = <&tlmm 0 0 190>;
+
+ gpio-wo-subnode-state {
+ pins = "gpio1";
+ function = "gpio";
+ };
+
+ uart-w-subnodes-state {
+ rx {
+ pins = "gpio4";
+ function = "qup6";
+ bias-pull-up;
+ };
+
+ tx {
+ pins = "gpio5";
+ function = "qup6";
+ bias-disable;
+ };
+ };
+ };
+...
diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sm8350-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sm8350-pinctrl.yaml
new file mode 100644
index 0000000..4f2667e
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/qcom,sm8350-pinctrl.yaml
@@ -0,0 +1,145 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pinctrl/qcom,sm8350-pinctrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Technologies, Inc. SM8350 TLMM block
+
+maintainers:
+ - Vinod Koul <vkoul@kernel.org>
+
+description: |
+ This binding describes the Top Level Mode Multiplexer (TLMM) block found
+ in the SM8350 platform.
+
+allOf:
+ - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
+
+properties:
+ compatible:
+ const: qcom,sm8350-tlmm
+
+ reg:
+ maxItems: 1
+
+ interrupts: true
+ interrupt-controller: true
+ '#interrupt-cells': true
+ gpio-controller: true
+ gpio-reserved-ranges: true
+ '#gpio-cells': true
+ gpio-ranges: true
+ wakeup-parent: true
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+patternProperties:
+ '-state$':
+ oneOf:
+ - $ref: "#/$defs/qcom-sm8350-tlmm-state"
+ - patternProperties:
+ ".*":
+ $ref: "#/$defs/qcom-sm8350-tlmm-state"
+
+$defs:
+ qcom-sm8350-tlmm-state:
+ type: object
+ description:
+ Pinctrl node's client devices use subnodes for desired pin configuration.
+ Client device subnodes use below standard properties.
+ $ref: "qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state"
+
+ properties:
+ pins:
+ description:
+ List of gpio pins affected by the properties specified in this
+ subnode.
+ items:
+ oneOf:
+ - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-9][0-9]|20[0-3])$"
+ - enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk, sdc2_cmd, sdc2_data ]
+ minItems: 1
+ maxItems: 36
+
+ function:
+ description:
+ Specify the alternative function to be configured for the specified
+ pins.
+
+ enum: [ atest_char, atest_usb, audio_ref, cam_mclk, cci_async,
+ cci_i2c, cci_timer, cmu_rng, coex_uart1, coex_uart2, cri_trng,
+ cri_trng0, cri_trng1, dbg_out, ddr_bist, ddr_pxi0, ddr_pxi1,
+ ddr_pxi2, ddr_pxi3, dp_hot, dp_lcd, gcc_gp1, gcc_gp2, gcc_gp3,
+ gpio, ibi_i3c, jitter_bist, lpass_slimbus, mdp_vsync, mdp_vsync0,
+ mdp_vsync1, mdp_vsync2, mdp_vsync3, mi2s0_data0, mi2s0_data1,
+ mi2s0_sck, mi2s0_ws, mi2s1_data0, mi2s1_data1, mi2s1_sck,
+ mi2s1_ws, mi2s2_data0, mi2s2_data1, mi2s2_sck, mi2s2_ws,
+ mss_grfc0, mss_grfc1, mss_grfc10, mss_grfc11, mss_grfc12,
+ mss_grfc2, mss_grfc3, mss_grfc4, mss_grfc5, mss_grfc6,
+ mss_grfc7, mss_grfc8, mss_grfc9, nav_gpio, pa_indicator,
+ pcie0_clkreqn, pcie1_clkreqn, phase_flag, pll_bist, pll_clk,
+ pri_mi2s, prng_rosc, qdss_cti, qdss_gpio, qlink0_enable,
+ qlink0_request, qlink0_wmss, qlink1_enable, qlink1_request,
+ qlink1_wmss, qlink2_enable, qlink2_request, qlink2_wmss, qspi0,
+ qspi1, qspi2, qspi3, qspi_clk, qspi_cs, qup0, qup1, qup10,
+ qup11, qup12, qup13, qup14, qup15, qup16, qup17, qup18, qup19,
+ qup2, qup3, qup4, qup5, qup6, qup7, qup8, qup9, qup_l4, qup_l5,
+ qup_l6, sd_write, sdc40, sdc41, sdc42, sdc43, sdc4_clk,
+ sdc4_cmd, sec_mi2s, tb_trig, tgu_ch0, tgu_ch1, tgu_ch2,
+ tgu_ch3, tsense_pwm1, tsense_pwm2, uim0_clk, uim0_data,
+ uim0_present, uim0_reset, uim1_clk, uim1_data, uim1_present,
+ uim1_reset, usb2phy_ac, usb_phy, vfr_0, vfr_1, vsense_trigger ]
+
+
+ bias-disable: true
+ bias-pull-down: true
+ bias-pull-up: true
+ drive-strength: true
+ input-enable: true
+ output-high: true
+ output-low: true
+
+ required:
+ - pins
+ - function
+
+ additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ pinctrl@f100000 {
+ compatible = "qcom,sm8350-tlmm";
+ reg = <0x0f100000 0x300000>;
+ interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ gpio-ranges = <&tlmm 0 0 203>;
+
+ gpio-wo-subnode-state {
+ pins = "gpio1";
+ function = "gpio";
+ };
+
+ uart-w-subnodes-state {
+ rx {
+ pins = "gpio18";
+ function = "qup3";
+ bias-pull-up;
+ };
+
+ tx {
+ pins = "gpio19";
+ function = "qup3";
+ bias-disable;
+ };
+ };
+ };
+...
diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,tlmm-common.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,tlmm-common.yaml
new file mode 100644
index 0000000..3b37cf1
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/qcom,tlmm-common.yaml
@@ -0,0 +1,85 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pinctrl/qcom,tlmm-common.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Technologies, Inc. Top Level Mode Multiplexer (TLMM) definitions
+
+maintainers:
+ - Bjorn Andersson <bjorn.andersson@linaro.org>
+
+description:
+ This defines the common properties used to describe all Qualcomm Top Level
+ Mode Multiplexer bindings and pinconf/pinmux states for these.
+
+properties:
+ interrupts:
+ description:
+ Specifies the TLMM summary IRQ
+ maxItems: 1
+
+ interrupt-controller: true
+
+ '#interrupt-cells':
+ description:
+ Specifies the PIN numbers and Flags, as defined in defined in
+ include/dt-bindings/interrupt-controller/irq.h
+ const: 2
+
+ gpio-controller: true
+
+ '#gpio-cells':
+ description:
+ Specifying the pin number and flags, as defined in
+ include/dt-bindings/gpio/gpio.h
+ const: 2
+
+ gpio-ranges:
+ maxItems: 1
+
+ wakeup-parent:
+ description:
+ Specifying the interrupt-controller used to wake up the system when the
+ TLMM block has been powered down.
+ maxItems: 1
+
+ gpio-reserved-ranges:
+ description:
+ Pins can be reserved for trusted applications and thereby unaccessible
+ from the OS. This property can be used to mark the pins which resources
+ should not be accessed by the OS. Please see the ../gpio/gpio.txt for more
+ information.
+
+required:
+ - interrupts
+ - interrupt-controller
+ - '#interrupt-cells'
+ - gpio-controller
+ - '#gpio-cells'
+ - gpio-ranges
+
+additionalProperties: true
+
+$defs:
+ qcom-tlmm-state:
+ allOf:
+ - $ref: pincfg-node.yaml#
+ - $ref: pinmux-node.yaml#
+
+ properties:
+ drive-strength:
+ enum: [2, 4, 6, 8, 10, 12, 14, 16]
+ default: 2
+ description:
+ Selects the drive strength for the specified pins, in mA.
+
+ bias-pull-down: true
+ bias-pull-up: true
+ bias-disable: true
+ input-enable: true
+ output-high: true
+ output-low: true
+
+ additionalProperties: true
+...
diff --git a/Documentation/devicetree/bindings/pinctrl/ralink,rt2880-pinmux.yaml b/Documentation/devicetree/bindings/pinctrl/ralink,rt2880-pinmux.yaml
index 7dea3e2..b32f267 100644
--- a/Documentation/devicetree/bindings/pinctrl/ralink,rt2880-pinmux.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/ralink,rt2880-pinmux.yaml
@@ -15,39 +15,38 @@
properties:
compatible:
- enum:
- - ralink,rt2880-pinmux
+ const: ralink,rt2880-pinmux
- pinctrl-0:
- description:
- A phandle to the node containing the subnodes containing default
- configurations. This is for pinctrl hogs.
+patternProperties:
+ '-pins$':
+ type: object
+ patternProperties:
+ '^(.*-)?pinmux$':
+ type: object
+ description: node for pinctrl.
+ $ref: pinmux-node.yaml#
- pinctrl-names:
- description:
- A pinctrl state named "default" can be defined.
- const: default
+ properties:
+ groups:
+ description: Name of the pin group to use for the functions.
+ enum: [i2c, spi, uart1, uart2, uart3, rgmii1, rgmii2, mdio,
+ pcie, sdhci]
+ function:
+ description: The mux function to select
+ enum: [gpio, i2c, spi, uart1, uart2, uart3, rgmii1, rgmii2,
+ mdio, nand1, nand2, sdhci]
+
+ required:
+ - groups
+ - function
+
+ additionalProperties: false
+
+ additionalProperties: false
required:
- compatible
-patternProperties:
- '[a-z0-9_-]+':
- if:
- type: object
- description: node for pinctrl.
- $ref: "pinmux-node.yaml"
- then:
- properties:
- groups:
- description: Name of the pin group to use for the functions.
- enum: [i2c, spi, uart1, uart2, uart3, rgmii1, rgmii2, mdio,
- pcie, sdhci]
- function:
- description: The mux function to select
- enum: [gpio, i2c, spi, uart1, uart2, uart3, rgmii1, rgmii2,
- mdio, nand1, nand2, sdhci]
-
additionalProperties: false
examples:
@@ -55,14 +54,9 @@
- |
pinctrl {
compatible = "ralink,rt2880-pinmux";
- pinctrl-names = "default";
- pinctrl-0 = <&state_default>;
- state_default: pinctrl0 {
- };
-
- i2c_pins: i2c0 {
- i2c0 {
+ i2c_pins: i2c0-pins {
+ pinmux {
groups = "i2c";
function = "i2c";
};
diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,pfc.yaml b/Documentation/devicetree/bindings/pinctrl/renesas,pfc.yaml
index 5d39479..ac4e068 100644
--- a/Documentation/devicetree/bindings/pinctrl/renesas,pfc.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/renesas,pfc.yaml
@@ -43,11 +43,12 @@
- renesas,pfc-r8a77980 # R-Car V3H
- renesas,pfc-r8a77990 # R-Car E3
- renesas,pfc-r8a77995 # R-Car D3
+ - renesas,pfc-r8a779a0 # R-Car V3U
- renesas,pfc-sh73a0 # SH-Mobile AG5
reg:
minItems: 1
- maxItems: 2
+ maxItems: 10
gpio-controller: true
diff --git a/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
index 7734ab6..38a1416 100644
--- a/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
@@ -336,7 +336,7 @@
interrupts = <0 52 0>;
pinctrl-names = "default", "flow-control;
pinctrl-0 = <&uart0_data>;
- pinctrl-1 = <&uart0_data &uart0_fctl>;
+ pinctrl-1 = <&uart0_data>, <&uart0_fctl>;
};
Example 4: Set up the default pin state for uart controller.
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index d4b2f2e..03c62e1 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -226,14 +226,6 @@
help
This selects the device tree based generic pinctrl driver.
-config PINCTRL_SIRF
- bool "CSR SiRFprimaII pin controller driver"
- depends on ARCH_SIRF
- select PINMUX
- select PINCONF
- select GENERIC_PINCONF
- select GPIOLIB_IRQCHIP
-
config PINCTRL_SX150X
bool "Semtech SX150x I2C GPIO expander pinctrl driver"
depends on I2C=y
@@ -279,22 +271,6 @@
and configuring push-pull, open-drain, and can also be used as
interrupt-controller.
-config PINCTRL_U300
- bool "U300 pin controller driver"
- depends on ARCH_U300
- select PINMUX
- select GENERIC_PINCONF
-
-config PINCTRL_COH901
- bool "ST-Ericsson U300 COH 901 335/571 GPIO"
- depends on GPIOLIB && ARCH_U300 && PINCTRL_U300
- select GPIOLIB_IRQCHIP
- help
- Say yes here to support GPIO interface on ST-Ericsson U300.
- The names of the two IP block variants supported are
- COH 901 335 and COH 901 571/3. They contain 3, 5 or 7
- ports of 8 GPIO pins each.
-
config PINCTRL_MAX77620
tristate "MAX77620/MAX20024 Pincontrol support"
depends on MFD_MAX77620 && OF
@@ -417,7 +393,6 @@
source "drivers/pinctrl/uniphier/Kconfig"
source "drivers/pinctrl/vt8500/Kconfig"
source "drivers/pinctrl/mediatek/Kconfig"
-source "drivers/pinctrl/zte/Kconfig"
source "drivers/pinctrl/meson/Kconfig"
source "drivers/pinctrl/cirrus/Kconfig"
source "drivers/pinctrl/visconti/Kconfig"
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index 5bb9bb6..efc96f2 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -31,11 +31,8 @@
obj-$(CONFIG_PINCTRL_PISTACHIO) += pinctrl-pistachio.o
obj-$(CONFIG_PINCTRL_ROCKCHIP) += pinctrl-rockchip.o
obj-$(CONFIG_PINCTRL_SINGLE) += pinctrl-single.o
-obj-$(CONFIG_PINCTRL_SIRF) += sirf/
obj-$(CONFIG_PINCTRL_SX150X) += pinctrl-sx150x.o
obj-$(CONFIG_ARCH_TEGRA) += tegra/
-obj-$(CONFIG_PINCTRL_U300) += pinctrl-u300.o
-obj-$(CONFIG_PINCTRL_COH901) += pinctrl-coh901.o
obj-$(CONFIG_PINCTRL_XWAY) += pinctrl-xway.o
obj-$(CONFIG_PINCTRL_LANTIQ) += pinctrl-lantiq.o
obj-$(CONFIG_PINCTRL_LPC18XX) += pinctrl-lpc18xx.o
@@ -71,6 +68,5 @@
obj-$(CONFIG_PINCTRL_UNIPHIER) += uniphier/
obj-$(CONFIG_ARCH_VT8500) += vt8500/
obj-y += mediatek/
-obj-$(CONFIG_PINCTRL_ZX) += zte/
obj-y += cirrus/
obj-$(CONFIG_PINCTRL_VISCONTI) += visconti/
diff --git a/drivers/pinctrl/actions/Kconfig b/drivers/pinctrl/actions/Kconfig
index a1d16e8..119f0e4 100644
--- a/drivers/pinctrl/actions/Kconfig
+++ b/drivers/pinctrl/actions/Kconfig
@@ -12,18 +12,21 @@
config PINCTRL_S500
bool "Actions Semi S500 pinctrl driver"
+ depends on ARM || COMPILE_TEST
depends on PINCTRL_OWL
help
Say Y here to enable Actions Semi S500 pinctrl driver
config PINCTRL_S700
bool "Actions Semi S700 pinctrl driver"
+ depends on ARM64 || COMPILE_TEST
depends on PINCTRL_OWL
help
Say Y here to enable Actions Semi S700 pinctrl driver
config PINCTRL_S900
bool "Actions Semi S900 pinctrl driver"
+ depends on ARM64 || COMPILE_TEST
depends on PINCTRL_OWL
help
Say Y here to enable Actions Semi S900 pinctrl driver
diff --git a/drivers/pinctrl/actions/pinctrl-owl.c b/drivers/pinctrl/actions/pinctrl-owl.c
index 903a4ba..c8b3e39 100644
--- a/drivers/pinctrl/actions/pinctrl-owl.c
+++ b/drivers/pinctrl/actions/pinctrl-owl.c
@@ -444,7 +444,6 @@
*config = pinconf_to_config_packed(param, arg);
return ret;
-
}
static int owl_group_config_set(struct pinctrl_dev *pctrldev,
diff --git a/drivers/pinctrl/bcm/pinctrl-ns2-mux.c b/drivers/pinctrl/bcm/pinctrl-ns2-mux.c
index 57044ab..0fe4a1f 100644
--- a/drivers/pinctrl/bcm/pinctrl-ns2-mux.c
+++ b/drivers/pinctrl/bcm/pinctrl-ns2-mux.c
@@ -853,7 +853,7 @@
switch (param) {
case PIN_CONFIG_BIAS_DISABLE:
ns2_pin_get_pull(pctldev, pin, &pull_up, &pull_down);
- if ((pull_up == false) && (pull_down == false))
+ if (!pull_up && !pull_down)
return 0;
else
return -EINVAL;
diff --git a/drivers/pinctrl/core.c b/drivers/pinctrl/core.c
index 9fc4433..7d33702 100644
--- a/drivers/pinctrl/core.c
+++ b/drivers/pinctrl/core.c
@@ -2117,7 +2117,6 @@
return ERR_PTR(error);
return pctldev;
-
}
EXPORT_SYMBOL_GPL(pinctrl_register);
diff --git a/drivers/pinctrl/freescale/pinctrl-imx1-core.c b/drivers/pinctrl/freescale/pinctrl-imx1-core.c
index 08d1100..7018644 100644
--- a/drivers/pinctrl/freescale/pinctrl-imx1-core.c
+++ b/drivers/pinctrl/freescale/pinctrl-imx1-core.c
@@ -290,7 +290,6 @@
.pin_dbg_show = imx1_pin_dbg_show,
.dt_node_to_map = imx1_dt_node_to_map,
.dt_free_map = imx1_dt_free_map,
-
};
static int imx1_pmx_set(struct pinctrl_dev *pctldev, unsigned selector,
diff --git a/drivers/pinctrl/intel/pinctrl-intel.c b/drivers/pinctrl/intel/pinctrl-intel.c
index b6ef191..8085782 100644
--- a/drivers/pinctrl/intel/pinctrl-intel.c
+++ b/drivers/pinctrl/intel/pinctrl-intel.c
@@ -29,6 +29,16 @@
#define REVID_SHIFT 16
#define REVID_MASK GENMASK(31, 16)
+#define CAPLIST 0x004
+#define CAPLIST_ID_SHIFT 16
+#define CAPLIST_ID_MASK GENMASK(23, 16)
+#define CAPLIST_ID_GPIO_HW_INFO 1
+#define CAPLIST_ID_PWM 2
+#define CAPLIST_ID_BLINK 3
+#define CAPLIST_ID_EXP 4
+#define CAPLIST_NEXT_SHIFT 0
+#define CAPLIST_NEXT_MASK GENMASK(15, 0)
+
#define PADBAR 0x00c
#define PADOWN_BITS 4
@@ -1321,34 +1331,19 @@
return 0;
}
-static int intel_pinctrl_add_padgroups(struct intel_pinctrl *pctrl,
- struct intel_community *community)
+static int intel_pinctrl_add_padgroups_by_gpps(struct intel_pinctrl *pctrl,
+ struct intel_community *community)
{
struct intel_padgroup *gpps;
- unsigned int npins = community->npins;
unsigned int padown_num = 0;
- size_t ngpps, i;
-
- if (community->gpps)
- ngpps = community->ngpps;
- else
- ngpps = DIV_ROUND_UP(community->npins, community->gpp_size);
+ size_t i, ngpps = community->ngpps;
gpps = devm_kcalloc(pctrl->dev, ngpps, sizeof(*gpps), GFP_KERNEL);
if (!gpps)
return -ENOMEM;
for (i = 0; i < ngpps; i++) {
- if (community->gpps) {
- gpps[i] = community->gpps[i];
- } else {
- unsigned int gpp_size = community->gpp_size;
-
- gpps[i].reg_num = i;
- gpps[i].base = community->pin_base + i * gpp_size;
- gpps[i].size = min(gpp_size, npins);
- npins -= gpps[i].size;
- }
+ gpps[i] = community->gpps[i];
if (gpps[i].size > 32)
return -EINVAL;
@@ -1367,6 +1362,38 @@
}
gpps[i].padown_num = padown_num;
+ padown_num += DIV_ROUND_UP(gpps[i].size * 4, 32);
+ }
+
+ community->gpps = gpps;
+
+ return 0;
+}
+
+static int intel_pinctrl_add_padgroups_by_size(struct intel_pinctrl *pctrl,
+ struct intel_community *community)
+{
+ struct intel_padgroup *gpps;
+ unsigned int npins = community->npins;
+ unsigned int padown_num = 0;
+ size_t i, ngpps = DIV_ROUND_UP(npins, community->gpp_size);
+
+ if (community->gpp_size > 32)
+ return -EINVAL;
+
+ gpps = devm_kcalloc(pctrl->dev, ngpps, sizeof(*gpps), GFP_KERNEL);
+ if (!gpps)
+ return -ENOMEM;
+
+ for (i = 0; i < ngpps; i++) {
+ unsigned int gpp_size = community->gpp_size;
+
+ gpps[i].reg_num = i;
+ gpps[i].base = community->pin_base + i * gpp_size;
+ gpps[i].size = min(gpp_size, npins);
+ npins -= gpps[i].size;
+
+ gpps[i].padown_num = padown_num;
/*
* In older hardware the number of padown registers per
@@ -1455,7 +1482,8 @@
for (i = 0; i < pctrl->ncommunities; i++) {
struct intel_community *community = &pctrl->communities[i];
void __iomem *regs;
- u32 padbar;
+ u32 offset;
+ u32 value;
*community = pctrl->soc->communities[i];
@@ -1463,27 +1491,48 @@
if (IS_ERR(regs))
return PTR_ERR(regs);
- /*
- * Determine community features based on the revision if
- * not specified already.
- */
- if (!community->features) {
- u32 rev;
-
- rev = (readl(regs + REVID) & REVID_MASK) >> REVID_SHIFT;
- if (rev >= 0x94) {
- community->features |= PINCTRL_FEATURE_DEBOUNCE;
- community->features |= PINCTRL_FEATURE_1K_PD;
- }
+ /* Determine community features based on the revision */
+ value = readl(regs + REVID);
+ if (((value & REVID_MASK) >> REVID_SHIFT) >= 0x94) {
+ community->features |= PINCTRL_FEATURE_DEBOUNCE;
+ community->features |= PINCTRL_FEATURE_1K_PD;
}
+ /* Determine community features based on the capabilities */
+ offset = CAPLIST;
+ do {
+ value = readl(regs + offset);
+ switch ((value & CAPLIST_ID_MASK) >> CAPLIST_ID_SHIFT) {
+ case CAPLIST_ID_GPIO_HW_INFO:
+ community->features |= PINCTRL_FEATURE_GPIO_HW_INFO;
+ break;
+ case CAPLIST_ID_PWM:
+ community->features |= PINCTRL_FEATURE_PWM;
+ break;
+ case CAPLIST_ID_BLINK:
+ community->features |= PINCTRL_FEATURE_BLINK;
+ break;
+ case CAPLIST_ID_EXP:
+ community->features |= PINCTRL_FEATURE_EXP;
+ break;
+ default:
+ break;
+ }
+ offset = (value & CAPLIST_NEXT_MASK) >> CAPLIST_NEXT_SHIFT;
+ } while (offset);
+
+ dev_dbg(&pdev->dev, "Community%d features: %#08x\n", i, community->features);
+
/* Read offset of the pad configuration registers */
- padbar = readl(regs + PADBAR);
+ offset = readl(regs + PADBAR);
community->regs = regs;
- community->pad_regs = regs + padbar;
+ community->pad_regs = regs + offset;
- ret = intel_pinctrl_add_padgroups(pctrl, community);
+ if (community->gpps)
+ ret = intel_pinctrl_add_padgroups_by_gpps(pctrl, community);
+ else
+ ret = intel_pinctrl_add_padgroups_by_size(pctrl, community);
if (ret)
return ret;
}
diff --git a/drivers/pinctrl/intel/pinctrl-intel.h b/drivers/pinctrl/intel/pinctrl-intel.h
index ad34b7a..c4fef03 100644
--- a/drivers/pinctrl/intel/pinctrl-intel.h
+++ b/drivers/pinctrl/intel/pinctrl-intel.h
@@ -143,6 +143,10 @@
/* Additional features supported by the hardware */
#define PINCTRL_FEATURE_DEBOUNCE BIT(0)
#define PINCTRL_FEATURE_1K_PD BIT(1)
+#define PINCTRL_FEATURE_GPIO_HW_INFO BIT(2)
+#define PINCTRL_FEATURE_PWM BIT(3)
+#define PINCTRL_FEATURE_BLINK BIT(4)
+#define PINCTRL_FEATURE_EXP BIT(5)
/**
* PIN_GROUP - Declare a pin group
diff --git a/drivers/pinctrl/intel/pinctrl-tigerlake.c b/drivers/pinctrl/intel/pinctrl-tigerlake.c
index 3e354e0..75b6d66 100644
--- a/drivers/pinctrl/intel/pinctrl-tigerlake.c
+++ b/drivers/pinctrl/intel/pinctrl-tigerlake.c
@@ -748,6 +748,7 @@
static const struct acpi_device_id tgl_pinctrl_acpi_match[] = {
{ "INT34C5", (kernel_ulong_t)&tgllp_soc_data },
{ "INT34C6", (kernel_ulong_t)&tglh_soc_data },
+ { "INTC1055", (kernel_ulong_t)&tgllp_soc_data },
{ }
};
MODULE_DEVICE_TABLE(acpi, tgl_pinctrl_acpi_match);
diff --git a/drivers/pinctrl/mediatek/mtk-eint.c b/drivers/pinctrl/mediatek/mtk-eint.c
index 22736f6..3b9b5db 100644
--- a/drivers/pinctrl/mediatek/mtk-eint.c
+++ b/drivers/pinctrl/mediatek/mtk-eint.c
@@ -157,6 +157,7 @@
static int mtk_eint_set_type(struct irq_data *d, unsigned int type)
{
struct mtk_eint *eint = irq_data_get_irq_chip_data(d);
+ bool masked;
u32 mask = BIT(d->hwirq & 0x1f);
void __iomem *reg;
@@ -173,6 +174,13 @@
else
eint->dual_edge[d->hwirq] = 0;
+ if (!mtk_eint_get_mask(eint, d->hwirq)) {
+ mtk_eint_mask(d);
+ masked = false;
+ } else {
+ masked = true;
+ }
+
if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_EDGE_FALLING)) {
reg = mtk_eint_get_offset(eint, d->hwirq, eint->regs->pol_clr);
writel(mask, reg);
@@ -189,8 +197,9 @@
writel(mask, reg);
}
- if (eint->dual_edge[d->hwirq])
- mtk_eint_flip_edge(eint, d->hwirq);
+ mtk_eint_ack(d);
+ if (!masked)
+ mtk_eint_unmask(d);
return 0;
}
diff --git a/drivers/pinctrl/mediatek/pinctrl-moore.c b/drivers/pinctrl/mediatek/pinctrl-moore.c
index 5e00f93..0fa7de4 100644
--- a/drivers/pinctrl/mediatek/pinctrl-moore.c
+++ b/drivers/pinctrl/mediatek/pinctrl-moore.c
@@ -514,8 +514,8 @@
chip->direction_output = mtk_gpio_direction_output;
chip->get = mtk_gpio_get;
chip->set = mtk_gpio_set;
- chip->to_irq = mtk_gpio_to_irq,
- chip->set_config = mtk_gpio_set_config,
+ chip->to_irq = mtk_gpio_to_irq;
+ chip->set_config = mtk_gpio_set_config;
chip->base = -1;
chip->ngpio = hw->soc->npins;
chip->of_node = np;
diff --git a/drivers/pinctrl/mediatek/pinctrl-paris.c b/drivers/pinctrl/mediatek/pinctrl-paris.c
index 039ce9b..da1f192 100644
--- a/drivers/pinctrl/mediatek/pinctrl-paris.c
+++ b/drivers/pinctrl/mediatek/pinctrl-paris.c
@@ -891,8 +891,8 @@
chip->direction_output = mtk_gpio_direction_output;
chip->get = mtk_gpio_get;
chip->set = mtk_gpio_set;
- chip->to_irq = mtk_gpio_to_irq,
- chip->set_config = mtk_gpio_set_config,
+ chip->to_irq = mtk_gpio_to_irq;
+ chip->set_config = mtk_gpio_set_config;
chip->base = -1;
chip->ngpio = hw->soc->npins;
chip->of_node = np;
diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c b/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c
index 68894e9..5a68e24 100644
--- a/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c
+++ b/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c
@@ -188,7 +188,6 @@
PIN_GRP_GPIO_2("led1_od", 12, 1, BIT(21), BIT(21), 0, "led"),
PIN_GRP_GPIO_2("led2_od", 13, 1, BIT(22), BIT(22), 0, "led"),
PIN_GRP_GPIO_2("led3_od", 14, 1, BIT(23), BIT(23), 0, "led"),
-
};
static struct armada_37xx_pin_group armada_37xx_sb_groups[] = {
diff --git a/drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c b/drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c
index 6de31b5..2535ca7 100644
--- a/drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c
+++ b/drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c
@@ -923,7 +923,7 @@
};
static const struct npcm7xx_pincfg pincfg[] = {
- /* PIN FUNCTION 1 FUNCTION 2 FUNCTION 3 FLAGS */
+ /* PIN FUNCTION 1 FUNCTION 2 FUNCTION 3 FLAGS */
NPCM7XX_PINCFG(0, iox1, MFSEL1, 30, none, NONE, 0, none, NONE, 0, 0),
NPCM7XX_PINCFG(1, iox1, MFSEL1, 30, none, NONE, 0, none, NONE, 0, DS(8, 12)),
NPCM7XX_PINCFG(2, iox1, MFSEL1, 30, none, NONE, 0, none, NONE, 0, DS(8, 12)),
diff --git a/drivers/pinctrl/pinctrl-at91-pio4.c b/drivers/pinctrl/pinctrl-at91-pio4.c
index 36c6078..e71ebccc 100644
--- a/drivers/pinctrl/pinctrl-at91-pio4.c
+++ b/drivers/pinctrl/pinctrl-at91-pio4.c
@@ -36,6 +36,7 @@
#define ATMEL_PIO_DIR_MASK BIT(8)
#define ATMEL_PIO_PUEN_MASK BIT(9)
#define ATMEL_PIO_PDEN_MASK BIT(10)
+#define ATMEL_PIO_SR_MASK BIT(11)
#define ATMEL_PIO_IFEN_MASK BIT(12)
#define ATMEL_PIO_IFSCEN_MASK BIT(13)
#define ATMEL_PIO_OPD_MASK BIT(14)
@@ -76,10 +77,12 @@
* @nbanks: number of PIO banks
* @last_bank_count: number of lines in the last bank (can be less than
* the rest of the banks).
+ * @slew_rate_support: slew rate support
*/
struct atmel_pioctrl_data {
- unsigned nbanks;
- unsigned last_bank_count;
+ unsigned int nbanks;
+ unsigned int last_bank_count;
+ unsigned int slew_rate_support;
};
struct atmel_group {
@@ -88,11 +91,11 @@
};
struct atmel_pin {
- unsigned pin_id;
- unsigned mux;
- unsigned ioset;
- unsigned bank;
- unsigned line;
+ unsigned int pin_id;
+ unsigned int mux;
+ unsigned int ioset;
+ unsigned int bank;
+ unsigned int line;
const char *device;
};
@@ -117,20 +120,21 @@
* @pm_suspend_backup: backup/restore register values on suspend/resume
* @dev: device entry for the Atmel PIO controller.
* @node: node of the Atmel PIO controller.
+ * @slew_rate_support: slew rate support
*/
struct atmel_pioctrl {
void __iomem *reg_base;
struct clk *clk;
- unsigned nbanks;
+ unsigned int nbanks;
struct pinctrl_dev *pinctrl_dev;
struct atmel_group *groups;
const char * const *group_names;
struct atmel_pin **pins;
- unsigned npins;
+ unsigned int npins;
struct gpio_chip *gpio_chip;
struct irq_domain *irq_domain;
int *irqs;
- unsigned *pm_wakeup_sources;
+ unsigned int *pm_wakeup_sources;
struct {
u32 imr;
u32 odsr;
@@ -138,6 +142,7 @@
} *pm_suspend_backup;
struct device *dev;
struct device_node *node;
+ unsigned int slew_rate_support;
};
static const char * const atmel_functions[] = {
@@ -172,11 +177,11 @@
*/
}
-static int atmel_gpio_irq_set_type(struct irq_data *d, unsigned type)
+static int atmel_gpio_irq_set_type(struct irq_data *d, unsigned int type)
{
struct atmel_pioctrl *atmel_pioctrl = irq_data_get_irq_chip_data(d);
struct atmel_pin *pin = atmel_pioctrl->pins[d->hwirq];
- unsigned reg;
+ unsigned int reg;
atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_MSKR,
BIT(pin->line));
@@ -263,7 +268,7 @@
.irq_set_wake = atmel_gpio_irq_set_wake,
};
-static int atmel_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
+static int atmel_gpio_to_irq(struct gpio_chip *chip, unsigned int offset)
{
struct atmel_pioctrl *atmel_pioctrl = gpiochip_get_data(chip);
@@ -311,11 +316,12 @@
chained_irq_exit(chip, desc);
}
-static int atmel_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
+static int atmel_gpio_direction_input(struct gpio_chip *chip,
+ unsigned int offset)
{
struct atmel_pioctrl *atmel_pioctrl = gpiochip_get_data(chip);
struct atmel_pin *pin = atmel_pioctrl->pins[offset];
- unsigned reg;
+ unsigned int reg;
atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_MSKR,
BIT(pin->line));
@@ -326,11 +332,11 @@
return 0;
}
-static int atmel_gpio_get(struct gpio_chip *chip, unsigned offset)
+static int atmel_gpio_get(struct gpio_chip *chip, unsigned int offset)
{
struct atmel_pioctrl *atmel_pioctrl = gpiochip_get_data(chip);
struct atmel_pin *pin = atmel_pioctrl->pins[offset];
- unsigned reg;
+ unsigned int reg;
reg = atmel_gpio_read(atmel_pioctrl, pin->bank, ATMEL_PIO_PDSR);
@@ -364,12 +370,13 @@
return 0;
}
-static int atmel_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
+static int atmel_gpio_direction_output(struct gpio_chip *chip,
+ unsigned int offset,
int value)
{
struct atmel_pioctrl *atmel_pioctrl = gpiochip_get_data(chip);
struct atmel_pin *pin = atmel_pioctrl->pins[offset];
- unsigned reg;
+ unsigned int reg;
atmel_gpio_write(atmel_pioctrl, pin->bank,
value ? ATMEL_PIO_SODR : ATMEL_PIO_CODR,
@@ -384,7 +391,7 @@
return 0;
}
-static void atmel_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
+static void atmel_gpio_set(struct gpio_chip *chip, unsigned int offset, int val)
{
struct atmel_pioctrl *atmel_pioctrl = gpiochip_get_data(chip);
struct atmel_pin *pin = atmel_pioctrl->pins[offset];
@@ -440,11 +447,11 @@
/* --- PINCTRL --- */
static unsigned int atmel_pin_config_read(struct pinctrl_dev *pctldev,
- unsigned pin_id)
+ unsigned int pin_id)
{
struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
- unsigned bank = atmel_pioctrl->pins[pin_id]->bank;
- unsigned line = atmel_pioctrl->pins[pin_id]->line;
+ unsigned int bank = atmel_pioctrl->pins[pin_id]->bank;
+ unsigned int line = atmel_pioctrl->pins[pin_id]->line;
void __iomem *addr = atmel_pioctrl->reg_base
+ bank * ATMEL_PIO_BANK_OFFSET;
@@ -456,11 +463,11 @@
}
static void atmel_pin_config_write(struct pinctrl_dev *pctldev,
- unsigned pin_id, u32 conf)
+ unsigned int pin_id, u32 conf)
{
struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
- unsigned bank = atmel_pioctrl->pins[pin_id]->bank;
- unsigned line = atmel_pioctrl->pins[pin_id]->line;
+ unsigned int bank = atmel_pioctrl->pins[pin_id]->bank;
+ unsigned int line = atmel_pioctrl->pins[pin_id]->line;
void __iomem *addr = atmel_pioctrl->reg_base
+ bank * ATMEL_PIO_BANK_OFFSET;
@@ -478,7 +485,7 @@
}
static const char *atmel_pctl_get_group_name(struct pinctrl_dev *pctldev,
- unsigned selector)
+ unsigned int selector)
{
struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
@@ -486,19 +493,20 @@
}
static int atmel_pctl_get_group_pins(struct pinctrl_dev *pctldev,
- unsigned selector, const unsigned **pins,
- unsigned *num_pins)
+ unsigned int selector,
+ const unsigned int **pins,
+ unsigned int *num_pins)
{
struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
- *pins = (unsigned *)&atmel_pioctrl->groups[selector].pin;
+ *pins = (unsigned int *)&atmel_pioctrl->groups[selector].pin;
*num_pins = 1;
return 0;
}
static struct atmel_group *
-atmel_pctl_find_group_by_pin(struct pinctrl_dev *pctldev, unsigned pin)
+atmel_pctl_find_group_by_pin(struct pinctrl_dev *pctldev, unsigned int pin)
{
struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
int i;
@@ -519,7 +527,7 @@
const char **func_name)
{
struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
- unsigned pin_id, func_id;
+ unsigned int pin_id, func_id;
struct atmel_group *grp;
pin_id = ATMEL_GET_PIN_NO(pinfunc);
@@ -549,10 +557,10 @@
static int atmel_pctl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
struct device_node *np,
struct pinctrl_map **map,
- unsigned *reserved_maps,
- unsigned *num_maps)
+ unsigned int *reserved_maps,
+ unsigned int *num_maps)
{
- unsigned num_pins, num_configs, reserve;
+ unsigned int num_pins, num_configs, reserve;
unsigned long *configs;
struct property *pins;
u32 pinfunc;
@@ -623,10 +631,10 @@
static int atmel_pctl_dt_node_to_map(struct pinctrl_dev *pctldev,
struct device_node *np_config,
struct pinctrl_map **map,
- unsigned *num_maps)
+ unsigned int *num_maps)
{
struct device_node *np;
- unsigned reserved_maps;
+ unsigned int reserved_maps;
int ret;
*map = NULL;
@@ -674,13 +682,13 @@
}
static const char *atmel_pmx_get_function_name(struct pinctrl_dev *pctldev,
- unsigned selector)
+ unsigned int selector)
{
return atmel_functions[selector];
}
static int atmel_pmx_get_function_groups(struct pinctrl_dev *pctldev,
- unsigned selector,
+ unsigned int selector,
const char * const **groups,
unsigned * const num_groups)
{
@@ -693,11 +701,11 @@
}
static int atmel_pmx_set_mux(struct pinctrl_dev *pctldev,
- unsigned function,
- unsigned group)
+ unsigned int function,
+ unsigned int group)
{
struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
- unsigned pin;
+ unsigned int pin;
u32 conf;
dev_dbg(pctldev->dev, "enable function %s group %s\n",
@@ -721,13 +729,13 @@
};
static int atmel_conf_pin_config_group_get(struct pinctrl_dev *pctldev,
- unsigned group,
+ unsigned int group,
unsigned long *config)
{
struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
- unsigned param = pinconf_to_config_param(*config), arg = 0;
+ unsigned int param = pinconf_to_config_param(*config), arg = 0;
struct atmel_group *grp = atmel_pioctrl->groups + group;
- unsigned pin_id = grp->pin;
+ unsigned int pin_id = grp->pin;
u32 res;
res = atmel_pin_config_read(pctldev, pin_id);
@@ -760,6 +768,13 @@
return -EINVAL;
arg = 1;
break;
+ case PIN_CONFIG_SLEW_RATE:
+ if (!atmel_pioctrl->slew_rate_support)
+ return -EOPNOTSUPP;
+ if (!(res & ATMEL_PIO_SR_MASK))
+ return -EINVAL;
+ arg = 1;
+ break;
case ATMEL_PIN_CONFIG_DRIVE_STRENGTH:
if (!(res & ATMEL_PIO_DRVSTR_MASK))
return -EINVAL;
@@ -774,25 +789,29 @@
}
static int atmel_conf_pin_config_group_set(struct pinctrl_dev *pctldev,
- unsigned group,
+ unsigned int group,
unsigned long *configs,
- unsigned num_configs)
+ unsigned int num_configs)
{
struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
struct atmel_group *grp = atmel_pioctrl->groups + group;
- unsigned bank, pin, pin_id = grp->pin;
+ unsigned int bank, pin, pin_id = grp->pin;
u32 mask, conf = 0;
int i;
conf = atmel_pin_config_read(pctldev, pin_id);
for (i = 0; i < num_configs; i++) {
- unsigned param = pinconf_to_config_param(configs[i]);
- unsigned arg = pinconf_to_config_argument(configs[i]);
+ unsigned int param = pinconf_to_config_param(configs[i]);
+ unsigned int arg = pinconf_to_config_argument(configs[i]);
dev_dbg(pctldev->dev, "%s: pin=%u, config=0x%lx\n",
__func__, pin_id, configs[i]);
+ /* Keep slew rate enabled by default. */
+ if (atmel_pioctrl->slew_rate_support)
+ conf |= ATMEL_PIO_SR_MASK;
+
switch (param) {
case PIN_CONFIG_BIAS_DISABLE:
conf &= (~ATMEL_PIO_PUEN_MASK);
@@ -850,6 +869,13 @@
ATMEL_PIO_SODR);
}
break;
+ case PIN_CONFIG_SLEW_RATE:
+ if (!atmel_pioctrl->slew_rate_support)
+ break;
+ /* And remove it if explicitly requested. */
+ if (arg == 0)
+ conf &= ~ATMEL_PIO_SR_MASK;
+ break;
case ATMEL_PIN_CONFIG_DRIVE_STRENGTH:
switch (arg) {
case ATMEL_PIO_DRVSTR_LO:
@@ -877,7 +903,8 @@
}
static void atmel_conf_pin_config_dbg_show(struct pinctrl_dev *pctldev,
- struct seq_file *s, unsigned pin_id)
+ struct seq_file *s,
+ unsigned int pin_id)
{
struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
u32 conf;
@@ -901,6 +928,8 @@
seq_printf(s, "%s ", "open-drain");
if (conf & ATMEL_PIO_SCHMITT_MASK)
seq_printf(s, "%s ", "schmitt");
+ if (atmel_pioctrl->slew_rate_support && (conf & ATMEL_PIO_SR_MASK))
+ seq_printf(s, "%s ", "slew-rate");
if (conf & ATMEL_PIO_DRVSTR_MASK) {
switch ((conf & ATMEL_PIO_DRVSTR_MASK) >> ATMEL_PIO_DRVSTR_OFFSET) {
case ATMEL_PIO_DRVSTR_ME:
@@ -994,6 +1023,7 @@
static const struct atmel_pioctrl_data microchip_sama7g5_pioctrl_data = {
.nbanks = 5,
.last_bank_count = 8, /* sama7g5 has only PE0 to PE7 */
+ .slew_rate_support = 1,
};
static const struct of_device_id atmel_pctrl_of_match[] = {
@@ -1039,6 +1069,7 @@
atmel_pioctrl->npins -= ATMEL_PIO_NPINS_PER_BANK;
atmel_pioctrl->npins += atmel_pioctrl_data->last_bank_count;
}
+ atmel_pioctrl->slew_rate_support = atmel_pioctrl_data->slew_rate_support;
atmel_pioctrl->reg_base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(atmel_pioctrl->reg_base))
@@ -1081,8 +1112,8 @@
return -ENOMEM;
for (i = 0 ; i < atmel_pioctrl->npins; i++) {
struct atmel_group *group = atmel_pioctrl->groups + i;
- unsigned bank = ATMEL_PIO_BANK(i);
- unsigned line = ATMEL_PIO_LINE(i);
+ unsigned int bank = ATMEL_PIO_BANK(i);
+ unsigned int line = ATMEL_PIO_LINE(i);
atmel_pioctrl->pins[i] = devm_kzalloc(dev,
sizeof(**atmel_pioctrl->pins), GFP_KERNEL);
diff --git a/drivers/pinctrl/pinctrl-at91.c b/drivers/pinctrl/pinctrl-at91.c
index 72edc67..8003d1b 100644
--- a/drivers/pinctrl/pinctrl-at91.c
+++ b/drivers/pinctrl/pinctrl-at91.c
@@ -733,7 +733,6 @@
.get_slewrate = at91_mux_sam9x60_get_slewrate,
.set_slewrate = at91_mux_sam9x60_set_slewrate,
.irq_type = alt_gpio_irq_type,
-
};
static struct at91_pinctrl_mux_ops sama5d3_ops = {
@@ -1742,7 +1741,7 @@
gpio_irqchip->irq_disable = gpio_irq_mask;
gpio_irqchip->irq_mask = gpio_irq_mask;
gpio_irqchip->irq_unmask = gpio_irq_unmask;
- gpio_irqchip->irq_set_wake = gpio_irq_set_wake,
+ gpio_irqchip->irq_set_wake = gpio_irq_set_wake;
gpio_irqchip->irq_set_type = at91_gpio->ops->irq_type;
/* Disable irqs of this PIO controller */
diff --git a/drivers/pinctrl/pinctrl-coh901.c b/drivers/pinctrl/pinctrl-coh901.c
deleted file mode 100644
index 2905348..0000000
--- a/drivers/pinctrl/pinctrl-coh901.c
+++ /dev/null
@@ -1,774 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * U300 GPIO module.
- *
- * Copyright (C) 2007-2012 ST-Ericsson AB
- * COH 901 571/3 - Used in DB3210 (U365 2.0) and DB3350 (U335 1.0)
- * Author: Linus Walleij <linus.walleij@linaro.org>
- * Author: Jonas Aaberg <jonas.aberg@stericsson.com>
- */
-#include <linux/module.h>
-#include <linux/interrupt.h>
-#include <linux/delay.h>
-#include <linux/errno.h>
-#include <linux/io.h>
-#include <linux/clk.h>
-#include <linux/err.h>
-#include <linux/platform_device.h>
-#include <linux/gpio/driver.h>
-#include <linux/slab.h>
-#include <linux/pinctrl/consumer.h>
-#include <linux/pinctrl/pinconf-generic.h>
-#include "pinctrl-coh901.h"
-
-#define U300_GPIO_PORT_STRIDE (0x30)
-/*
- * Control Register 32bit (R/W)
- * bit 15-9 (mask 0x0000FE00) contains the number of cores. 8*cores
- * gives the number of GPIO pins.
- * bit 8-2 (mask 0x000001FC) contains the core version ID.
- */
-#define U300_GPIO_CR (0x00)
-#define U300_GPIO_CR_SYNC_SEL_ENABLE (0x00000002UL)
-#define U300_GPIO_CR_BLOCK_CLKRQ_ENABLE (0x00000001UL)
-#define U300_GPIO_PXPDIR (0x04)
-#define U300_GPIO_PXPDOR (0x08)
-#define U300_GPIO_PXPCR (0x0C)
-#define U300_GPIO_PXPCR_ALL_PINS_MODE_MASK (0x0000FFFFUL)
-#define U300_GPIO_PXPCR_PIN_MODE_MASK (0x00000003UL)
-#define U300_GPIO_PXPCR_PIN_MODE_SHIFT (0x00000002UL)
-#define U300_GPIO_PXPCR_PIN_MODE_INPUT (0x00000000UL)
-#define U300_GPIO_PXPCR_PIN_MODE_OUTPUT_PUSH_PULL (0x00000001UL)
-#define U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_DRAIN (0x00000002UL)
-#define U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_SOURCE (0x00000003UL)
-#define U300_GPIO_PXPER (0x10)
-#define U300_GPIO_PXPER_ALL_PULL_UP_DISABLE_MASK (0x000000FFUL)
-#define U300_GPIO_PXPER_PULL_UP_DISABLE (0x00000001UL)
-#define U300_GPIO_PXIEV (0x14)
-#define U300_GPIO_PXIEN (0x18)
-#define U300_GPIO_PXIFR (0x1C)
-#define U300_GPIO_PXICR (0x20)
-#define U300_GPIO_PXICR_ALL_IRQ_CONFIG_MASK (0x000000FFUL)
-#define U300_GPIO_PXICR_IRQ_CONFIG_MASK (0x00000001UL)
-#define U300_GPIO_PXICR_IRQ_CONFIG_FALLING_EDGE (0x00000000UL)
-#define U300_GPIO_PXICR_IRQ_CONFIG_RISING_EDGE (0x00000001UL)
-
-/* 8 bits per port, no version has more than 7 ports */
-#define U300_GPIO_NUM_PORTS 7
-#define U300_GPIO_PINS_PER_PORT 8
-#define U300_GPIO_MAX (U300_GPIO_PINS_PER_PORT * U300_GPIO_NUM_PORTS)
-
-struct u300_gpio_port {
- struct u300_gpio *gpio;
- char name[8];
- int irq;
- int number;
- u8 toggle_edge_mode;
-};
-
-struct u300_gpio {
- struct gpio_chip chip;
- struct u300_gpio_port ports[U300_GPIO_NUM_PORTS];
- struct clk *clk;
- void __iomem *base;
- struct device *dev;
- u32 stride;
- /* Register offsets */
- u32 pcr;
- u32 dor;
- u32 dir;
- u32 per;
- u32 icr;
- u32 ien;
- u32 iev;
-};
-
-/*
- * Macro to expand to read a specific register found in the "gpio"
- * struct. It requires the struct u300_gpio *gpio variable to exist in
- * its context. It calculates the port offset from the given pin
- * offset, muliplies by the port stride and adds the register offset
- * so it provides a pointer to the desired register.
- */
-#define U300_PIN_REG(pin, reg) \
- (gpio->base + (pin >> 3) * gpio->stride + gpio->reg)
-
-/*
- * Provides a bitmask for a specific gpio pin inside an 8-bit GPIO
- * register.
- */
-#define U300_PIN_BIT(pin) \
- (1 << (pin & 0x07))
-
-struct u300_gpio_confdata {
- u16 bias_mode;
- bool output;
- int outval;
-};
-
-#define U300_FLOATING_INPUT { \
- .bias_mode = PIN_CONFIG_BIAS_HIGH_IMPEDANCE, \
- .output = false, \
-}
-
-#define U300_PULL_UP_INPUT { \
- .bias_mode = PIN_CONFIG_BIAS_PULL_UP, \
- .output = false, \
-}
-
-#define U300_OUTPUT_LOW { \
- .output = true, \
- .outval = 0, \
-}
-
-#define U300_OUTPUT_HIGH { \
- .output = true, \
- .outval = 1, \
-}
-
-/* Initial configuration */
-static const struct u300_gpio_confdata __initconst
-bs335_gpio_config[U300_GPIO_NUM_PORTS][U300_GPIO_PINS_PER_PORT] = {
- /* Port 0, pins 0-7 */
- {
- U300_FLOATING_INPUT,
- U300_OUTPUT_HIGH,
- U300_FLOATING_INPUT,
- U300_OUTPUT_LOW,
- U300_OUTPUT_LOW,
- U300_OUTPUT_LOW,
- U300_OUTPUT_LOW,
- U300_OUTPUT_LOW,
- },
- /* Port 1, pins 0-7 */
- {
- U300_OUTPUT_LOW,
- U300_OUTPUT_LOW,
- U300_OUTPUT_LOW,
- U300_PULL_UP_INPUT,
- U300_FLOATING_INPUT,
- U300_OUTPUT_HIGH,
- U300_OUTPUT_LOW,
- U300_OUTPUT_LOW,
- },
- /* Port 2, pins 0-7 */
- {
- U300_FLOATING_INPUT,
- U300_FLOATING_INPUT,
- U300_FLOATING_INPUT,
- U300_FLOATING_INPUT,
- U300_OUTPUT_LOW,
- U300_PULL_UP_INPUT,
- U300_OUTPUT_LOW,
- U300_PULL_UP_INPUT,
- },
- /* Port 3, pins 0-7 */
- {
- U300_PULL_UP_INPUT,
- U300_OUTPUT_LOW,
- U300_FLOATING_INPUT,
- U300_FLOATING_INPUT,
- U300_FLOATING_INPUT,
- U300_FLOATING_INPUT,
- U300_FLOATING_INPUT,
- U300_FLOATING_INPUT,
- },
- /* Port 4, pins 0-7 */
- {
- U300_FLOATING_INPUT,
- U300_FLOATING_INPUT,
- U300_FLOATING_INPUT,
- U300_FLOATING_INPUT,
- U300_FLOATING_INPUT,
- U300_FLOATING_INPUT,
- U300_FLOATING_INPUT,
- U300_FLOATING_INPUT,
- },
- /* Port 5, pins 0-7 */
- {
- U300_FLOATING_INPUT,
- U300_FLOATING_INPUT,
- U300_FLOATING_INPUT,
- U300_FLOATING_INPUT,
- U300_FLOATING_INPUT,
- U300_FLOATING_INPUT,
- U300_FLOATING_INPUT,
- U300_FLOATING_INPUT,
- },
- /* Port 6, pind 0-7 */
- {
- U300_FLOATING_INPUT,
- U300_FLOATING_INPUT,
- U300_FLOATING_INPUT,
- U300_FLOATING_INPUT,
- U300_FLOATING_INPUT,
- U300_FLOATING_INPUT,
- U300_FLOATING_INPUT,
- U300_FLOATING_INPUT,
- }
-};
-
-static int u300_gpio_get(struct gpio_chip *chip, unsigned offset)
-{
- struct u300_gpio *gpio = gpiochip_get_data(chip);
-
- return !!(readl(U300_PIN_REG(offset, dir)) & U300_PIN_BIT(offset));
-}
-
-static void u300_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
-{
- struct u300_gpio *gpio = gpiochip_get_data(chip);
- unsigned long flags;
- u32 val;
-
- local_irq_save(flags);
-
- val = readl(U300_PIN_REG(offset, dor));
- if (value)
- writel(val | U300_PIN_BIT(offset), U300_PIN_REG(offset, dor));
- else
- writel(val & ~U300_PIN_BIT(offset), U300_PIN_REG(offset, dor));
-
- local_irq_restore(flags);
-}
-
-static int u300_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
-{
- struct u300_gpio *gpio = gpiochip_get_data(chip);
- unsigned long flags;
- u32 val;
-
- local_irq_save(flags);
- val = readl(U300_PIN_REG(offset, pcr));
- /* Mask out this pin, note 2 bits per setting */
- val &= ~(U300_GPIO_PXPCR_PIN_MODE_MASK << ((offset & 0x07) << 1));
- writel(val, U300_PIN_REG(offset, pcr));
- local_irq_restore(flags);
- return 0;
-}
-
-static int u300_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
- int value)
-{
- struct u300_gpio *gpio = gpiochip_get_data(chip);
- unsigned long flags;
- u32 oldmode;
- u32 val;
-
- local_irq_save(flags);
- val = readl(U300_PIN_REG(offset, pcr));
- /*
- * Drive mode must be set by the special mode set function, set
- * push/pull mode by default if no mode has been selected.
- */
- oldmode = val & (U300_GPIO_PXPCR_PIN_MODE_MASK <<
- ((offset & 0x07) << 1));
- /* mode = 0 means input, else some mode is already set */
- if (oldmode == 0) {
- val &= ~(U300_GPIO_PXPCR_PIN_MODE_MASK <<
- ((offset & 0x07) << 1));
- val |= (U300_GPIO_PXPCR_PIN_MODE_OUTPUT_PUSH_PULL
- << ((offset & 0x07) << 1));
- writel(val, U300_PIN_REG(offset, pcr));
- }
- u300_gpio_set(chip, offset, value);
- local_irq_restore(flags);
- return 0;
-}
-
-/* Returning -EINVAL means "supported but not available" */
-int u300_gpio_config_get(struct gpio_chip *chip,
- unsigned offset,
- unsigned long *config)
-{
- struct u300_gpio *gpio = gpiochip_get_data(chip);
- enum pin_config_param param = (enum pin_config_param) *config;
- bool biasmode;
- u32 drmode;
-
- /* One bit per pin, clamp to bool range */
- biasmode = !!(readl(U300_PIN_REG(offset, per)) & U300_PIN_BIT(offset));
-
- /* Mask out the two bits for this pin and shift to bits 0,1 */
- drmode = readl(U300_PIN_REG(offset, pcr));
- drmode &= (U300_GPIO_PXPCR_PIN_MODE_MASK << ((offset & 0x07) << 1));
- drmode >>= ((offset & 0x07) << 1);
-
- switch (param) {
- case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
- *config = 0;
- if (biasmode)
- return 0;
- else
- return -EINVAL;
- break;
- case PIN_CONFIG_BIAS_PULL_UP:
- *config = 0;
- if (!biasmode)
- return 0;
- else
- return -EINVAL;
- break;
- case PIN_CONFIG_DRIVE_PUSH_PULL:
- *config = 0;
- if (drmode == U300_GPIO_PXPCR_PIN_MODE_OUTPUT_PUSH_PULL)
- return 0;
- else
- return -EINVAL;
- break;
- case PIN_CONFIG_DRIVE_OPEN_DRAIN:
- *config = 0;
- if (drmode == U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_DRAIN)
- return 0;
- else
- return -EINVAL;
- break;
- case PIN_CONFIG_DRIVE_OPEN_SOURCE:
- *config = 0;
- if (drmode == U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_SOURCE)
- return 0;
- else
- return -EINVAL;
- break;
- default:
- break;
- }
- return -ENOTSUPP;
-}
-
-int u300_gpio_config_set(struct gpio_chip *chip, unsigned offset,
- enum pin_config_param param)
-{
- struct u300_gpio *gpio = gpiochip_get_data(chip);
- unsigned long flags;
- u32 val;
-
- local_irq_save(flags);
- switch (param) {
- case PIN_CONFIG_BIAS_DISABLE:
- case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
- val = readl(U300_PIN_REG(offset, per));
- writel(val | U300_PIN_BIT(offset), U300_PIN_REG(offset, per));
- break;
- case PIN_CONFIG_BIAS_PULL_UP:
- val = readl(U300_PIN_REG(offset, per));
- writel(val & ~U300_PIN_BIT(offset), U300_PIN_REG(offset, per));
- break;
- case PIN_CONFIG_DRIVE_PUSH_PULL:
- val = readl(U300_PIN_REG(offset, pcr));
- val &= ~(U300_GPIO_PXPCR_PIN_MODE_MASK
- << ((offset & 0x07) << 1));
- val |= (U300_GPIO_PXPCR_PIN_MODE_OUTPUT_PUSH_PULL
- << ((offset & 0x07) << 1));
- writel(val, U300_PIN_REG(offset, pcr));
- break;
- case PIN_CONFIG_DRIVE_OPEN_DRAIN:
- val = readl(U300_PIN_REG(offset, pcr));
- val &= ~(U300_GPIO_PXPCR_PIN_MODE_MASK
- << ((offset & 0x07) << 1));
- val |= (U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_DRAIN
- << ((offset & 0x07) << 1));
- writel(val, U300_PIN_REG(offset, pcr));
- break;
- case PIN_CONFIG_DRIVE_OPEN_SOURCE:
- val = readl(U300_PIN_REG(offset, pcr));
- val &= ~(U300_GPIO_PXPCR_PIN_MODE_MASK
- << ((offset & 0x07) << 1));
- val |= (U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_SOURCE
- << ((offset & 0x07) << 1));
- writel(val, U300_PIN_REG(offset, pcr));
- break;
- default:
- local_irq_restore(flags);
- dev_err(gpio->dev, "illegal configuration requested\n");
- return -EINVAL;
- }
- local_irq_restore(flags);
- return 0;
-}
-
-static const struct gpio_chip u300_gpio_chip = {
- .label = "u300-gpio-chip",
- .owner = THIS_MODULE,
- .request = gpiochip_generic_request,
- .free = gpiochip_generic_free,
- .get = u300_gpio_get,
- .set = u300_gpio_set,
- .direction_input = u300_gpio_direction_input,
- .direction_output = u300_gpio_direction_output,
-};
-
-static void u300_toggle_trigger(struct u300_gpio *gpio, unsigned offset)
-{
- u32 val;
-
- val = readl(U300_PIN_REG(offset, icr));
- /* Set mode depending on state */
- if (u300_gpio_get(&gpio->chip, offset)) {
- /* High now, let's trigger on falling edge next then */
- writel(val & ~U300_PIN_BIT(offset), U300_PIN_REG(offset, icr));
- dev_dbg(gpio->dev, "next IRQ on falling edge on pin %d\n",
- offset);
- } else {
- /* Low now, let's trigger on rising edge next then */
- writel(val | U300_PIN_BIT(offset), U300_PIN_REG(offset, icr));
- dev_dbg(gpio->dev, "next IRQ on rising edge on pin %d\n",
- offset);
- }
-}
-
-static int u300_gpio_irq_type(struct irq_data *d, unsigned trigger)
-{
- struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
- struct u300_gpio *gpio = gpiochip_get_data(chip);
- struct u300_gpio_port *port = &gpio->ports[d->hwirq >> 3];
- int offset = d->hwirq;
- u32 val;
-
- if ((trigger & IRQF_TRIGGER_RISING) &&
- (trigger & IRQF_TRIGGER_FALLING)) {
- /*
- * The GPIO block can only trigger on falling OR rising edges,
- * not both. So we need to toggle the mode whenever the pin
- * goes from one state to the other with a special state flag
- */
- dev_dbg(gpio->dev,
- "trigger on both rising and falling edge on pin %d\n",
- offset);
- port->toggle_edge_mode |= U300_PIN_BIT(offset);
- u300_toggle_trigger(gpio, offset);
- } else if (trigger & IRQF_TRIGGER_RISING) {
- dev_dbg(gpio->dev, "trigger on rising edge on pin %d\n",
- offset);
- val = readl(U300_PIN_REG(offset, icr));
- writel(val | U300_PIN_BIT(offset), U300_PIN_REG(offset, icr));
- port->toggle_edge_mode &= ~U300_PIN_BIT(offset);
- } else if (trigger & IRQF_TRIGGER_FALLING) {
- dev_dbg(gpio->dev, "trigger on falling edge on pin %d\n",
- offset);
- val = readl(U300_PIN_REG(offset, icr));
- writel(val & ~U300_PIN_BIT(offset), U300_PIN_REG(offset, icr));
- port->toggle_edge_mode &= ~U300_PIN_BIT(offset);
- }
-
- return 0;
-}
-
-static void u300_gpio_irq_enable(struct irq_data *d)
-{
- struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
- struct u300_gpio *gpio = gpiochip_get_data(chip);
- struct u300_gpio_port *port = &gpio->ports[d->hwirq >> 3];
- int offset = d->hwirq;
- u32 val;
- unsigned long flags;
-
- dev_dbg(gpio->dev, "enable IRQ for hwirq %lu on port %s, offset %d\n",
- d->hwirq, port->name, offset);
- local_irq_save(flags);
- val = readl(U300_PIN_REG(offset, ien));
- writel(val | U300_PIN_BIT(offset), U300_PIN_REG(offset, ien));
- local_irq_restore(flags);
-}
-
-static void u300_gpio_irq_disable(struct irq_data *d)
-{
- struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
- struct u300_gpio *gpio = gpiochip_get_data(chip);
- int offset = d->hwirq;
- u32 val;
- unsigned long flags;
-
- local_irq_save(flags);
- val = readl(U300_PIN_REG(offset, ien));
- writel(val & ~U300_PIN_BIT(offset), U300_PIN_REG(offset, ien));
- local_irq_restore(flags);
-}
-
-static struct irq_chip u300_gpio_irqchip = {
- .name = "u300-gpio-irqchip",
- .irq_enable = u300_gpio_irq_enable,
- .irq_disable = u300_gpio_irq_disable,
- .irq_set_type = u300_gpio_irq_type,
-};
-
-static void u300_gpio_irq_handler(struct irq_desc *desc)
-{
- unsigned int irq = irq_desc_get_irq(desc);
- struct irq_chip *parent_chip = irq_desc_get_chip(desc);
- struct gpio_chip *chip = irq_desc_get_handler_data(desc);
- struct u300_gpio *gpio = gpiochip_get_data(chip);
- struct u300_gpio_port *port = &gpio->ports[irq - chip->base];
- int pinoffset = port->number << 3; /* get the right stride */
- unsigned long val;
-
- chained_irq_enter(parent_chip, desc);
-
- /* Read event register */
- val = readl(U300_PIN_REG(pinoffset, iev));
- /* Mask relevant bits */
- val &= 0xFFU; /* 8 bits per port */
- /* ACK IRQ (clear event) */
- writel(val, U300_PIN_REG(pinoffset, iev));
-
- /* Call IRQ handler */
- if (val != 0) {
- int irqoffset;
-
- for_each_set_bit(irqoffset, &val, U300_GPIO_PINS_PER_PORT) {
- int offset = pinoffset + irqoffset;
- int pin_irq = irq_find_mapping(chip->irq.domain, offset);
-
- dev_dbg(gpio->dev, "GPIO IRQ %d on pin %d\n",
- pin_irq, offset);
- generic_handle_irq(pin_irq);
- /*
- * Triggering IRQ on both rising and falling edge
- * needs mockery
- */
- if (port->toggle_edge_mode & U300_PIN_BIT(offset))
- u300_toggle_trigger(gpio, offset);
- }
- }
-
- chained_irq_exit(parent_chip, desc);
-}
-
-static void __init u300_gpio_init_pin(struct u300_gpio *gpio,
- int offset,
- const struct u300_gpio_confdata *conf)
-{
- /* Set mode: input or output */
- if (conf->output) {
- u300_gpio_direction_output(&gpio->chip, offset, conf->outval);
-
- /* Deactivate bias mode for output */
- u300_gpio_config_set(&gpio->chip, offset,
- PIN_CONFIG_BIAS_HIGH_IMPEDANCE);
-
- /* Set drive mode for output */
- u300_gpio_config_set(&gpio->chip, offset,
- PIN_CONFIG_DRIVE_PUSH_PULL);
-
- dev_dbg(gpio->dev, "set up pin %d as output, value: %d\n",
- offset, conf->outval);
- } else {
- u300_gpio_direction_input(&gpio->chip, offset);
-
- /* Always set output low on input pins */
- u300_gpio_set(&gpio->chip, offset, 0);
-
- /* Set bias mode for input */
- u300_gpio_config_set(&gpio->chip, offset, conf->bias_mode);
-
- dev_dbg(gpio->dev, "set up pin %d as input, bias: %04x\n",
- offset, conf->bias_mode);
- }
-}
-
-static void __init u300_gpio_init_coh901571(struct u300_gpio *gpio)
-{
- int i, j;
-
- /* Write default config and values to all pins */
- for (i = 0; i < U300_GPIO_NUM_PORTS; i++) {
- for (j = 0; j < 8; j++) {
- const struct u300_gpio_confdata *conf;
- int offset = (i*8) + j;
-
- conf = &bs335_gpio_config[i][j];
- u300_gpio_init_pin(gpio, offset, conf);
- }
- }
-}
-
-/*
- * Here we map a GPIO in the local gpio_chip pin space to a pin in
- * the local pinctrl pin space. The pin controller used is
- * pinctrl-u300.
- */
-struct coh901_pinpair {
- unsigned int offset;
- unsigned int pin_base;
-};
-
-#define COH901_PINRANGE(a, b) { .offset = a, .pin_base = b }
-
-static struct coh901_pinpair coh901_pintable[] = {
- COH901_PINRANGE(10, 426),
- COH901_PINRANGE(11, 180),
- COH901_PINRANGE(12, 165), /* MS/MMC card insertion */
- COH901_PINRANGE(13, 179),
- COH901_PINRANGE(14, 178),
- COH901_PINRANGE(16, 194),
- COH901_PINRANGE(17, 193),
- COH901_PINRANGE(18, 192),
- COH901_PINRANGE(19, 191),
- COH901_PINRANGE(20, 186),
- COH901_PINRANGE(21, 185),
- COH901_PINRANGE(22, 184),
- COH901_PINRANGE(23, 183),
- COH901_PINRANGE(24, 182),
- COH901_PINRANGE(25, 181),
-};
-
-static int __init u300_gpio_probe(struct platform_device *pdev)
-{
- struct u300_gpio *gpio;
- struct gpio_irq_chip *girq;
- int err = 0;
- int portno;
- u32 val;
- u32 ifr;
- int i;
-
- gpio = devm_kzalloc(&pdev->dev, sizeof(struct u300_gpio), GFP_KERNEL);
- if (gpio == NULL)
- return -ENOMEM;
-
- gpio->chip = u300_gpio_chip;
- gpio->chip.ngpio = U300_GPIO_NUM_PORTS * U300_GPIO_PINS_PER_PORT;
- gpio->chip.parent = &pdev->dev;
- gpio->chip.base = 0;
- gpio->dev = &pdev->dev;
-
- gpio->base = devm_platform_ioremap_resource(pdev, 0);
- if (IS_ERR(gpio->base))
- return PTR_ERR(gpio->base);
-
- gpio->clk = devm_clk_get(gpio->dev, NULL);
- if (IS_ERR(gpio->clk)) {
- err = PTR_ERR(gpio->clk);
- dev_err(gpio->dev, "could not get GPIO clock\n");
- return err;
- }
-
- err = clk_prepare_enable(gpio->clk);
- if (err) {
- dev_err(gpio->dev, "could not enable GPIO clock\n");
- return err;
- }
-
- dev_info(gpio->dev,
- "initializing GPIO Controller COH 901 571/3\n");
- gpio->stride = U300_GPIO_PORT_STRIDE;
- gpio->pcr = U300_GPIO_PXPCR;
- gpio->dor = U300_GPIO_PXPDOR;
- gpio->dir = U300_GPIO_PXPDIR;
- gpio->per = U300_GPIO_PXPER;
- gpio->icr = U300_GPIO_PXICR;
- gpio->ien = U300_GPIO_PXIEN;
- gpio->iev = U300_GPIO_PXIEV;
- ifr = U300_GPIO_PXIFR;
-
- val = readl(gpio->base + U300_GPIO_CR);
- dev_info(gpio->dev, "COH901571/3 block version: %d, " \
- "number of cores: %d totalling %d pins\n",
- ((val & 0x000001FC) >> 2),
- ((val & 0x0000FE00) >> 9),
- ((val & 0x0000FE00) >> 9) * 8);
- writel(U300_GPIO_CR_BLOCK_CLKRQ_ENABLE,
- gpio->base + U300_GPIO_CR);
- u300_gpio_init_coh901571(gpio);
-
- girq = &gpio->chip.irq;
- girq->chip = &u300_gpio_irqchip;
- girq->parent_handler = u300_gpio_irq_handler;
- girq->num_parents = U300_GPIO_NUM_PORTS;
- girq->parents = devm_kcalloc(gpio->dev, U300_GPIO_NUM_PORTS,
- sizeof(*girq->parents),
- GFP_KERNEL);
- if (!girq->parents) {
- err = -ENOMEM;
- goto err_dis_clk;
- }
- for (portno = 0 ; portno < U300_GPIO_NUM_PORTS; portno++) {
- struct u300_gpio_port *port = &gpio->ports[portno];
-
- snprintf(port->name, 8, "gpio%d", portno);
- port->number = portno;
- port->gpio = gpio;
-
- port->irq = platform_get_irq(pdev, portno);
- girq->parents[portno] = port->irq;
-
- /* Turns off irq force (test register) for this port */
- writel(0x0, gpio->base + portno * gpio->stride + ifr);
- }
- girq->default_type = IRQ_TYPE_EDGE_FALLING;
- girq->handler = handle_simple_irq;
-#ifdef CONFIG_OF_GPIO
- gpio->chip.of_node = pdev->dev.of_node;
-#endif
- err = gpiochip_add_data(&gpio->chip, gpio);
- if (err) {
- dev_err(gpio->dev, "unable to add gpiochip: %d\n", err);
- goto err_dis_clk;
- }
-
- /*
- * Add pinctrl pin ranges, the pin controller must be registered
- * at this point
- */
- for (i = 0; i < ARRAY_SIZE(coh901_pintable); i++) {
- struct coh901_pinpair *p = &coh901_pintable[i];
-
- err = gpiochip_add_pin_range(&gpio->chip, "pinctrl-u300",
- p->offset, p->pin_base, 1);
- if (err)
- goto err_no_range;
- }
-
- platform_set_drvdata(pdev, gpio);
-
- return 0;
-
-err_no_range:
- gpiochip_remove(&gpio->chip);
-err_dis_clk:
- clk_disable_unprepare(gpio->clk);
- dev_err(&pdev->dev, "module ERROR:%d\n", err);
- return err;
-}
-
-static int __exit u300_gpio_remove(struct platform_device *pdev)
-{
- struct u300_gpio *gpio = platform_get_drvdata(pdev);
-
- /* Turn off the GPIO block */
- writel(0x00000000U, gpio->base + U300_GPIO_CR);
-
- gpiochip_remove(&gpio->chip);
- clk_disable_unprepare(gpio->clk);
- return 0;
-}
-
-static const struct of_device_id u300_gpio_match[] = {
- { .compatible = "stericsson,gpio-coh901" },
- {},
-};
-
-static struct platform_driver u300_gpio_driver = {
- .driver = {
- .name = "u300-gpio",
- .of_match_table = u300_gpio_match,
- },
- .remove = __exit_p(u300_gpio_remove),
-};
-
-static int __init u300_gpio_init(void)
-{
- return platform_driver_probe(&u300_gpio_driver, u300_gpio_probe);
-}
-
-static void __exit u300_gpio_exit(void)
-{
- platform_driver_unregister(&u300_gpio_driver);
-}
-
-arch_initcall(u300_gpio_init);
-module_exit(u300_gpio_exit);
-
-MODULE_AUTHOR("Linus Walleij <linus.walleij@stericsson.com>");
-MODULE_DESCRIPTION("ST-Ericsson AB COH 901 335/COH 901 571/3 GPIO driver");
-MODULE_LICENSE("GPL");
diff --git a/drivers/pinctrl/pinctrl-coh901.h b/drivers/pinctrl/pinctrl-coh901.h
deleted file mode 100644
index ba26786..0000000
--- a/drivers/pinctrl/pinctrl-coh901.h
+++ /dev/null
@@ -1,6 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-int u300_gpio_config_get(struct gpio_chip *chip,
- unsigned offset,
- unsigned long *config);
-int u300_gpio_config_set(struct gpio_chip *chip, unsigned offset,
- enum pin_config_param param);
diff --git a/drivers/pinctrl/pinctrl-ingenic.c b/drivers/pinctrl/pinctrl-ingenic.c
index 3ea1634..f274612 100644
--- a/drivers/pinctrl/pinctrl-ingenic.c
+++ b/drivers/pinctrl/pinctrl-ingenic.c
@@ -376,12 +376,21 @@
0x26, 0x27, 0x28, 0x29,
0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, 0x30, 0x31,
};
-static int jz4760_lcd_24bit_pins[] = {
- 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47,
- 0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f,
- 0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57,
- 0x58, 0x59, 0x5a, 0x5b,
+static int jz4760_lcd_8bit_pins[] = {
+ 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x4c,
+ 0x4d, 0x52, 0x53,
};
+static int jz4760_lcd_16bit_pins[] = {
+ 0x4e, 0x4f, 0x50, 0x51, 0x56, 0x57, 0x58, 0x59,
+};
+static int jz4760_lcd_18bit_pins[] = {
+ 0x5a, 0x5b,
+};
+static int jz4760_lcd_24bit_pins[] = {
+ 0x40, 0x41, 0x4a, 0x4b, 0x54, 0x55,
+};
+static int jz4760_lcd_special_pins[] = { 0x40, 0x41, 0x4a, 0x54 };
+static int jz4760_lcd_generic_pins[] = { 0x49, };
static int jz4760_pwm_pwm0_pins[] = { 0x80, };
static int jz4760_pwm_pwm1_pins[] = { 0x81, };
static int jz4760_pwm_pwm2_pins[] = { 0x82, };
@@ -390,6 +399,7 @@
static int jz4760_pwm_pwm5_pins[] = { 0x85, };
static int jz4760_pwm_pwm6_pins[] = { 0x6a, };
static int jz4760_pwm_pwm7_pins[] = { 0x6b, };
+static int jz4760_otg_pins[] = { 0x8a, };
static u8 jz4760_uart3_data_funcs[] = { 0, 1, };
static u8 jz4760_mmc0_1bit_a_funcs[] = { 1, 1, 0, };
@@ -436,8 +446,12 @@
INGENIC_PIN_GROUP("i2c0-data", jz4760_i2c0, 0),
INGENIC_PIN_GROUP("i2c1-data", jz4760_i2c1, 0),
INGENIC_PIN_GROUP("cim-data", jz4760_cim, 0),
+ INGENIC_PIN_GROUP("lcd-8bit", jz4760_lcd_8bit, 0),
+ INGENIC_PIN_GROUP("lcd-16bit", jz4760_lcd_16bit, 0),
+ INGENIC_PIN_GROUP("lcd-18bit", jz4760_lcd_18bit, 0),
INGENIC_PIN_GROUP("lcd-24bit", jz4760_lcd_24bit, 0),
- { "lcd-no-pins", },
+ INGENIC_PIN_GROUP("lcd-generic", jz4760_lcd_generic, 0),
+ INGENIC_PIN_GROUP("lcd-special", jz4760_lcd_special, 1),
INGENIC_PIN_GROUP("pwm0", jz4760_pwm_pwm0, 0),
INGENIC_PIN_GROUP("pwm1", jz4760_pwm_pwm1, 0),
INGENIC_PIN_GROUP("pwm2", jz4760_pwm_pwm2, 0),
@@ -446,6 +460,7 @@
INGENIC_PIN_GROUP("pwm5", jz4760_pwm_pwm5, 0),
INGENIC_PIN_GROUP("pwm6", jz4760_pwm_pwm6, 0),
INGENIC_PIN_GROUP("pwm7", jz4760_pwm_pwm7, 0),
+ INGENIC_PIN_GROUP("otg-vbus", jz4760_otg, 0),
};
static const char *jz4760_uart0_groups[] = { "uart0-data", "uart0-hwflow", };
@@ -477,7 +492,10 @@
static const char *jz4760_i2c0_groups[] = { "i2c0-data", };
static const char *jz4760_i2c1_groups[] = { "i2c1-data", };
static const char *jz4760_cim_groups[] = { "cim-data", };
-static const char *jz4760_lcd_groups[] = { "lcd-24bit", "lcd-no-pins", };
+static const char *jz4760_lcd_groups[] = {
+ "lcd-8bit", "lcd-16bit", "lcd-18bit", "lcd-24bit",
+ "lcd-special", "lcd-generic",
+};
static const char *jz4760_pwm0_groups[] = { "pwm0", };
static const char *jz4760_pwm1_groups[] = { "pwm1", };
static const char *jz4760_pwm2_groups[] = { "pwm2", };
@@ -486,6 +504,7 @@
static const char *jz4760_pwm5_groups[] = { "pwm5", };
static const char *jz4760_pwm6_groups[] = { "pwm6", };
static const char *jz4760_pwm7_groups[] = { "pwm7", };
+static const char *jz4760_otg_groups[] = { "otg-vbus", };
static const struct function_desc jz4760_functions[] = {
{ "uart0", jz4760_uart0_groups, ARRAY_SIZE(jz4760_uart0_groups), },
@@ -514,6 +533,7 @@
{ "pwm5", jz4760_pwm5_groups, ARRAY_SIZE(jz4760_pwm5_groups), },
{ "pwm6", jz4760_pwm6_groups, ARRAY_SIZE(jz4760_pwm6_groups), },
{ "pwm7", jz4760_pwm7_groups, ARRAY_SIZE(jz4760_pwm7_groups), },
+ { "otg", jz4760_otg_groups, ARRAY_SIZE(jz4760_otg_groups), },
};
static const struct ingenic_chip_info jz4760_chip_info = {
@@ -648,7 +668,6 @@
0xa9, 0xab, 0xaa, 0xac, 0xa5, 0xa4, 0xad, 0xae, 0xa6, 0xa8,
};
static int jz4770_mac_mii_pins[] = { 0xa7, 0xaf, };
-static int jz4770_otg_pins[] = { 0x8a, };
static const struct group_desc jz4770_groups[] = {
INGENIC_PIN_GROUP("uart0-data", jz4770_uart0_data, 0),
@@ -747,7 +766,7 @@
INGENIC_PIN_GROUP("pwm7", jz4770_pwm_pwm7, 0),
INGENIC_PIN_GROUP("mac-rmii", jz4770_mac_rmii, 0),
INGENIC_PIN_GROUP("mac-mii", jz4770_mac_mii, 0),
- INGENIC_PIN_GROUP("otg-vbus", jz4770_otg, 0),
+ INGENIC_PIN_GROUP("otg-vbus", jz4760_otg, 0),
};
static const char *jz4770_uart0_groups[] = { "uart0-data", "uart0-hwflow", };
@@ -808,7 +827,6 @@
static const char *jz4770_pwm6_groups[] = { "pwm6", };
static const char *jz4770_pwm7_groups[] = { "pwm7", };
static const char *jz4770_mac_groups[] = { "mac-rmii", "mac-mii", };
-static const char *jz4770_otg_groups[] = { "otg-vbus", };
static const struct function_desc jz4770_functions[] = {
{ "uart0", jz4770_uart0_groups, ARRAY_SIZE(jz4770_uart0_groups), },
@@ -841,7 +859,7 @@
{ "pwm6", jz4770_pwm6_groups, ARRAY_SIZE(jz4770_pwm6_groups), },
{ "pwm7", jz4770_pwm7_groups, ARRAY_SIZE(jz4770_pwm7_groups), },
{ "mac", jz4770_mac_groups, ARRAY_SIZE(jz4770_mac_groups), },
- { "otg", jz4770_otg_groups, ARRAY_SIZE(jz4770_otg_groups), },
+ { "otg", jz4760_otg_groups, ARRAY_SIZE(jz4760_otg_groups), },
};
static const struct ingenic_chip_info jz4770_chip_info = {
@@ -2384,6 +2402,12 @@
unsigned int i;
int err;
+ chip_info = of_device_get_match_data(dev);
+ if (!chip_info) {
+ dev_err(dev, "Unsupported SoC\n");
+ return -EINVAL;
+ }
+
jzpc = devm_kzalloc(dev, sizeof(*jzpc), GFP_KERNEL);
if (!jzpc)
return -ENOMEM;
@@ -2400,7 +2424,7 @@
}
jzpc->dev = dev;
- jzpc->info = chip_info = of_device_get_match_data(dev);
+ jzpc->info = chip_info;
pctl_desc = devm_kzalloc(&pdev->dev, sizeof(*pctl_desc), GFP_KERNEL);
if (!pctl_desc)
@@ -2470,17 +2494,47 @@
}
static const struct of_device_id ingenic_pinctrl_of_match[] = {
- { .compatible = "ingenic,jz4740-pinctrl", .data = &jz4740_chip_info },
- { .compatible = "ingenic,jz4725b-pinctrl", .data = &jz4725b_chip_info },
- { .compatible = "ingenic,jz4760-pinctrl", .data = &jz4760_chip_info },
- { .compatible = "ingenic,jz4760b-pinctrl", .data = &jz4760_chip_info },
- { .compatible = "ingenic,jz4770-pinctrl", .data = &jz4770_chip_info },
- { .compatible = "ingenic,jz4780-pinctrl", .data = &jz4780_chip_info },
- { .compatible = "ingenic,x1000-pinctrl", .data = &x1000_chip_info },
- { .compatible = "ingenic,x1000e-pinctrl", .data = &x1000_chip_info },
- { .compatible = "ingenic,x1500-pinctrl", .data = &x1500_chip_info },
- { .compatible = "ingenic,x1830-pinctrl", .data = &x1830_chip_info },
- {},
+ {
+ .compatible = "ingenic,jz4740-pinctrl",
+ .data = IF_ENABLED(CONFIG_MACH_JZ4740, &jz4740_chip_info)
+ },
+ {
+ .compatible = "ingenic,jz4725b-pinctrl",
+ .data = IF_ENABLED(CONFIG_MACH_JZ4725B, &jz4725b_chip_info)
+ },
+ {
+ .compatible = "ingenic,jz4760-pinctrl",
+ .data = IF_ENABLED(CONFIG_MACH_JZ4760, &jz4760_chip_info)
+ },
+ {
+ .compatible = "ingenic,jz4760b-pinctrl",
+ .data = IF_ENABLED(CONFIG_MACH_JZ4760, &jz4760_chip_info)
+ },
+ {
+ .compatible = "ingenic,jz4770-pinctrl",
+ .data = IF_ENABLED(CONFIG_MACH_JZ4770, &jz4770_chip_info)
+ },
+ {
+ .compatible = "ingenic,jz4780-pinctrl",
+ .data = IF_ENABLED(CONFIG_MACH_JZ4780, &jz4780_chip_info)
+ },
+ {
+ .compatible = "ingenic,x1000-pinctrl",
+ .data = IF_ENABLED(CONFIG_MACH_X1000, &x1000_chip_info)
+ },
+ {
+ .compatible = "ingenic,x1000e-pinctrl",
+ .data = IF_ENABLED(CONFIG_MACH_X1000, &x1000_chip_info)
+ },
+ {
+ .compatible = "ingenic,x1500-pinctrl",
+ .data = IF_ENABLED(CONFIG_MACH_X1500, &x1500_chip_info)
+ },
+ {
+ .compatible = "ingenic,x1830-pinctrl",
+ .data = IF_ENABLED(CONFIG_MACH_X1830, &x1830_chip_info)
+ },
+ { /* sentinel */ },
};
static struct platform_driver ingenic_pinctrl_driver = {
diff --git a/drivers/pinctrl/pinctrl-single.c b/drivers/pinctrl/pinctrl-single.c
index f3cd7e2..7771316 100644
--- a/drivers/pinctrl/pinctrl-single.c
+++ b/drivers/pinctrl/pinctrl-single.c
@@ -777,6 +777,7 @@
function->vals = vals;
function->nvals = nvals;
+ function->name = name;
selector = pinmux_generic_add_function(pcs->pctl, name,
pgnames, npgnames,
diff --git a/drivers/pinctrl/pinctrl-st.c b/drivers/pinctrl/pinctrl-st.c
index 7b8c7a0..43d9e6c 100644
--- a/drivers/pinctrl/pinctrl-st.c
+++ b/drivers/pinctrl/pinctrl-st.c
@@ -541,7 +541,6 @@
st_regmap_field_bit_set_clear_pin(rt_p->delay_0, delay & 0x1, pin);
/* 2 bit delay, msb */
st_regmap_field_bit_set_clear_pin(rt_p->delay_1, delay & 0x2, pin);
-
}
static void st_pinconf_set_retime_dedicated(struct st_pinctrl *info,
diff --git a/drivers/pinctrl/pinctrl-sx150x.c b/drivers/pinctrl/pinctrl-sx150x.c
index c110f78..484a3b9 100644
--- a/drivers/pinctrl/pinctrl-sx150x.c
+++ b/drivers/pinctrl/pinctrl-sx150x.c
@@ -443,7 +443,6 @@
sx150x_gpio_oscio_set(pctl, value);
else
__sx150x_gpio_set(pctl, offset, value);
-
}
static void sx150x_gpio_set_multiple(struct gpio_chip *chip,
diff --git a/drivers/pinctrl/pinctrl-u300.c b/drivers/pinctrl/pinctrl-u300.c
deleted file mode 100644
index cc30644..0000000
--- a/drivers/pinctrl/pinctrl-u300.c
+++ /dev/null
@@ -1,1111 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Driver for the U300 pin controller
- *
- * Based on the original U300 padmux functions
- * Copyright (C) 2009-2011 ST-Ericsson AB
- * Author: Martin Persson <martin.persson@stericsson.com>
- * Author: Linus Walleij <linus.walleij@linaro.org>
- *
- * The DB3350 design and control registers are oriented around pads rather than
- * pins, so we enumerate the pads we can mux rather than actual pins. The pads
- * are connected to different pins in different packaging types, so it would
- * be confusing.
- */
-#include <linux/init.h>
-#include <linux/module.h>
-#include <linux/mod_devicetable.h>
-#include <linux/platform_device.h>
-#include <linux/io.h>
-#include <linux/slab.h>
-#include <linux/err.h>
-#include <linux/pinctrl/pinctrl.h>
-#include <linux/pinctrl/pinmux.h>
-#include <linux/pinctrl/pinconf.h>
-#include <linux/pinctrl/pinconf-generic.h>
-#include "pinctrl-coh901.h"
-
-/*
- * Register definitions for the U300 Padmux control registers in the
- * system controller
- */
-
-/* PAD MUX Control register 1 (LOW) 16bit (R/W) */
-#define U300_SYSCON_PMC1LR 0x007C
-#define U300_SYSCON_PMC1LR_MASK 0xFFFF
-#define U300_SYSCON_PMC1LR_CDI_MASK 0xC000
-#define U300_SYSCON_PMC1LR_CDI_CDI 0x0000
-#define U300_SYSCON_PMC1LR_CDI_EMIF 0x4000
-/* For BS335 */
-#define U300_SYSCON_PMC1LR_CDI_CDI2 0x8000
-#define U300_SYSCON_PMC1LR_CDI_WCDMA_APP_GPIO 0xC000
-/* For BS365 */
-#define U300_SYSCON_PMC1LR_CDI_GPIO 0x8000
-#define U300_SYSCON_PMC1LR_CDI_WCDMA 0xC000
-/* Common defs */
-#define U300_SYSCON_PMC1LR_PDI_MASK 0x3000
-#define U300_SYSCON_PMC1LR_PDI_PDI 0x0000
-#define U300_SYSCON_PMC1LR_PDI_EGG 0x1000
-#define U300_SYSCON_PMC1LR_PDI_WCDMA 0x3000
-#define U300_SYSCON_PMC1LR_MMCSD_MASK 0x0C00
-#define U300_SYSCON_PMC1LR_MMCSD_MMCSD 0x0000
-#define U300_SYSCON_PMC1LR_MMCSD_MSPRO 0x0400
-#define U300_SYSCON_PMC1LR_MMCSD_DSP 0x0800
-#define U300_SYSCON_PMC1LR_MMCSD_WCDMA 0x0C00
-#define U300_SYSCON_PMC1LR_ETM_MASK 0x0300
-#define U300_SYSCON_PMC1LR_ETM_ACC 0x0000
-#define U300_SYSCON_PMC1LR_ETM_APP 0x0100
-#define U300_SYSCON_PMC1LR_EMIF_1_CS2_MASK 0x00C0
-#define U300_SYSCON_PMC1LR_EMIF_1_CS2_STATIC 0x0000
-#define U300_SYSCON_PMC1LR_EMIF_1_CS2_NFIF 0x0040
-#define U300_SYSCON_PMC1LR_EMIF_1_CS2_SDRAM 0x0080
-#define U300_SYSCON_PMC1LR_EMIF_1_CS2_STATIC_2GB 0x00C0
-#define U300_SYSCON_PMC1LR_EMIF_1_CS1_MASK 0x0030
-#define U300_SYSCON_PMC1LR_EMIF_1_CS1_STATIC 0x0000
-#define U300_SYSCON_PMC1LR_EMIF_1_CS1_NFIF 0x0010
-#define U300_SYSCON_PMC1LR_EMIF_1_CS1_SDRAM 0x0020
-#define U300_SYSCON_PMC1LR_EMIF_1_CS1_SEMI 0x0030
-#define U300_SYSCON_PMC1LR_EMIF_1_CS0_MASK 0x000C
-#define U300_SYSCON_PMC1LR_EMIF_1_CS0_STATIC 0x0000
-#define U300_SYSCON_PMC1LR_EMIF_1_CS0_NFIF 0x0004
-#define U300_SYSCON_PMC1LR_EMIF_1_CS0_SDRAM 0x0008
-#define U300_SYSCON_PMC1LR_EMIF_1_CS0_SEMI 0x000C
-#define U300_SYSCON_PMC1LR_EMIF_1_MASK 0x0003
-#define U300_SYSCON_PMC1LR_EMIF_1_STATIC 0x0000
-#define U300_SYSCON_PMC1LR_EMIF_1_SDRAM0 0x0001
-#define U300_SYSCON_PMC1LR_EMIF_1_SDRAM1 0x0002
-#define U300_SYSCON_PMC1LR_EMIF_1 0x0003
-/* PAD MUX Control register 2 (HIGH) 16bit (R/W) */
-#define U300_SYSCON_PMC1HR 0x007E
-#define U300_SYSCON_PMC1HR_MASK 0xFFFF
-#define U300_SYSCON_PMC1HR_MISC_2_MASK 0xC000
-#define U300_SYSCON_PMC1HR_MISC_2_APP_GPIO 0x0000
-#define U300_SYSCON_PMC1HR_MISC_2_MSPRO 0x4000
-#define U300_SYSCON_PMC1HR_MISC_2_DSP 0x8000
-#define U300_SYSCON_PMC1HR_MISC_2_AAIF 0xC000
-#define U300_SYSCON_PMC1HR_APP_GPIO_2_MASK 0x3000
-#define U300_SYSCON_PMC1HR_APP_GPIO_2_APP_GPIO 0x0000
-#define U300_SYSCON_PMC1HR_APP_GPIO_2_NFIF 0x1000
-#define U300_SYSCON_PMC1HR_APP_GPIO_2_DSP 0x2000
-#define U300_SYSCON_PMC1HR_APP_GPIO_2_AAIF 0x3000
-#define U300_SYSCON_PMC1HR_APP_GPIO_1_MASK 0x0C00
-#define U300_SYSCON_PMC1HR_APP_GPIO_1_APP_GPIO 0x0000
-#define U300_SYSCON_PMC1HR_APP_GPIO_1_MMC 0x0400
-#define U300_SYSCON_PMC1HR_APP_GPIO_1_DSP 0x0800
-#define U300_SYSCON_PMC1HR_APP_GPIO_1_AAIF 0x0C00
-#define U300_SYSCON_PMC1HR_APP_SPI_CS_2_MASK 0x0300
-#define U300_SYSCON_PMC1HR_APP_SPI_CS_2_APP_GPIO 0x0000
-#define U300_SYSCON_PMC1HR_APP_SPI_CS_2_SPI 0x0100
-#define U300_SYSCON_PMC1HR_APP_SPI_CS_2_AAIF 0x0300
-#define U300_SYSCON_PMC1HR_APP_SPI_CS_1_MASK 0x00C0
-#define U300_SYSCON_PMC1HR_APP_SPI_CS_1_APP_GPIO 0x0000
-#define U300_SYSCON_PMC1HR_APP_SPI_CS_1_SPI 0x0040
-#define U300_SYSCON_PMC1HR_APP_SPI_CS_1_AAIF 0x00C0
-#define U300_SYSCON_PMC1HR_APP_SPI_2_MASK 0x0030
-#define U300_SYSCON_PMC1HR_APP_SPI_2_APP_GPIO 0x0000
-#define U300_SYSCON_PMC1HR_APP_SPI_2_SPI 0x0010
-#define U300_SYSCON_PMC1HR_APP_SPI_2_DSP 0x0020
-#define U300_SYSCON_PMC1HR_APP_SPI_2_AAIF 0x0030
-#define U300_SYSCON_PMC1HR_APP_UART0_2_MASK 0x000C
-#define U300_SYSCON_PMC1HR_APP_UART0_2_APP_GPIO 0x0000
-#define U300_SYSCON_PMC1HR_APP_UART0_2_UART0 0x0004
-#define U300_SYSCON_PMC1HR_APP_UART0_2_NFIF_CS 0x0008
-#define U300_SYSCON_PMC1HR_APP_UART0_2_AAIF 0x000C
-#define U300_SYSCON_PMC1HR_APP_UART0_1_MASK 0x0003
-#define U300_SYSCON_PMC1HR_APP_UART0_1_APP_GPIO 0x0000
-#define U300_SYSCON_PMC1HR_APP_UART0_1_UART0 0x0001
-#define U300_SYSCON_PMC1HR_APP_UART0_1_AAIF 0x0003
-/* Padmux 2 control */
-#define U300_SYSCON_PMC2R 0x100
-#define U300_SYSCON_PMC2R_APP_MISC_0_MASK 0x00C0
-#define U300_SYSCON_PMC2R_APP_MISC_0_APP_GPIO 0x0000
-#define U300_SYSCON_PMC2R_APP_MISC_0_EMIF_SDRAM 0x0040
-#define U300_SYSCON_PMC2R_APP_MISC_0_MMC 0x0080
-#define U300_SYSCON_PMC2R_APP_MISC_0_CDI2 0x00C0
-#define U300_SYSCON_PMC2R_APP_MISC_1_MASK 0x0300
-#define U300_SYSCON_PMC2R_APP_MISC_1_APP_GPIO 0x0000
-#define U300_SYSCON_PMC2R_APP_MISC_1_EMIF_SDRAM 0x0100
-#define U300_SYSCON_PMC2R_APP_MISC_1_MMC 0x0200
-#define U300_SYSCON_PMC2R_APP_MISC_1_CDI2 0x0300
-#define U300_SYSCON_PMC2R_APP_MISC_2_MASK 0x0C00
-#define U300_SYSCON_PMC2R_APP_MISC_2_APP_GPIO 0x0000
-#define U300_SYSCON_PMC2R_APP_MISC_2_EMIF_SDRAM 0x0400
-#define U300_SYSCON_PMC2R_APP_MISC_2_MMC 0x0800
-#define U300_SYSCON_PMC2R_APP_MISC_2_CDI2 0x0C00
-#define U300_SYSCON_PMC2R_APP_MISC_3_MASK 0x3000
-#define U300_SYSCON_PMC2R_APP_MISC_3_APP_GPIO 0x0000
-#define U300_SYSCON_PMC2R_APP_MISC_3_EMIF_SDRAM 0x1000
-#define U300_SYSCON_PMC2R_APP_MISC_3_MMC 0x2000
-#define U300_SYSCON_PMC2R_APP_MISC_3_CDI2 0x3000
-#define U300_SYSCON_PMC2R_APP_MISC_4_MASK 0xC000
-#define U300_SYSCON_PMC2R_APP_MISC_4_APP_GPIO 0x0000
-#define U300_SYSCON_PMC2R_APP_MISC_4_EMIF_SDRAM 0x4000
-#define U300_SYSCON_PMC2R_APP_MISC_4_MMC 0x8000
-#define U300_SYSCON_PMC2R_APP_MISC_4_ACC_GPIO 0xC000
-/* TODO: More SYSCON registers missing */
-#define U300_SYSCON_PMC3R 0x10C
-#define U300_SYSCON_PMC3R_APP_MISC_11_MASK 0xC000
-#define U300_SYSCON_PMC3R_APP_MISC_11_SPI 0x4000
-#define U300_SYSCON_PMC3R_APP_MISC_10_MASK 0x3000
-#define U300_SYSCON_PMC3R_APP_MISC_10_SPI 0x1000
-/* TODO: Missing other configs */
-#define U300_SYSCON_PMC4R 0x168
-#define U300_SYSCON_PMC4R_APP_MISC_12_MASK 0x0003
-#define U300_SYSCON_PMC4R_APP_MISC_12_APP_GPIO 0x0000
-#define U300_SYSCON_PMC4R_APP_MISC_13_MASK 0x000C
-#define U300_SYSCON_PMC4R_APP_MISC_13_CDI 0x0000
-#define U300_SYSCON_PMC4R_APP_MISC_13_SMIA 0x0004
-#define U300_SYSCON_PMC4R_APP_MISC_13_SMIA2 0x0008
-#define U300_SYSCON_PMC4R_APP_MISC_13_APP_GPIO 0x000C
-#define U300_SYSCON_PMC4R_APP_MISC_14_MASK 0x0030
-#define U300_SYSCON_PMC4R_APP_MISC_14_CDI 0x0000
-#define U300_SYSCON_PMC4R_APP_MISC_14_SMIA 0x0010
-#define U300_SYSCON_PMC4R_APP_MISC_14_CDI2 0x0020
-#define U300_SYSCON_PMC4R_APP_MISC_14_APP_GPIO 0x0030
-#define U300_SYSCON_PMC4R_APP_MISC_16_MASK 0x0300
-#define U300_SYSCON_PMC4R_APP_MISC_16_APP_GPIO_13 0x0000
-#define U300_SYSCON_PMC4R_APP_MISC_16_APP_UART1_CTS 0x0100
-#define U300_SYSCON_PMC4R_APP_MISC_16_EMIF_1_STATIC_CS5_N 0x0200
-
-#define DRIVER_NAME "pinctrl-u300"
-
-/*
- * The DB3350 has 467 pads, I have enumerated the pads clockwise around the
- * edges of the silicon, finger by finger. LTCORNER upper left is pad 0.
- * Data taken from the PadRing chart, arranged like this:
- *
- * 0 ..... 104
- * 466 105
- * . .
- * . .
- * 358 224
- * 357 .... 225
- */
-#define U300_NUM_PADS 467
-
-/* Pad names for the pinmux subsystem */
-static const struct pinctrl_pin_desc u300_pads[] = {
- /* Pads along the top edge of the chip */
- PINCTRL_PIN(0, "P PAD VDD 28"),
- PINCTRL_PIN(1, "P PAD GND 28"),
- PINCTRL_PIN(2, "PO SIM RST N"),
- PINCTRL_PIN(3, "VSSIO 25"),
- PINCTRL_PIN(4, "VSSA ADDA ESDSUB"),
- PINCTRL_PIN(5, "PWR VSSCOMMON"),
- PINCTRL_PIN(6, "PI ADC I1 POS"),
- PINCTRL_PIN(7, "PI ADC I1 NEG"),
- PINCTRL_PIN(8, "PWR VSSAD0"),
- PINCTRL_PIN(9, "PWR VCCAD0"),
- PINCTRL_PIN(10, "PI ADC Q1 NEG"),
- PINCTRL_PIN(11, "PI ADC Q1 POS"),
- PINCTRL_PIN(12, "PWR VDDAD"),
- PINCTRL_PIN(13, "PWR GNDAD"),
- PINCTRL_PIN(14, "PI ADC I2 POS"),
- PINCTRL_PIN(15, "PI ADC I2 NEG"),
- PINCTRL_PIN(16, "PWR VSSAD1"),
- PINCTRL_PIN(17, "PWR VCCAD1"),
- PINCTRL_PIN(18, "PI ADC Q2 NEG"),
- PINCTRL_PIN(19, "PI ADC Q2 POS"),
- PINCTRL_PIN(20, "VSSA ADDA ESDSUB"),
- PINCTRL_PIN(21, "PWR VCCGPAD"),
- PINCTRL_PIN(22, "PI TX POW"),
- PINCTRL_PIN(23, "PWR VSSGPAD"),
- PINCTRL_PIN(24, "PO DAC I POS"),
- PINCTRL_PIN(25, "PO DAC I NEG"),
- PINCTRL_PIN(26, "PO DAC Q POS"),
- PINCTRL_PIN(27, "PO DAC Q NEG"),
- PINCTRL_PIN(28, "PWR VSSDA"),
- PINCTRL_PIN(29, "PWR VCCDA"),
- PINCTRL_PIN(30, "VSSA ADDA ESDSUB"),
- PINCTRL_PIN(31, "P PAD VDDIO 11"),
- PINCTRL_PIN(32, "PI PLL 26 FILTVDD"),
- PINCTRL_PIN(33, "PI PLL 26 VCONT"),
- PINCTRL_PIN(34, "PWR AGNDPLL2V5 32 13"),
- PINCTRL_PIN(35, "PWR AVDDPLL2V5 32 13"),
- PINCTRL_PIN(36, "VDDA PLL ESD"),
- PINCTRL_PIN(37, "VSSA PLL ESD"),
- PINCTRL_PIN(38, "VSS PLL"),
- PINCTRL_PIN(39, "VDDC PLL"),
- PINCTRL_PIN(40, "PWR AGNDPLL2V5 26 60"),
- PINCTRL_PIN(41, "PWR AVDDPLL2V5 26 60"),
- PINCTRL_PIN(42, "PWR AVDDPLL2V5 26 208"),
- PINCTRL_PIN(43, "PWR AGNDPLL2V5 26 208"),
- PINCTRL_PIN(44, "PWR AVDDPLL2V5 13 208"),
- PINCTRL_PIN(45, "PWR AGNDPLL2V5 13 208"),
- PINCTRL_PIN(46, "P PAD VSSIO 11"),
- PINCTRL_PIN(47, "P PAD VSSIO 12"),
- PINCTRL_PIN(48, "PI POW RST N"),
- PINCTRL_PIN(49, "VDDC IO"),
- PINCTRL_PIN(50, "P PAD VDDIO 16"),
- PINCTRL_PIN(51, "PO RF WCDMA EN 4"),
- PINCTRL_PIN(52, "PO RF WCDMA EN 3"),
- PINCTRL_PIN(53, "PO RF WCDMA EN 2"),
- PINCTRL_PIN(54, "PO RF WCDMA EN 1"),
- PINCTRL_PIN(55, "PO RF WCDMA EN 0"),
- PINCTRL_PIN(56, "PO GSM PA ENABLE"),
- PINCTRL_PIN(57, "PO RF DATA STRB"),
- PINCTRL_PIN(58, "PO RF DATA2"),
- PINCTRL_PIN(59, "PIO RF DATA1"),
- PINCTRL_PIN(60, "PIO RF DATA0"),
- PINCTRL_PIN(61, "P PAD VDD 11"),
- PINCTRL_PIN(62, "P PAD GND 11"),
- PINCTRL_PIN(63, "P PAD VSSIO 16"),
- PINCTRL_PIN(64, "P PAD VDDIO 18"),
- PINCTRL_PIN(65, "PO RF CTRL STRB2"),
- PINCTRL_PIN(66, "PO RF CTRL STRB1"),
- PINCTRL_PIN(67, "PO RF CTRL STRB0"),
- PINCTRL_PIN(68, "PIO RF CTRL DATA"),
- PINCTRL_PIN(69, "PO RF CTRL CLK"),
- PINCTRL_PIN(70, "PO TX ADC STRB"),
- PINCTRL_PIN(71, "PO ANT SW 2"),
- PINCTRL_PIN(72, "PO ANT SW 3"),
- PINCTRL_PIN(73, "PO ANT SW 0"),
- PINCTRL_PIN(74, "PO ANT SW 1"),
- PINCTRL_PIN(75, "PO M CLKRQ"),
- PINCTRL_PIN(76, "PI M CLK"),
- PINCTRL_PIN(77, "PI RTC CLK"),
- PINCTRL_PIN(78, "P PAD VDD 8"),
- PINCTRL_PIN(79, "P PAD GND 8"),
- PINCTRL_PIN(80, "P PAD VSSIO 13"),
- PINCTRL_PIN(81, "P PAD VDDIO 13"),
- PINCTRL_PIN(82, "PO SYS 1 CLK"),
- PINCTRL_PIN(83, "PO SYS 2 CLK"),
- PINCTRL_PIN(84, "PO SYS 0 CLK"),
- PINCTRL_PIN(85, "PI SYS 0 CLKRQ"),
- PINCTRL_PIN(86, "PO PWR MNGT CTRL 1"),
- PINCTRL_PIN(87, "PO PWR MNGT CTRL 0"),
- PINCTRL_PIN(88, "PO RESOUT2 RST N"),
- PINCTRL_PIN(89, "PO RESOUT1 RST N"),
- PINCTRL_PIN(90, "PO RESOUT0 RST N"),
- PINCTRL_PIN(91, "PI SERVICE N"),
- PINCTRL_PIN(92, "P PAD VDD 29"),
- PINCTRL_PIN(93, "P PAD GND 29"),
- PINCTRL_PIN(94, "P PAD VSSIO 8"),
- PINCTRL_PIN(95, "P PAD VDDIO 8"),
- PINCTRL_PIN(96, "PI EXT IRQ1 N"),
- PINCTRL_PIN(97, "PI EXT IRQ0 N"),
- PINCTRL_PIN(98, "PIO DC ON"),
- PINCTRL_PIN(99, "PIO ACC APP I2C DATA"),
- PINCTRL_PIN(100, "PIO ACC APP I2C CLK"),
- PINCTRL_PIN(101, "P PAD VDD 12"),
- PINCTRL_PIN(102, "P PAD GND 12"),
- PINCTRL_PIN(103, "P PAD VSSIO 14"),
- PINCTRL_PIN(104, "P PAD VDDIO 14"),
- /* Pads along the right edge of the chip */
- PINCTRL_PIN(105, "PIO APP I2C1 DATA"),
- PINCTRL_PIN(106, "PIO APP I2C1 CLK"),
- PINCTRL_PIN(107, "PO KEY OUT0"),
- PINCTRL_PIN(108, "PO KEY OUT1"),
- PINCTRL_PIN(109, "PO KEY OUT2"),
- PINCTRL_PIN(110, "PO KEY OUT3"),
- PINCTRL_PIN(111, "PO KEY OUT4"),
- PINCTRL_PIN(112, "PI KEY IN0"),
- PINCTRL_PIN(113, "PI KEY IN1"),
- PINCTRL_PIN(114, "PI KEY IN2"),
- PINCTRL_PIN(115, "P PAD VDDIO 15"),
- PINCTRL_PIN(116, "P PAD VSSIO 15"),
- PINCTRL_PIN(117, "P PAD GND 13"),
- PINCTRL_PIN(118, "P PAD VDD 13"),
- PINCTRL_PIN(119, "PI KEY IN3"),
- PINCTRL_PIN(120, "PI KEY IN4"),
- PINCTRL_PIN(121, "PI KEY IN5"),
- PINCTRL_PIN(122, "PIO APP PCM I2S1 DATA B"),
- PINCTRL_PIN(123, "PIO APP PCM I2S1 DATA A"),
- PINCTRL_PIN(124, "PIO APP PCM I2S1 WS"),
- PINCTRL_PIN(125, "PIO APP PCM I2S1 CLK"),
- PINCTRL_PIN(126, "PIO APP PCM I2S0 DATA B"),
- PINCTRL_PIN(127, "PIO APP PCM I2S0 DATA A"),
- PINCTRL_PIN(128, "PIO APP PCM I2S0 WS"),
- PINCTRL_PIN(129, "PIO APP PCM I2S0 CLK"),
- PINCTRL_PIN(130, "P PAD VDD 17"),
- PINCTRL_PIN(131, "P PAD GND 17"),
- PINCTRL_PIN(132, "P PAD VSSIO 19"),
- PINCTRL_PIN(133, "P PAD VDDIO 19"),
- PINCTRL_PIN(134, "UART0 RTS"),
- PINCTRL_PIN(135, "UART0 CTS"),
- PINCTRL_PIN(136, "UART0 TX"),
- PINCTRL_PIN(137, "UART0 RX"),
- PINCTRL_PIN(138, "PIO ACC SPI DO"),
- PINCTRL_PIN(139, "PIO ACC SPI DI"),
- PINCTRL_PIN(140, "PIO ACC SPI CS0 N"),
- PINCTRL_PIN(141, "PIO ACC SPI CS1 N"),
- PINCTRL_PIN(142, "PIO ACC SPI CS2 N"),
- PINCTRL_PIN(143, "PIO ACC SPI CLK"),
- PINCTRL_PIN(144, "PO PDI EXT RST N"),
- PINCTRL_PIN(145, "P PAD VDDIO 22"),
- PINCTRL_PIN(146, "P PAD VSSIO 22"),
- PINCTRL_PIN(147, "P PAD GND 18"),
- PINCTRL_PIN(148, "P PAD VDD 18"),
- PINCTRL_PIN(149, "PIO PDI C0"),
- PINCTRL_PIN(150, "PIO PDI C1"),
- PINCTRL_PIN(151, "PIO PDI C2"),
- PINCTRL_PIN(152, "PIO PDI C3"),
- PINCTRL_PIN(153, "PIO PDI C4"),
- PINCTRL_PIN(154, "PIO PDI C5"),
- PINCTRL_PIN(155, "PIO PDI D0"),
- PINCTRL_PIN(156, "PIO PDI D1"),
- PINCTRL_PIN(157, "PIO PDI D2"),
- PINCTRL_PIN(158, "PIO PDI D3"),
- PINCTRL_PIN(159, "P PAD VDDIO 21"),
- PINCTRL_PIN(160, "P PAD VSSIO 21"),
- PINCTRL_PIN(161, "PIO PDI D4"),
- PINCTRL_PIN(162, "PIO PDI D5"),
- PINCTRL_PIN(163, "PIO PDI D6"),
- PINCTRL_PIN(164, "PIO PDI D7"),
- PINCTRL_PIN(165, "PIO MS INS"),
- PINCTRL_PIN(166, "MMC DATA DIR LS"),
- PINCTRL_PIN(167, "MMC DATA 3"),
- PINCTRL_PIN(168, "MMC DATA 2"),
- PINCTRL_PIN(169, "MMC DATA 1"),
- PINCTRL_PIN(170, "MMC DATA 0"),
- PINCTRL_PIN(171, "MMC CMD DIR LS"),
- PINCTRL_PIN(172, "P PAD VDD 27"),
- PINCTRL_PIN(173, "P PAD GND 27"),
- PINCTRL_PIN(174, "P PAD VSSIO 20"),
- PINCTRL_PIN(175, "P PAD VDDIO 20"),
- PINCTRL_PIN(176, "MMC CMD"),
- PINCTRL_PIN(177, "MMC CLK"),
- PINCTRL_PIN(178, "PIO APP GPIO 14"),
- PINCTRL_PIN(179, "PIO APP GPIO 13"),
- PINCTRL_PIN(180, "PIO APP GPIO 11"),
- PINCTRL_PIN(181, "PIO APP GPIO 25"),
- PINCTRL_PIN(182, "PIO APP GPIO 24"),
- PINCTRL_PIN(183, "PIO APP GPIO 23"),
- PINCTRL_PIN(184, "PIO APP GPIO 22"),
- PINCTRL_PIN(185, "PIO APP GPIO 21"),
- PINCTRL_PIN(186, "PIO APP GPIO 20"),
- PINCTRL_PIN(187, "P PAD VDD 19"),
- PINCTRL_PIN(188, "P PAD GND 19"),
- PINCTRL_PIN(189, "P PAD VSSIO 23"),
- PINCTRL_PIN(190, "P PAD VDDIO 23"),
- PINCTRL_PIN(191, "PIO APP GPIO 19"),
- PINCTRL_PIN(192, "PIO APP GPIO 18"),
- PINCTRL_PIN(193, "PIO APP GPIO 17"),
- PINCTRL_PIN(194, "PIO APP GPIO 16"),
- PINCTRL_PIN(195, "PI CI D1"),
- PINCTRL_PIN(196, "PI CI D0"),
- PINCTRL_PIN(197, "PI CI HSYNC"),
- PINCTRL_PIN(198, "PI CI VSYNC"),
- PINCTRL_PIN(199, "PI CI EXT CLK"),
- PINCTRL_PIN(200, "PO CI EXT RST N"),
- PINCTRL_PIN(201, "P PAD VSSIO 43"),
- PINCTRL_PIN(202, "P PAD VDDIO 43"),
- PINCTRL_PIN(203, "PI CI D6"),
- PINCTRL_PIN(204, "PI CI D7"),
- PINCTRL_PIN(205, "PI CI D2"),
- PINCTRL_PIN(206, "PI CI D3"),
- PINCTRL_PIN(207, "PI CI D4"),
- PINCTRL_PIN(208, "PI CI D5"),
- PINCTRL_PIN(209, "PI CI D8"),
- PINCTRL_PIN(210, "PI CI D9"),
- PINCTRL_PIN(211, "P PAD VDD 20"),
- PINCTRL_PIN(212, "P PAD GND 20"),
- PINCTRL_PIN(213, "P PAD VSSIO 24"),
- PINCTRL_PIN(214, "P PAD VDDIO 24"),
- PINCTRL_PIN(215, "P PAD VDDIO 26"),
- PINCTRL_PIN(216, "PO EMIF 1 A26"),
- PINCTRL_PIN(217, "PO EMIF 1 A25"),
- PINCTRL_PIN(218, "P PAD VSSIO 26"),
- PINCTRL_PIN(219, "PO EMIF 1 A24"),
- PINCTRL_PIN(220, "PO EMIF 1 A23"),
- /* Pads along the bottom edge of the chip */
- PINCTRL_PIN(221, "PO EMIF 1 A22"),
- PINCTRL_PIN(222, "PO EMIF 1 A21"),
- PINCTRL_PIN(223, "P PAD VDD 21"),
- PINCTRL_PIN(224, "P PAD GND 21"),
- PINCTRL_PIN(225, "P PAD VSSIO 27"),
- PINCTRL_PIN(226, "P PAD VDDIO 27"),
- PINCTRL_PIN(227, "PO EMIF 1 A20"),
- PINCTRL_PIN(228, "PO EMIF 1 A19"),
- PINCTRL_PIN(229, "PO EMIF 1 A18"),
- PINCTRL_PIN(230, "PO EMIF 1 A17"),
- PINCTRL_PIN(231, "P PAD VDDIO 28"),
- PINCTRL_PIN(232, "P PAD VSSIO 28"),
- PINCTRL_PIN(233, "PO EMIF 1 A16"),
- PINCTRL_PIN(234, "PIO EMIF 1 D15"),
- PINCTRL_PIN(235, "PO EMIF 1 A15"),
- PINCTRL_PIN(236, "PIO EMIF 1 D14"),
- PINCTRL_PIN(237, "P PAD VDD 22"),
- PINCTRL_PIN(238, "P PAD GND 22"),
- PINCTRL_PIN(239, "P PAD VSSIO 29"),
- PINCTRL_PIN(240, "P PAD VDDIO 29"),
- PINCTRL_PIN(241, "PO EMIF 1 A14"),
- PINCTRL_PIN(242, "PIO EMIF 1 D13"),
- PINCTRL_PIN(243, "PO EMIF 1 A13"),
- PINCTRL_PIN(244, "PIO EMIF 1 D12"),
- PINCTRL_PIN(245, "P PAD VSSIO 30"),
- PINCTRL_PIN(246, "P PAD VDDIO 30"),
- PINCTRL_PIN(247, "PO EMIF 1 A12"),
- PINCTRL_PIN(248, "PIO EMIF 1 D11"),
- PINCTRL_PIN(249, "PO EMIF 1 A11"),
- PINCTRL_PIN(250, "PIO EMIF 1 D10"),
- PINCTRL_PIN(251, "P PAD VSSIO 31"),
- PINCTRL_PIN(252, "P PAD VDDIO 31"),
- PINCTRL_PIN(253, "PO EMIF 1 A10"),
- PINCTRL_PIN(254, "PIO EMIF 1 D09"),
- PINCTRL_PIN(255, "PO EMIF 1 A09"),
- PINCTRL_PIN(256, "P PAD VDDIO 32"),
- PINCTRL_PIN(257, "P PAD VSSIO 32"),
- PINCTRL_PIN(258, "P PAD GND 24"),
- PINCTRL_PIN(259, "P PAD VDD 24"),
- PINCTRL_PIN(260, "PIO EMIF 1 D08"),
- PINCTRL_PIN(261, "PO EMIF 1 A08"),
- PINCTRL_PIN(262, "PIO EMIF 1 D07"),
- PINCTRL_PIN(263, "PO EMIF 1 A07"),
- PINCTRL_PIN(264, "P PAD VDDIO 33"),
- PINCTRL_PIN(265, "P PAD VSSIO 33"),
- PINCTRL_PIN(266, "PIO EMIF 1 D06"),
- PINCTRL_PIN(267, "PO EMIF 1 A06"),
- PINCTRL_PIN(268, "PIO EMIF 1 D05"),
- PINCTRL_PIN(269, "PO EMIF 1 A05"),
- PINCTRL_PIN(270, "P PAD VDDIO 34"),
- PINCTRL_PIN(271, "P PAD VSSIO 34"),
- PINCTRL_PIN(272, "PIO EMIF 1 D04"),
- PINCTRL_PIN(273, "PO EMIF 1 A04"),
- PINCTRL_PIN(274, "PIO EMIF 1 D03"),
- PINCTRL_PIN(275, "PO EMIF 1 A03"),
- PINCTRL_PIN(276, "P PAD VDDIO 35"),
- PINCTRL_PIN(277, "P PAD VSSIO 35"),
- PINCTRL_PIN(278, "P PAD GND 23"),
- PINCTRL_PIN(279, "P PAD VDD 23"),
- PINCTRL_PIN(280, "PIO EMIF 1 D02"),
- PINCTRL_PIN(281, "PO EMIF 1 A02"),
- PINCTRL_PIN(282, "PIO EMIF 1 D01"),
- PINCTRL_PIN(283, "PO EMIF 1 A01"),
- PINCTRL_PIN(284, "P PAD VDDIO 36"),
- PINCTRL_PIN(285, "P PAD VSSIO 36"),
- PINCTRL_PIN(286, "PIO EMIF 1 D00"),
- PINCTRL_PIN(287, "PO EMIF 1 BE1 N"),
- PINCTRL_PIN(288, "PO EMIF 1 BE0 N"),
- PINCTRL_PIN(289, "PO EMIF 1 ADV N"),
- PINCTRL_PIN(290, "P PAD VDDIO 37"),
- PINCTRL_PIN(291, "P PAD VSSIO 37"),
- PINCTRL_PIN(292, "PO EMIF 1 SD CKE0"),
- PINCTRL_PIN(293, "PO EMIF 1 OE N"),
- PINCTRL_PIN(294, "PO EMIF 1 WE N"),
- PINCTRL_PIN(295, "P PAD VDDIO 38"),
- PINCTRL_PIN(296, "P PAD VSSIO 38"),
- PINCTRL_PIN(297, "PO EMIF 1 CLK"),
- PINCTRL_PIN(298, "PIO EMIF 1 SD CLK"),
- PINCTRL_PIN(299, "P PAD VSSIO 45 (not bonded)"),
- PINCTRL_PIN(300, "P PAD VDDIO 42"),
- PINCTRL_PIN(301, "P PAD VSSIO 42"),
- PINCTRL_PIN(302, "P PAD GND 31"),
- PINCTRL_PIN(303, "P PAD VDD 31"),
- PINCTRL_PIN(304, "PI EMIF 1 RET CLK"),
- PINCTRL_PIN(305, "PI EMIF 1 WAIT N"),
- PINCTRL_PIN(306, "PI EMIF 1 NFIF READY"),
- PINCTRL_PIN(307, "PO EMIF 1 SD CKE1"),
- PINCTRL_PIN(308, "PO EMIF 1 CS3 N"),
- PINCTRL_PIN(309, "P PAD VDD 25"),
- PINCTRL_PIN(310, "P PAD GND 25"),
- PINCTRL_PIN(311, "P PAD VSSIO 39"),
- PINCTRL_PIN(312, "P PAD VDDIO 39"),
- PINCTRL_PIN(313, "PO EMIF 1 CS2 N"),
- PINCTRL_PIN(314, "PO EMIF 1 CS1 N"),
- PINCTRL_PIN(315, "PO EMIF 1 CS0 N"),
- PINCTRL_PIN(316, "PO ETM TRACE PKT0"),
- PINCTRL_PIN(317, "PO ETM TRACE PKT1"),
- PINCTRL_PIN(318, "PO ETM TRACE PKT2"),
- PINCTRL_PIN(319, "P PAD VDD 30"),
- PINCTRL_PIN(320, "P PAD GND 30"),
- PINCTRL_PIN(321, "P PAD VSSIO 44"),
- PINCTRL_PIN(322, "P PAD VDDIO 44"),
- PINCTRL_PIN(323, "PO ETM TRACE PKT3"),
- PINCTRL_PIN(324, "PO ETM TRACE PKT4"),
- PINCTRL_PIN(325, "PO ETM TRACE PKT5"),
- PINCTRL_PIN(326, "PO ETM TRACE PKT6"),
- PINCTRL_PIN(327, "PO ETM TRACE PKT7"),
- PINCTRL_PIN(328, "PO ETM PIPE STAT0"),
- PINCTRL_PIN(329, "P PAD VDD 26"),
- PINCTRL_PIN(330, "P PAD GND 26"),
- PINCTRL_PIN(331, "P PAD VSSIO 40"),
- PINCTRL_PIN(332, "P PAD VDDIO 40"),
- PINCTRL_PIN(333, "PO ETM PIPE STAT1"),
- PINCTRL_PIN(334, "PO ETM PIPE STAT2"),
- PINCTRL_PIN(335, "PO ETM TRACE CLK"),
- PINCTRL_PIN(336, "PO ETM TRACE SYNC"),
- PINCTRL_PIN(337, "PIO ACC GPIO 33"),
- PINCTRL_PIN(338, "PIO ACC GPIO 32"),
- PINCTRL_PIN(339, "PIO ACC GPIO 30"),
- PINCTRL_PIN(340, "PIO ACC GPIO 29"),
- PINCTRL_PIN(341, "P PAD VDDIO 17"),
- PINCTRL_PIN(342, "P PAD VSSIO 17"),
- PINCTRL_PIN(343, "P PAD GND 15"),
- PINCTRL_PIN(344, "P PAD VDD 15"),
- PINCTRL_PIN(345, "PIO ACC GPIO 28"),
- PINCTRL_PIN(346, "PIO ACC GPIO 27"),
- PINCTRL_PIN(347, "PIO ACC GPIO 16"),
- PINCTRL_PIN(348, "PI TAP TMS"),
- PINCTRL_PIN(349, "PI TAP TDI"),
- PINCTRL_PIN(350, "PO TAP TDO"),
- PINCTRL_PIN(351, "PI TAP RST N"),
- /* Pads along the left edge of the chip */
- PINCTRL_PIN(352, "PI EMU MODE 0"),
- PINCTRL_PIN(353, "PO TAP RET CLK"),
- PINCTRL_PIN(354, "PI TAP CLK"),
- PINCTRL_PIN(355, "PO EMIF 0 SD CS N"),
- PINCTRL_PIN(356, "PO EMIF 0 SD CAS N"),
- PINCTRL_PIN(357, "PO EMIF 0 SD WE N"),
- PINCTRL_PIN(358, "P PAD VDDIO 1"),
- PINCTRL_PIN(359, "P PAD VSSIO 1"),
- PINCTRL_PIN(360, "P PAD GND 1"),
- PINCTRL_PIN(361, "P PAD VDD 1"),
- PINCTRL_PIN(362, "PO EMIF 0 SD CKE"),
- PINCTRL_PIN(363, "PO EMIF 0 SD DQML"),
- PINCTRL_PIN(364, "PO EMIF 0 SD DQMU"),
- PINCTRL_PIN(365, "PO EMIF 0 SD RAS N"),
- PINCTRL_PIN(366, "PIO EMIF 0 D15"),
- PINCTRL_PIN(367, "PO EMIF 0 A15"),
- PINCTRL_PIN(368, "PIO EMIF 0 D14"),
- PINCTRL_PIN(369, "PO EMIF 0 A14"),
- PINCTRL_PIN(370, "PIO EMIF 0 D13"),
- PINCTRL_PIN(371, "PO EMIF 0 A13"),
- PINCTRL_PIN(372, "P PAD VDDIO 2"),
- PINCTRL_PIN(373, "P PAD VSSIO 2"),
- PINCTRL_PIN(374, "P PAD GND 2"),
- PINCTRL_PIN(375, "P PAD VDD 2"),
- PINCTRL_PIN(376, "PIO EMIF 0 D12"),
- PINCTRL_PIN(377, "PO EMIF 0 A12"),
- PINCTRL_PIN(378, "PIO EMIF 0 D11"),
- PINCTRL_PIN(379, "PO EMIF 0 A11"),
- PINCTRL_PIN(380, "PIO EMIF 0 D10"),
- PINCTRL_PIN(381, "PO EMIF 0 A10"),
- PINCTRL_PIN(382, "PIO EMIF 0 D09"),
- PINCTRL_PIN(383, "PO EMIF 0 A09"),
- PINCTRL_PIN(384, "PIO EMIF 0 D08"),
- PINCTRL_PIN(385, "PO EMIF 0 A08"),
- PINCTRL_PIN(386, "PIO EMIF 0 D07"),
- PINCTRL_PIN(387, "PO EMIF 0 A07"),
- PINCTRL_PIN(388, "P PAD VDDIO 3"),
- PINCTRL_PIN(389, "P PAD VSSIO 3"),
- PINCTRL_PIN(390, "P PAD GND 3"),
- PINCTRL_PIN(391, "P PAD VDD 3"),
- PINCTRL_PIN(392, "PO EFUSE RDOUT1"),
- PINCTRL_PIN(393, "PIO EMIF 0 D06"),
- PINCTRL_PIN(394, "PO EMIF 0 A06"),
- PINCTRL_PIN(395, "PIO EMIF 0 D05"),
- PINCTRL_PIN(396, "PO EMIF 0 A05"),
- PINCTRL_PIN(397, "PIO EMIF 0 D04"),
- PINCTRL_PIN(398, "PO EMIF 0 A04"),
- PINCTRL_PIN(399, "A PADS/A VDDCO1v82v5 GND 80U SF LIN VDDCO AF"),
- PINCTRL_PIN(400, "PWR VDDCO AF"),
- PINCTRL_PIN(401, "PWR EFUSE HV1"),
- PINCTRL_PIN(402, "P PAD VSSIO 4"),
- PINCTRL_PIN(403, "P PAD VDDIO 4"),
- PINCTRL_PIN(404, "P PAD GND 4"),
- PINCTRL_PIN(405, "P PAD VDD 4"),
- PINCTRL_PIN(406, "PIO EMIF 0 D03"),
- PINCTRL_PIN(407, "PO EMIF 0 A03"),
- PINCTRL_PIN(408, "PWR EFUSE HV2"),
- PINCTRL_PIN(409, "PWR EFUSE HV3"),
- PINCTRL_PIN(410, "PIO EMIF 0 D02"),
- PINCTRL_PIN(411, "PO EMIF 0 A02"),
- PINCTRL_PIN(412, "PIO EMIF 0 D01"),
- PINCTRL_PIN(413, "P PAD VDDIO 5"),
- PINCTRL_PIN(414, "P PAD VSSIO 5"),
- PINCTRL_PIN(415, "P PAD GND 5"),
- PINCTRL_PIN(416, "P PAD VDD 5"),
- PINCTRL_PIN(417, "PO EMIF 0 A01"),
- PINCTRL_PIN(418, "PIO EMIF 0 D00"),
- PINCTRL_PIN(419, "IF 0 SD CLK"),
- PINCTRL_PIN(420, "APP SPI CLK"),
- PINCTRL_PIN(421, "APP SPI DO"),
- PINCTRL_PIN(422, "APP SPI DI"),
- PINCTRL_PIN(423, "APP SPI CS0"),
- PINCTRL_PIN(424, "APP SPI CS1"),
- PINCTRL_PIN(425, "APP SPI CS2"),
- PINCTRL_PIN(426, "PIO APP GPIO 10"),
- PINCTRL_PIN(427, "P PAD VDDIO 41"),
- PINCTRL_PIN(428, "P PAD VSSIO 41"),
- PINCTRL_PIN(429, "P PAD GND 6"),
- PINCTRL_PIN(430, "P PAD VDD 6"),
- PINCTRL_PIN(431, "PIO ACC SDIO0 CMD"),
- PINCTRL_PIN(432, "PIO ACC SDIO0 CK"),
- PINCTRL_PIN(433, "PIO ACC SDIO0 D3"),
- PINCTRL_PIN(434, "PIO ACC SDIO0 D2"),
- PINCTRL_PIN(435, "PIO ACC SDIO0 D1"),
- PINCTRL_PIN(436, "PIO ACC SDIO0 D0"),
- PINCTRL_PIN(437, "PIO USB PU"),
- PINCTRL_PIN(438, "PIO USB SP"),
- PINCTRL_PIN(439, "PIO USB DAT VP"),
- PINCTRL_PIN(440, "PIO USB SE0 VM"),
- PINCTRL_PIN(441, "PIO USB OE"),
- PINCTRL_PIN(442, "PIO USB SUSP"),
- PINCTRL_PIN(443, "P PAD VSSIO 6"),
- PINCTRL_PIN(444, "P PAD VDDIO 6"),
- PINCTRL_PIN(445, "PIO USB PUEN"),
- PINCTRL_PIN(446, "PIO ACC UART0 RX"),
- PINCTRL_PIN(447, "PIO ACC UART0 TX"),
- PINCTRL_PIN(448, "PIO ACC UART0 CTS"),
- PINCTRL_PIN(449, "PIO ACC UART0 RTS"),
- PINCTRL_PIN(450, "PIO ACC UART3 RX"),
- PINCTRL_PIN(451, "PIO ACC UART3 TX"),
- PINCTRL_PIN(452, "PIO ACC UART3 CTS"),
- PINCTRL_PIN(453, "PIO ACC UART3 RTS"),
- PINCTRL_PIN(454, "PIO ACC IRDA TX"),
- PINCTRL_PIN(455, "P PAD VDDIO 7"),
- PINCTRL_PIN(456, "P PAD VSSIO 7"),
- PINCTRL_PIN(457, "P PAD GND 7"),
- PINCTRL_PIN(458, "P PAD VDD 7"),
- PINCTRL_PIN(459, "PIO ACC IRDA RX"),
- PINCTRL_PIN(460, "PIO ACC PCM I2S CLK"),
- PINCTRL_PIN(461, "PIO ACC PCM I2S WS"),
- PINCTRL_PIN(462, "PIO ACC PCM I2S DATA A"),
- PINCTRL_PIN(463, "PIO ACC PCM I2S DATA B"),
- PINCTRL_PIN(464, "PO SIM CLK"),
- PINCTRL_PIN(465, "PIO ACC IRDA SD"),
- PINCTRL_PIN(466, "PIO SIM DATA"),
-};
-
-/**
- * @dev: a pointer back to containing device
- * @virtbase: the offset to the controller in virtual memory
- */
-struct u300_pmx {
- struct device *dev;
- struct pinctrl_dev *pctl;
- void __iomem *virtbase;
-};
-
-/**
- * u300_pmx_registers - the array of registers read/written for each pinmux
- * shunt setting
- */
-static const u32 u300_pmx_registers[] = {
- U300_SYSCON_PMC1LR,
- U300_SYSCON_PMC1HR,
- U300_SYSCON_PMC2R,
- U300_SYSCON_PMC3R,
- U300_SYSCON_PMC4R,
-};
-
-/**
- * struct u300_pin_group - describes a U300 pin group
- * @name: the name of this specific pin group
- * @pins: an array of discrete physical pins used in this group, taken
- * from the driver-local pin enumeration space
- * @num_pins: the number of pins in this group array, i.e. the number of
- * elements in .pins so we can iterate over that array
- */
-struct u300_pin_group {
- const char *name;
- const unsigned int *pins;
- const unsigned num_pins;
-};
-
-/**
- * struct pmx_onmask - mask bits to enable/disable padmux
- * @mask: mask bits to disable
- * @val: mask bits to enable
- *
- * onmask lazy dog:
- * onmask = {
- * {"PMC1LR" mask, "PMC1LR" value},
- * {"PMC1HR" mask, "PMC1HR" value},
- * {"PMC2R" mask, "PMC2R" value},
- * {"PMC3R" mask, "PMC3R" value},
- * {"PMC4R" mask, "PMC4R" value}
- * }
- */
-struct u300_pmx_mask {
- u16 mask;
- u16 bits;
-};
-
-/* The chip power pins are VDD, GND, VDDIO and VSSIO */
-static const unsigned power_pins[] = { 0, 1, 3, 31, 46, 47, 49, 50, 61, 62, 63,
- 64, 78, 79, 80, 81, 92, 93, 94, 95, 101, 102, 103, 104, 115, 116, 117,
- 118, 130, 131, 132, 133, 145, 146, 147, 148, 159, 160, 172, 173, 174,
- 175, 187, 188, 189, 190, 201, 202, 211, 212, 213, 214, 215, 218, 223,
- 224, 225, 226, 231, 232, 237, 238, 239, 240, 245, 246, 251, 252, 256,
- 257, 258, 259, 264, 265, 270, 271, 276, 277, 278, 279, 284, 285, 290,
- 291, 295, 296, 299, 300, 301, 302, 303, 309, 310, 311, 312, 319, 320,
- 321, 322, 329, 330, 331, 332, 341, 342, 343, 344, 358, 359, 360, 361,
- 372, 373, 374, 375, 388, 389, 390, 391, 402, 403, 404, 405, 413, 414,
- 415, 416, 427, 428, 429, 430, 443, 444, 455, 456, 457, 458 };
-static const unsigned emif0_pins[] = { 355, 356, 357, 362, 363, 364, 365, 366,
- 367, 368, 369, 370, 371, 376, 377, 378, 379, 380, 381, 382, 383, 384,
- 385, 386, 387, 393, 394, 395, 396, 397, 398, 406, 407, 410, 411, 412,
- 417, 418 };
-static const unsigned emif1_pins[] = { 216, 217, 219, 220, 221, 222, 227, 228,
- 229, 230, 233, 234, 235, 236, 241, 242, 243, 244, 247, 248, 249, 250,
- 253, 254, 255, 260, 261, 262, 263, 266, 267, 268, 269, 272, 273, 274,
- 275, 280, 281, 282, 283, 286, 287, 288, 289, 292, 293, 294, 297, 298,
- 304, 305, 306, 307, 308, 313, 314, 315 };
-static const unsigned uart0_pins[] = { 134, 135, 136, 137 };
-static const unsigned mmc0_pins[] = { 166, 167, 168, 169, 170, 171, 176, 177 };
-static const unsigned spi0_pins[] = { 420, 421, 422, 423, 424, 425 };
-
-static const struct u300_pmx_mask emif0_mask[] = {
- {0, 0},
- {0, 0},
- {0, 0},
- {0, 0},
- {0, 0},
-};
-
-static const struct u300_pmx_mask emif1_mask[] = {
- /*
- * This connects the SDRAM to CS2 and a NAND flash to
- * CS0 on the EMIF.
- */
- {
- U300_SYSCON_PMC1LR_EMIF_1_CS2_MASK |
- U300_SYSCON_PMC1LR_EMIF_1_CS1_MASK |
- U300_SYSCON_PMC1LR_EMIF_1_CS0_MASK |
- U300_SYSCON_PMC1LR_EMIF_1_MASK,
- U300_SYSCON_PMC1LR_EMIF_1_CS2_SDRAM |
- U300_SYSCON_PMC1LR_EMIF_1_CS1_STATIC |
- U300_SYSCON_PMC1LR_EMIF_1_CS0_NFIF |
- U300_SYSCON_PMC1LR_EMIF_1_SDRAM0
- },
- {0, 0},
- {0, 0},
- {0, 0},
- {0, 0},
-};
-
-static const struct u300_pmx_mask uart0_mask[] = {
- {0, 0},
- {
- U300_SYSCON_PMC1HR_APP_UART0_1_MASK |
- U300_SYSCON_PMC1HR_APP_UART0_2_MASK,
- U300_SYSCON_PMC1HR_APP_UART0_1_UART0 |
- U300_SYSCON_PMC1HR_APP_UART0_2_UART0
- },
- {0, 0},
- {0, 0},
- {0, 0},
-};
-
-static const struct u300_pmx_mask mmc0_mask[] = {
- { U300_SYSCON_PMC1LR_MMCSD_MASK, U300_SYSCON_PMC1LR_MMCSD_MMCSD},
- {0, 0},
- {0, 0},
- {0, 0},
- { U300_SYSCON_PMC4R_APP_MISC_12_MASK,
- U300_SYSCON_PMC4R_APP_MISC_12_APP_GPIO }
-};
-
-static const struct u300_pmx_mask spi0_mask[] = {
- {0, 0},
- {
- U300_SYSCON_PMC1HR_APP_SPI_2_MASK |
- U300_SYSCON_PMC1HR_APP_SPI_CS_1_MASK |
- U300_SYSCON_PMC1HR_APP_SPI_CS_2_MASK,
- U300_SYSCON_PMC1HR_APP_SPI_2_SPI |
- U300_SYSCON_PMC1HR_APP_SPI_CS_1_SPI |
- U300_SYSCON_PMC1HR_APP_SPI_CS_2_SPI
- },
- {0, 0},
- {0, 0},
- {0, 0}
-};
-
-static const struct u300_pin_group u300_pin_groups[] = {
- {
- .name = "powergrp",
- .pins = power_pins,
- .num_pins = ARRAY_SIZE(power_pins),
- },
- {
- .name = "emif0grp",
- .pins = emif0_pins,
- .num_pins = ARRAY_SIZE(emif0_pins),
- },
- {
- .name = "emif1grp",
- .pins = emif1_pins,
- .num_pins = ARRAY_SIZE(emif1_pins),
- },
- {
- .name = "uart0grp",
- .pins = uart0_pins,
- .num_pins = ARRAY_SIZE(uart0_pins),
- },
- {
- .name = "mmc0grp",
- .pins = mmc0_pins,
- .num_pins = ARRAY_SIZE(mmc0_pins),
- },
- {
- .name = "spi0grp",
- .pins = spi0_pins,
- .num_pins = ARRAY_SIZE(spi0_pins),
- },
-};
-
-static int u300_get_groups_count(struct pinctrl_dev *pctldev)
-{
- return ARRAY_SIZE(u300_pin_groups);
-}
-
-static const char *u300_get_group_name(struct pinctrl_dev *pctldev,
- unsigned selector)
-{
- return u300_pin_groups[selector].name;
-}
-
-static int u300_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
- const unsigned **pins,
- unsigned *num_pins)
-{
- *pins = u300_pin_groups[selector].pins;
- *num_pins = u300_pin_groups[selector].num_pins;
- return 0;
-}
-
-static void u300_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
- unsigned offset)
-{
- seq_printf(s, " " DRIVER_NAME);
-}
-
-static const struct pinctrl_ops u300_pctrl_ops = {
- .get_groups_count = u300_get_groups_count,
- .get_group_name = u300_get_group_name,
- .get_group_pins = u300_get_group_pins,
- .pin_dbg_show = u300_pin_dbg_show,
-};
-
-/*
- * Here we define the available functions and their corresponding pin groups
- */
-
-/**
- * struct u300_pmx_func - describes U300 pinmux functions
- * @name: the name of this specific function
- * @groups: corresponding pin groups
- * @onmask: bits to set to enable this when doing pin muxing
- */
-struct u300_pmx_func {
- const char *name;
- const char * const *groups;
- const unsigned num_groups;
- const struct u300_pmx_mask *mask;
-};
-
-static const char * const powergrps[] = { "powergrp" };
-static const char * const emif0grps[] = { "emif0grp" };
-static const char * const emif1grps[] = { "emif1grp" };
-static const char * const uart0grps[] = { "uart0grp" };
-static const char * const mmc0grps[] = { "mmc0grp" };
-static const char * const spi0grps[] = { "spi0grp" };
-
-static const struct u300_pmx_func u300_pmx_functions[] = {
- {
- .name = "power",
- .groups = powergrps,
- .num_groups = ARRAY_SIZE(powergrps),
- /* Mask is N/A */
- },
- {
- .name = "emif0",
- .groups = emif0grps,
- .num_groups = ARRAY_SIZE(emif0grps),
- .mask = emif0_mask,
- },
- {
- .name = "emif1",
- .groups = emif1grps,
- .num_groups = ARRAY_SIZE(emif1grps),
- .mask = emif1_mask,
- },
- {
- .name = "uart0",
- .groups = uart0grps,
- .num_groups = ARRAY_SIZE(uart0grps),
- .mask = uart0_mask,
- },
- {
- .name = "mmc0",
- .groups = mmc0grps,
- .num_groups = ARRAY_SIZE(mmc0grps),
- .mask = mmc0_mask,
- },
- {
- .name = "spi0",
- .groups = spi0grps,
- .num_groups = ARRAY_SIZE(spi0grps),
- .mask = spi0_mask,
- },
-};
-
-static void u300_pmx_endisable(struct u300_pmx *upmx, unsigned selector,
- bool enable)
-{
- u16 regval, val, mask;
- int i;
- const struct u300_pmx_mask *upmx_mask;
-
- upmx_mask = u300_pmx_functions[selector].mask;
- for (i = 0; i < ARRAY_SIZE(u300_pmx_registers); i++) {
- if (enable)
- val = upmx_mask->bits;
- else
- val = 0;
-
- mask = upmx_mask->mask;
- if (mask != 0) {
- regval = readw(upmx->virtbase + u300_pmx_registers[i]);
- regval &= ~mask;
- regval |= val;
- writew(regval, upmx->virtbase + u300_pmx_registers[i]);
- }
- upmx_mask++;
- }
-}
-
-static int u300_pmx_set_mux(struct pinctrl_dev *pctldev, unsigned selector,
- unsigned group)
-{
- struct u300_pmx *upmx;
-
- /* There is nothing to do with the power pins */
- if (selector == 0)
- return 0;
-
- upmx = pinctrl_dev_get_drvdata(pctldev);
- u300_pmx_endisable(upmx, selector, true);
-
- return 0;
-}
-
-static int u300_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
-{
- return ARRAY_SIZE(u300_pmx_functions);
-}
-
-static const char *u300_pmx_get_func_name(struct pinctrl_dev *pctldev,
- unsigned selector)
-{
- return u300_pmx_functions[selector].name;
-}
-
-static int u300_pmx_get_groups(struct pinctrl_dev *pctldev, unsigned selector,
- const char * const **groups,
- unsigned * const num_groups)
-{
- *groups = u300_pmx_functions[selector].groups;
- *num_groups = u300_pmx_functions[selector].num_groups;
- return 0;
-}
-
-static const struct pinmux_ops u300_pmx_ops = {
- .get_functions_count = u300_pmx_get_funcs_count,
- .get_function_name = u300_pmx_get_func_name,
- .get_function_groups = u300_pmx_get_groups,
- .set_mux = u300_pmx_set_mux,
-};
-
-static int u300_pin_config_get(struct pinctrl_dev *pctldev, unsigned pin,
- unsigned long *config)
-{
- struct pinctrl_gpio_range *range =
- pinctrl_find_gpio_range_from_pin(pctldev, pin);
-
- /* We get config for those pins we CAN get it for and that's it */
- if (!range)
- return -ENOTSUPP;
-
- return u300_gpio_config_get(range->gc,
- (pin - range->pin_base + range->base),
- config);
-}
-
-static int u300_pin_config_set(struct pinctrl_dev *pctldev, unsigned pin,
- unsigned long *configs, unsigned num_configs)
-{
- struct pinctrl_gpio_range *range =
- pinctrl_find_gpio_range_from_pin(pctldev, pin);
- int ret, i;
-
- if (!range)
- return -EINVAL;
-
- for (i = 0; i < num_configs; i++) {
- /* Note: none of these configurations take any argument */
- ret = u300_gpio_config_set(range->gc,
- (pin - range->pin_base + range->base),
- pinconf_to_config_param(configs[i]));
- if (ret)
- return ret;
- } /* for each config */
-
- return 0;
-}
-
-static const struct pinconf_ops u300_pconf_ops = {
- .is_generic = true,
- .pin_config_get = u300_pin_config_get,
- .pin_config_set = u300_pin_config_set,
-};
-
-static struct pinctrl_desc u300_pmx_desc = {
- .name = DRIVER_NAME,
- .pins = u300_pads,
- .npins = ARRAY_SIZE(u300_pads),
- .pctlops = &u300_pctrl_ops,
- .pmxops = &u300_pmx_ops,
- .confops = &u300_pconf_ops,
- .owner = THIS_MODULE,
-};
-
-static int u300_pmx_probe(struct platform_device *pdev)
-{
- struct u300_pmx *upmx;
-
- /* Create state holders etc for this driver */
- upmx = devm_kzalloc(&pdev->dev, sizeof(*upmx), GFP_KERNEL);
- if (!upmx)
- return -ENOMEM;
-
- upmx->dev = &pdev->dev;
-
- upmx->virtbase = devm_platform_ioremap_resource(pdev, 0);
- if (IS_ERR(upmx->virtbase))
- return PTR_ERR(upmx->virtbase);
-
- upmx->pctl = devm_pinctrl_register(&pdev->dev, &u300_pmx_desc, upmx);
- if (IS_ERR(upmx->pctl)) {
- dev_err(&pdev->dev, "could not register U300 pinmux driver\n");
- return PTR_ERR(upmx->pctl);
- }
-
- platform_set_drvdata(pdev, upmx);
-
- dev_info(&pdev->dev, "initialized U300 pin control driver\n");
-
- return 0;
-}
-
-static const struct of_device_id u300_pinctrl_match[] = {
- { .compatible = "stericsson,pinctrl-u300" },
- {},
-};
-
-
-static struct platform_driver u300_pmx_driver = {
- .driver = {
- .name = DRIVER_NAME,
- .of_match_table = u300_pinctrl_match,
- },
- .probe = u300_pmx_probe,
-};
-
-static int __init u300_pmx_init(void)
-{
- return platform_driver_register(&u300_pmx_driver);
-}
-arch_initcall(u300_pmx_init);
-
-static void __exit u300_pmx_exit(void)
-{
- platform_driver_unregister(&u300_pmx_driver);
-}
-module_exit(u300_pmx_exit);
-
-MODULE_AUTHOR("Linus Walleij <linus.walleij@linaro.org>");
-MODULE_DESCRIPTION("U300 pin control driver");
-MODULE_LICENSE("GPL v2");
diff --git a/drivers/pinctrl/pinmux.c b/drivers/pinctrl/pinmux.c
index bab888f..36a11c9 100644
--- a/drivers/pinctrl/pinmux.c
+++ b/drivers/pinctrl/pinmux.c
@@ -564,7 +564,7 @@
continue;
}
- seq_printf(s, "function: %s, groups = [ ", func);
+ seq_printf(s, "function %d: %s, groups = [ ", func_selector, func);
for (i = 0; i < num_groups; i++)
seq_printf(s, "%s ", groups[i]);
seq_puts(s, "]\n");
diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig
index a003776..6853a89 100644
--- a/drivers/pinctrl/qcom/Kconfig
+++ b/drivers/pinctrl/qcom/Kconfig
@@ -220,6 +220,15 @@
Qualcomm Technologies Inc TLMM block found on the Qualcomm
Technologies Inc SC7280 platform.
+config PINCTRL_SC8180X
+ tristate "Qualcomm Technologies Inc SC8180x pin controller driver"
+ depends on GPIOLIB && OF
+ select PINCTRL_MSM
+ help
+ This is the pinctrl, pinmux, pinconf and gpiolib driver for the
+ Qualcomm Technologies Inc TLMM block found on the Qualcomm
+ Technologies Inc SC8180x platform.
+
config PINCTRL_SDM660
tristate "Qualcomm Technologies Inc SDM660 pin controller driver"
depends on GPIOLIB && OF
@@ -265,6 +274,15 @@
Qualcomm Technologies Inc TLMM block found on the Qualcomm
Technologies Inc SM8250 platform.
+config PINCTRL_SM8350
+ tristate "Qualcomm Technologies Inc SM8350 pin controller driver"
+ depends on GPIOLIB && OF
+ select PINCTRL_MSM
+ help
+ This is the pinctrl, pinmux, pinconf and gpiolib driver for the
+ Qualcomm Technologies Inc TLMM block found on the Qualcomm
+ Technologies Inc SM8350 platform.
+
config PINCTRL_LPASS_LPI
tristate "Qualcomm Technologies Inc LPASS LPI pin controller driver"
select PINMUX
diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile
index 91875a3..d4301fb 100644
--- a/drivers/pinctrl/qcom/Makefile
+++ b/drivers/pinctrl/qcom/Makefile
@@ -26,9 +26,11 @@
obj-$(CONFIG_PINCTRL_QCOM_SSBI_PMIC) += pinctrl-ssbi-mpp.o
obj-$(CONFIG_PINCTRL_SC7180) += pinctrl-sc7180.o
obj-$(CONFIG_PINCTRL_SC7280) += pinctrl-sc7280.o
+obj-$(CONFIG_PINCTRL_SC8180X) += pinctrl-sc8180x.o
obj-$(CONFIG_PINCTRL_SDM660) += pinctrl-sdm660.o
obj-$(CONFIG_PINCTRL_SDM845) += pinctrl-sdm845.o
obj-$(CONFIG_PINCTRL_SDX55) += pinctrl-sdx55.o
obj-$(CONFIG_PINCTRL_SM8150) += pinctrl-sm8150.o
obj-$(CONFIG_PINCTRL_SM8250) += pinctrl-sm8250.o
+obj-$(CONFIG_PINCTRL_SM8350) += pinctrl-sm8350.o
obj-$(CONFIG_PINCTRL_LPASS_LPI) += pinctrl-lpass-lpi.o
diff --git a/drivers/pinctrl/qcom/pinctrl-sc8180x.c b/drivers/pinctrl/qcom/pinctrl-sc8180x.c
new file mode 100644
index 0000000..b765bf6
--- /dev/null
+++ b/drivers/pinctrl/qcom/pinctrl-sc8180x.c
@@ -0,0 +1,1624 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2020-2021, Linaro Ltd.
+ */
+
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/pinctrl/pinctrl.h>
+
+#include "pinctrl-msm.h"
+
+static const char * const sc8180x_tiles[] = {
+ "south",
+ "east",
+ "west"
+};
+
+enum {
+ SOUTH,
+ EAST,
+ WEST
+};
+
+#define FUNCTION(fname) \
+ [msm_mux_##fname] = { \
+ .name = #fname, \
+ .groups = fname##_groups, \
+ .ngroups = ARRAY_SIZE(fname##_groups), \
+ }
+
+#define REG_SIZE 0x1000
+#define PINGROUP_OFFSET(id, _tile, offset, f1, f2, f3, f4, f5, f6, f7, f8, f9) \
+ { \
+ .name = "gpio" #id, \
+ .pins = gpio##id##_pins, \
+ .npins = (unsigned int)ARRAY_SIZE(gpio##id##_pins), \
+ .funcs = (int[]){ \
+ msm_mux_gpio, /* gpio mode */ \
+ msm_mux_##f1, \
+ msm_mux_##f2, \
+ msm_mux_##f3, \
+ msm_mux_##f4, \
+ msm_mux_##f5, \
+ msm_mux_##f6, \
+ msm_mux_##f7, \
+ msm_mux_##f8, \
+ msm_mux_##f9 \
+ }, \
+ .nfuncs = 10, \
+ .ctl_reg = REG_SIZE * id + offset, \
+ .io_reg = REG_SIZE * id + 0x4 + offset, \
+ .intr_cfg_reg = REG_SIZE * id + 0x8 + offset, \
+ .intr_status_reg = REG_SIZE * id + 0xc + offset,\
+ .intr_target_reg = REG_SIZE * id + 0x8 + offset,\
+ .tile = _tile, \
+ .mux_bit = 2, \
+ .pull_bit = 0, \
+ .drv_bit = 6, \
+ .oe_bit = 9, \
+ .in_bit = 0, \
+ .out_bit = 1, \
+ .intr_enable_bit = 0, \
+ .intr_status_bit = 0, \
+ .intr_target_bit = 5, \
+ .intr_target_kpss_val = 3, \
+ .intr_raw_status_bit = 4, \
+ .intr_polarity_bit = 1, \
+ .intr_detection_bit = 2, \
+ .intr_detection_width = 2, \
+ }
+
+#define PINGROUP(id, _tile, f1, f2, f3, f4, f5, f6, f7, f8, f9) \
+ PINGROUP_OFFSET(id, _tile, 0x0, f1, f2, f3, f4, f5, f6, f7, f8, f9)
+
+#define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv) \
+ { \
+ .name = #pg_name, \
+ .pins = pg_name##_pins, \
+ .npins = (unsigned int)ARRAY_SIZE(pg_name##_pins), \
+ .ctl_reg = ctl, \
+ .io_reg = 0, \
+ .intr_cfg_reg = 0, \
+ .intr_status_reg = 0, \
+ .intr_target_reg = 0, \
+ .tile = EAST, \
+ .mux_bit = -1, \
+ .pull_bit = pull, \
+ .drv_bit = drv, \
+ .oe_bit = -1, \
+ .in_bit = -1, \
+ .out_bit = -1, \
+ .intr_enable_bit = -1, \
+ .intr_status_bit = -1, \
+ .intr_target_bit = -1, \
+ .intr_raw_status_bit = -1, \
+ .intr_polarity_bit = -1, \
+ .intr_detection_bit = -1, \
+ .intr_detection_width = -1, \
+ }
+
+#define UFS_RESET(pg_name) \
+ { \
+ .name = #pg_name, \
+ .pins = pg_name##_pins, \
+ .npins = (unsigned int)ARRAY_SIZE(pg_name##_pins), \
+ .ctl_reg = 0xb6000, \
+ .io_reg = 0xb6004, \
+ .intr_cfg_reg = 0, \
+ .intr_status_reg = 0, \
+ .intr_target_reg = 0, \
+ .tile = SOUTH, \
+ .mux_bit = -1, \
+ .pull_bit = 3, \
+ .drv_bit = 0, \
+ .oe_bit = -1, \
+ .in_bit = -1, \
+ .out_bit = 0, \
+ .intr_enable_bit = -1, \
+ .intr_status_bit = -1, \
+ .intr_target_bit = -1, \
+ .intr_raw_status_bit = -1, \
+ .intr_polarity_bit = -1, \
+ .intr_detection_bit = -1, \
+ .intr_detection_width = -1, \
+ }
+static const struct pinctrl_pin_desc sc8180x_pins[] = {
+ PINCTRL_PIN(0, "GPIO_0"),
+ PINCTRL_PIN(1, "GPIO_1"),
+ PINCTRL_PIN(2, "GPIO_2"),
+ PINCTRL_PIN(3, "GPIO_3"),
+ PINCTRL_PIN(4, "GPIO_4"),
+ PINCTRL_PIN(5, "GPIO_5"),
+ PINCTRL_PIN(6, "GPIO_6"),
+ PINCTRL_PIN(7, "GPIO_7"),
+ PINCTRL_PIN(8, "GPIO_8"),
+ PINCTRL_PIN(9, "GPIO_9"),
+ PINCTRL_PIN(10, "GPIO_10"),
+ PINCTRL_PIN(11, "GPIO_11"),
+ PINCTRL_PIN(12, "GPIO_12"),
+ PINCTRL_PIN(13, "GPIO_13"),
+ PINCTRL_PIN(14, "GPIO_14"),
+ PINCTRL_PIN(15, "GPIO_15"),
+ PINCTRL_PIN(16, "GPIO_16"),
+ PINCTRL_PIN(17, "GPIO_17"),
+ PINCTRL_PIN(18, "GPIO_18"),
+ PINCTRL_PIN(19, "GPIO_19"),
+ PINCTRL_PIN(20, "GPIO_20"),
+ PINCTRL_PIN(21, "GPIO_21"),
+ PINCTRL_PIN(22, "GPIO_22"),
+ PINCTRL_PIN(23, "GPIO_23"),
+ PINCTRL_PIN(24, "GPIO_24"),
+ PINCTRL_PIN(25, "GPIO_25"),
+ PINCTRL_PIN(26, "GPIO_26"),
+ PINCTRL_PIN(27, "GPIO_27"),
+ PINCTRL_PIN(28, "GPIO_28"),
+ PINCTRL_PIN(29, "GPIO_29"),
+ PINCTRL_PIN(30, "GPIO_30"),
+ PINCTRL_PIN(31, "GPIO_31"),
+ PINCTRL_PIN(32, "GPIO_32"),
+ PINCTRL_PIN(33, "GPIO_33"),
+ PINCTRL_PIN(34, "GPIO_34"),
+ PINCTRL_PIN(35, "GPIO_35"),
+ PINCTRL_PIN(36, "GPIO_36"),
+ PINCTRL_PIN(37, "GPIO_37"),
+ PINCTRL_PIN(38, "GPIO_38"),
+ PINCTRL_PIN(39, "GPIO_39"),
+ PINCTRL_PIN(40, "GPIO_40"),
+ PINCTRL_PIN(41, "GPIO_41"),
+ PINCTRL_PIN(42, "GPIO_42"),
+ PINCTRL_PIN(43, "GPIO_43"),
+ PINCTRL_PIN(44, "GPIO_44"),
+ PINCTRL_PIN(45, "GPIO_45"),
+ PINCTRL_PIN(46, "GPIO_46"),
+ PINCTRL_PIN(47, "GPIO_47"),
+ PINCTRL_PIN(48, "GPIO_48"),
+ PINCTRL_PIN(49, "GPIO_49"),
+ PINCTRL_PIN(50, "GPIO_50"),
+ PINCTRL_PIN(51, "GPIO_51"),
+ PINCTRL_PIN(52, "GPIO_52"),
+ PINCTRL_PIN(53, "GPIO_53"),
+ PINCTRL_PIN(54, "GPIO_54"),
+ PINCTRL_PIN(55, "GPIO_55"),
+ PINCTRL_PIN(56, "GPIO_56"),
+ PINCTRL_PIN(57, "GPIO_57"),
+ PINCTRL_PIN(58, "GPIO_58"),
+ PINCTRL_PIN(59, "GPIO_59"),
+ PINCTRL_PIN(60, "GPIO_60"),
+ PINCTRL_PIN(61, "GPIO_61"),
+ PINCTRL_PIN(62, "GPIO_62"),
+ PINCTRL_PIN(63, "GPIO_63"),
+ PINCTRL_PIN(64, "GPIO_64"),
+ PINCTRL_PIN(65, "GPIO_65"),
+ PINCTRL_PIN(66, "GPIO_66"),
+ PINCTRL_PIN(67, "GPIO_67"),
+ PINCTRL_PIN(68, "GPIO_68"),
+ PINCTRL_PIN(69, "GPIO_69"),
+ PINCTRL_PIN(70, "GPIO_70"),
+ PINCTRL_PIN(71, "GPIO_71"),
+ PINCTRL_PIN(72, "GPIO_72"),
+ PINCTRL_PIN(73, "GPIO_73"),
+ PINCTRL_PIN(74, "GPIO_74"),
+ PINCTRL_PIN(75, "GPIO_75"),
+ PINCTRL_PIN(76, "GPIO_76"),
+ PINCTRL_PIN(77, "GPIO_77"),
+ PINCTRL_PIN(78, "GPIO_78"),
+ PINCTRL_PIN(79, "GPIO_79"),
+ PINCTRL_PIN(80, "GPIO_80"),
+ PINCTRL_PIN(81, "GPIO_81"),
+ PINCTRL_PIN(82, "GPIO_82"),
+ PINCTRL_PIN(83, "GPIO_83"),
+ PINCTRL_PIN(84, "GPIO_84"),
+ PINCTRL_PIN(85, "GPIO_85"),
+ PINCTRL_PIN(86, "GPIO_86"),
+ PINCTRL_PIN(87, "GPIO_87"),
+ PINCTRL_PIN(88, "GPIO_88"),
+ PINCTRL_PIN(89, "GPIO_89"),
+ PINCTRL_PIN(90, "GPIO_90"),
+ PINCTRL_PIN(91, "GPIO_91"),
+ PINCTRL_PIN(92, "GPIO_92"),
+ PINCTRL_PIN(93, "GPIO_93"),
+ PINCTRL_PIN(94, "GPIO_94"),
+ PINCTRL_PIN(95, "GPIO_95"),
+ PINCTRL_PIN(96, "GPIO_96"),
+ PINCTRL_PIN(97, "GPIO_97"),
+ PINCTRL_PIN(98, "GPIO_98"),
+ PINCTRL_PIN(99, "GPIO_99"),
+ PINCTRL_PIN(100, "GPIO_100"),
+ PINCTRL_PIN(101, "GPIO_101"),
+ PINCTRL_PIN(102, "GPIO_102"),
+ PINCTRL_PIN(103, "GPIO_103"),
+ PINCTRL_PIN(104, "GPIO_104"),
+ PINCTRL_PIN(105, "GPIO_105"),
+ PINCTRL_PIN(106, "GPIO_106"),
+ PINCTRL_PIN(107, "GPIO_107"),
+ PINCTRL_PIN(108, "GPIO_108"),
+ PINCTRL_PIN(109, "GPIO_109"),
+ PINCTRL_PIN(110, "GPIO_110"),
+ PINCTRL_PIN(111, "GPIO_111"),
+ PINCTRL_PIN(112, "GPIO_112"),
+ PINCTRL_PIN(113, "GPIO_113"),
+ PINCTRL_PIN(114, "GPIO_114"),
+ PINCTRL_PIN(115, "GPIO_115"),
+ PINCTRL_PIN(116, "GPIO_116"),
+ PINCTRL_PIN(117, "GPIO_117"),
+ PINCTRL_PIN(118, "GPIO_118"),
+ PINCTRL_PIN(119, "GPIO_119"),
+ PINCTRL_PIN(120, "GPIO_120"),
+ PINCTRL_PIN(121, "GPIO_121"),
+ PINCTRL_PIN(122, "GPIO_122"),
+ PINCTRL_PIN(123, "GPIO_123"),
+ PINCTRL_PIN(124, "GPIO_124"),
+ PINCTRL_PIN(125, "GPIO_125"),
+ PINCTRL_PIN(126, "GPIO_126"),
+ PINCTRL_PIN(127, "GPIO_127"),
+ PINCTRL_PIN(128, "GPIO_128"),
+ PINCTRL_PIN(129, "GPIO_129"),
+ PINCTRL_PIN(130, "GPIO_130"),
+ PINCTRL_PIN(131, "GPIO_131"),
+ PINCTRL_PIN(132, "GPIO_132"),
+ PINCTRL_PIN(133, "GPIO_133"),
+ PINCTRL_PIN(134, "GPIO_134"),
+ PINCTRL_PIN(135, "GPIO_135"),
+ PINCTRL_PIN(136, "GPIO_136"),
+ PINCTRL_PIN(137, "GPIO_137"),
+ PINCTRL_PIN(138, "GPIO_138"),
+ PINCTRL_PIN(139, "GPIO_139"),
+ PINCTRL_PIN(140, "GPIO_140"),
+ PINCTRL_PIN(141, "GPIO_141"),
+ PINCTRL_PIN(142, "GPIO_142"),
+ PINCTRL_PIN(143, "GPIO_143"),
+ PINCTRL_PIN(144, "GPIO_144"),
+ PINCTRL_PIN(145, "GPIO_145"),
+ PINCTRL_PIN(146, "GPIO_146"),
+ PINCTRL_PIN(147, "GPIO_147"),
+ PINCTRL_PIN(148, "GPIO_148"),
+ PINCTRL_PIN(149, "GPIO_149"),
+ PINCTRL_PIN(150, "GPIO_150"),
+ PINCTRL_PIN(151, "GPIO_151"),
+ PINCTRL_PIN(152, "GPIO_152"),
+ PINCTRL_PIN(153, "GPIO_153"),
+ PINCTRL_PIN(154, "GPIO_154"),
+ PINCTRL_PIN(155, "GPIO_155"),
+ PINCTRL_PIN(156, "GPIO_156"),
+ PINCTRL_PIN(157, "GPIO_157"),
+ PINCTRL_PIN(158, "GPIO_158"),
+ PINCTRL_PIN(159, "GPIO_159"),
+ PINCTRL_PIN(160, "GPIO_160"),
+ PINCTRL_PIN(161, "GPIO_161"),
+ PINCTRL_PIN(162, "GPIO_162"),
+ PINCTRL_PIN(163, "GPIO_163"),
+ PINCTRL_PIN(164, "GPIO_164"),
+ PINCTRL_PIN(165, "GPIO_165"),
+ PINCTRL_PIN(166, "GPIO_166"),
+ PINCTRL_PIN(167, "GPIO_167"),
+ PINCTRL_PIN(168, "GPIO_168"),
+ PINCTRL_PIN(169, "GPIO_169"),
+ PINCTRL_PIN(170, "GPIO_170"),
+ PINCTRL_PIN(171, "GPIO_171"),
+ PINCTRL_PIN(172, "GPIO_172"),
+ PINCTRL_PIN(173, "GPIO_173"),
+ PINCTRL_PIN(174, "GPIO_174"),
+ PINCTRL_PIN(175, "GPIO_175"),
+ PINCTRL_PIN(176, "GPIO_176"),
+ PINCTRL_PIN(177, "GPIO_177"),
+ PINCTRL_PIN(178, "GPIO_178"),
+ PINCTRL_PIN(179, "GPIO_179"),
+ PINCTRL_PIN(180, "GPIO_180"),
+ PINCTRL_PIN(181, "GPIO_181"),
+ PINCTRL_PIN(182, "GPIO_182"),
+ PINCTRL_PIN(183, "GPIO_183"),
+ PINCTRL_PIN(184, "GPIO_184"),
+ PINCTRL_PIN(185, "GPIO_185"),
+ PINCTRL_PIN(186, "GPIO_186"),
+ PINCTRL_PIN(187, "GPIO_187"),
+ PINCTRL_PIN(188, "GPIO_188"),
+ PINCTRL_PIN(189, "GPIO_189"),
+ PINCTRL_PIN(190, "UFS_RESET"),
+ PINCTRL_PIN(191, "SDC2_CLK"),
+ PINCTRL_PIN(192, "SDC2_CMD"),
+ PINCTRL_PIN(193, "SDC2_DATA"),
+};
+
+#define DECLARE_MSM_GPIO_PINS(pin) \
+ static const unsigned int gpio##pin##_pins[] = { pin }
+DECLARE_MSM_GPIO_PINS(0);
+DECLARE_MSM_GPIO_PINS(1);
+DECLARE_MSM_GPIO_PINS(2);
+DECLARE_MSM_GPIO_PINS(3);
+DECLARE_MSM_GPIO_PINS(4);
+DECLARE_MSM_GPIO_PINS(5);
+DECLARE_MSM_GPIO_PINS(6);
+DECLARE_MSM_GPIO_PINS(7);
+DECLARE_MSM_GPIO_PINS(8);
+DECLARE_MSM_GPIO_PINS(9);
+DECLARE_MSM_GPIO_PINS(10);
+DECLARE_MSM_GPIO_PINS(11);
+DECLARE_MSM_GPIO_PINS(12);
+DECLARE_MSM_GPIO_PINS(13);
+DECLARE_MSM_GPIO_PINS(14);
+DECLARE_MSM_GPIO_PINS(15);
+DECLARE_MSM_GPIO_PINS(16);
+DECLARE_MSM_GPIO_PINS(17);
+DECLARE_MSM_GPIO_PINS(18);
+DECLARE_MSM_GPIO_PINS(19);
+DECLARE_MSM_GPIO_PINS(20);
+DECLARE_MSM_GPIO_PINS(21);
+DECLARE_MSM_GPIO_PINS(22);
+DECLARE_MSM_GPIO_PINS(23);
+DECLARE_MSM_GPIO_PINS(24);
+DECLARE_MSM_GPIO_PINS(25);
+DECLARE_MSM_GPIO_PINS(26);
+DECLARE_MSM_GPIO_PINS(27);
+DECLARE_MSM_GPIO_PINS(28);
+DECLARE_MSM_GPIO_PINS(29);
+DECLARE_MSM_GPIO_PINS(30);
+DECLARE_MSM_GPIO_PINS(31);
+DECLARE_MSM_GPIO_PINS(32);
+DECLARE_MSM_GPIO_PINS(33);
+DECLARE_MSM_GPIO_PINS(34);
+DECLARE_MSM_GPIO_PINS(35);
+DECLARE_MSM_GPIO_PINS(36);
+DECLARE_MSM_GPIO_PINS(37);
+DECLARE_MSM_GPIO_PINS(38);
+DECLARE_MSM_GPIO_PINS(39);
+DECLARE_MSM_GPIO_PINS(40);
+DECLARE_MSM_GPIO_PINS(41);
+DECLARE_MSM_GPIO_PINS(42);
+DECLARE_MSM_GPIO_PINS(43);
+DECLARE_MSM_GPIO_PINS(44);
+DECLARE_MSM_GPIO_PINS(45);
+DECLARE_MSM_GPIO_PINS(46);
+DECLARE_MSM_GPIO_PINS(47);
+DECLARE_MSM_GPIO_PINS(48);
+DECLARE_MSM_GPIO_PINS(49);
+DECLARE_MSM_GPIO_PINS(50);
+DECLARE_MSM_GPIO_PINS(51);
+DECLARE_MSM_GPIO_PINS(52);
+DECLARE_MSM_GPIO_PINS(53);
+DECLARE_MSM_GPIO_PINS(54);
+DECLARE_MSM_GPIO_PINS(55);
+DECLARE_MSM_GPIO_PINS(56);
+DECLARE_MSM_GPIO_PINS(57);
+DECLARE_MSM_GPIO_PINS(58);
+DECLARE_MSM_GPIO_PINS(59);
+DECLARE_MSM_GPIO_PINS(60);
+DECLARE_MSM_GPIO_PINS(61);
+DECLARE_MSM_GPIO_PINS(62);
+DECLARE_MSM_GPIO_PINS(63);
+DECLARE_MSM_GPIO_PINS(64);
+DECLARE_MSM_GPIO_PINS(65);
+DECLARE_MSM_GPIO_PINS(66);
+DECLARE_MSM_GPIO_PINS(67);
+DECLARE_MSM_GPIO_PINS(68);
+DECLARE_MSM_GPIO_PINS(69);
+DECLARE_MSM_GPIO_PINS(70);
+DECLARE_MSM_GPIO_PINS(71);
+DECLARE_MSM_GPIO_PINS(72);
+DECLARE_MSM_GPIO_PINS(73);
+DECLARE_MSM_GPIO_PINS(74);
+DECLARE_MSM_GPIO_PINS(75);
+DECLARE_MSM_GPIO_PINS(76);
+DECLARE_MSM_GPIO_PINS(77);
+DECLARE_MSM_GPIO_PINS(78);
+DECLARE_MSM_GPIO_PINS(79);
+DECLARE_MSM_GPIO_PINS(80);
+DECLARE_MSM_GPIO_PINS(81);
+DECLARE_MSM_GPIO_PINS(82);
+DECLARE_MSM_GPIO_PINS(83);
+DECLARE_MSM_GPIO_PINS(84);
+DECLARE_MSM_GPIO_PINS(85);
+DECLARE_MSM_GPIO_PINS(86);
+DECLARE_MSM_GPIO_PINS(87);
+DECLARE_MSM_GPIO_PINS(88);
+DECLARE_MSM_GPIO_PINS(89);
+DECLARE_MSM_GPIO_PINS(90);
+DECLARE_MSM_GPIO_PINS(91);
+DECLARE_MSM_GPIO_PINS(92);
+DECLARE_MSM_GPIO_PINS(93);
+DECLARE_MSM_GPIO_PINS(94);
+DECLARE_MSM_GPIO_PINS(95);
+DECLARE_MSM_GPIO_PINS(96);
+DECLARE_MSM_GPIO_PINS(97);
+DECLARE_MSM_GPIO_PINS(98);
+DECLARE_MSM_GPIO_PINS(99);
+DECLARE_MSM_GPIO_PINS(100);
+DECLARE_MSM_GPIO_PINS(101);
+DECLARE_MSM_GPIO_PINS(102);
+DECLARE_MSM_GPIO_PINS(103);
+DECLARE_MSM_GPIO_PINS(104);
+DECLARE_MSM_GPIO_PINS(105);
+DECLARE_MSM_GPIO_PINS(106);
+DECLARE_MSM_GPIO_PINS(107);
+DECLARE_MSM_GPIO_PINS(108);
+DECLARE_MSM_GPIO_PINS(109);
+DECLARE_MSM_GPIO_PINS(110);
+DECLARE_MSM_GPIO_PINS(111);
+DECLARE_MSM_GPIO_PINS(112);
+DECLARE_MSM_GPIO_PINS(113);
+DECLARE_MSM_GPIO_PINS(114);
+DECLARE_MSM_GPIO_PINS(115);
+DECLARE_MSM_GPIO_PINS(116);
+DECLARE_MSM_GPIO_PINS(117);
+DECLARE_MSM_GPIO_PINS(118);
+DECLARE_MSM_GPIO_PINS(119);
+DECLARE_MSM_GPIO_PINS(120);
+DECLARE_MSM_GPIO_PINS(121);
+DECLARE_MSM_GPIO_PINS(122);
+DECLARE_MSM_GPIO_PINS(123);
+DECLARE_MSM_GPIO_PINS(124);
+DECLARE_MSM_GPIO_PINS(125);
+DECLARE_MSM_GPIO_PINS(126);
+DECLARE_MSM_GPIO_PINS(127);
+DECLARE_MSM_GPIO_PINS(128);
+DECLARE_MSM_GPIO_PINS(129);
+DECLARE_MSM_GPIO_PINS(130);
+DECLARE_MSM_GPIO_PINS(131);
+DECLARE_MSM_GPIO_PINS(132);
+DECLARE_MSM_GPIO_PINS(133);
+DECLARE_MSM_GPIO_PINS(134);
+DECLARE_MSM_GPIO_PINS(135);
+DECLARE_MSM_GPIO_PINS(136);
+DECLARE_MSM_GPIO_PINS(137);
+DECLARE_MSM_GPIO_PINS(138);
+DECLARE_MSM_GPIO_PINS(139);
+DECLARE_MSM_GPIO_PINS(140);
+DECLARE_MSM_GPIO_PINS(141);
+DECLARE_MSM_GPIO_PINS(142);
+DECLARE_MSM_GPIO_PINS(143);
+DECLARE_MSM_GPIO_PINS(144);
+DECLARE_MSM_GPIO_PINS(145);
+DECLARE_MSM_GPIO_PINS(146);
+DECLARE_MSM_GPIO_PINS(147);
+DECLARE_MSM_GPIO_PINS(148);
+DECLARE_MSM_GPIO_PINS(149);
+DECLARE_MSM_GPIO_PINS(150);
+DECLARE_MSM_GPIO_PINS(151);
+DECLARE_MSM_GPIO_PINS(152);
+DECLARE_MSM_GPIO_PINS(153);
+DECLARE_MSM_GPIO_PINS(154);
+DECLARE_MSM_GPIO_PINS(155);
+DECLARE_MSM_GPIO_PINS(156);
+DECLARE_MSM_GPIO_PINS(157);
+DECLARE_MSM_GPIO_PINS(158);
+DECLARE_MSM_GPIO_PINS(159);
+DECLARE_MSM_GPIO_PINS(160);
+DECLARE_MSM_GPIO_PINS(161);
+DECLARE_MSM_GPIO_PINS(162);
+DECLARE_MSM_GPIO_PINS(163);
+DECLARE_MSM_GPIO_PINS(164);
+DECLARE_MSM_GPIO_PINS(165);
+DECLARE_MSM_GPIO_PINS(166);
+DECLARE_MSM_GPIO_PINS(167);
+DECLARE_MSM_GPIO_PINS(168);
+DECLARE_MSM_GPIO_PINS(169);
+DECLARE_MSM_GPIO_PINS(170);
+DECLARE_MSM_GPIO_PINS(171);
+DECLARE_MSM_GPIO_PINS(172);
+DECLARE_MSM_GPIO_PINS(173);
+DECLARE_MSM_GPIO_PINS(174);
+DECLARE_MSM_GPIO_PINS(175);
+DECLARE_MSM_GPIO_PINS(176);
+DECLARE_MSM_GPIO_PINS(177);
+DECLARE_MSM_GPIO_PINS(178);
+DECLARE_MSM_GPIO_PINS(179);
+DECLARE_MSM_GPIO_PINS(180);
+DECLARE_MSM_GPIO_PINS(181);
+DECLARE_MSM_GPIO_PINS(182);
+DECLARE_MSM_GPIO_PINS(183);
+DECLARE_MSM_GPIO_PINS(184);
+DECLARE_MSM_GPIO_PINS(185);
+DECLARE_MSM_GPIO_PINS(186);
+DECLARE_MSM_GPIO_PINS(187);
+DECLARE_MSM_GPIO_PINS(188);
+DECLARE_MSM_GPIO_PINS(189);
+
+static const unsigned int sdc2_clk_pins[] = { 190 };
+static const unsigned int sdc2_cmd_pins[] = { 191 };
+static const unsigned int sdc2_data_pins[] = { 192 };
+static const unsigned int ufs_reset_pins[] = { 193 };
+
+enum sc8180x_functions {
+ msm_mux_adsp_ext,
+ msm_mux_agera_pll,
+ msm_mux_aoss_cti,
+ msm_mux_atest_char,
+ msm_mux_atest_tsens,
+ msm_mux_atest_tsens2,
+ msm_mux_atest_usb0,
+ msm_mux_atest_usb1,
+ msm_mux_atest_usb2,
+ msm_mux_atest_usb3,
+ msm_mux_atest_usb4,
+ msm_mux_audio_ref,
+ msm_mux_btfm_slimbus,
+ msm_mux_cam_mclk,
+ msm_mux_cci_async,
+ msm_mux_cci_i2c,
+ msm_mux_cci_timer0,
+ msm_mux_cci_timer1,
+ msm_mux_cci_timer2,
+ msm_mux_cci_timer3,
+ msm_mux_cci_timer4,
+ msm_mux_cci_timer5,
+ msm_mux_cci_timer6,
+ msm_mux_cci_timer7,
+ msm_mux_cci_timer8,
+ msm_mux_cci_timer9,
+ msm_mux_cri_trng,
+ msm_mux_dbg_out,
+ msm_mux_ddr_bist,
+ msm_mux_ddr_pxi,
+ msm_mux_debug_hot,
+ msm_mux_dp_hot,
+ msm_mux_edp_hot,
+ msm_mux_edp_lcd,
+ msm_mux_emac_phy,
+ msm_mux_emac_pps,
+ msm_mux_gcc_gp1,
+ msm_mux_gcc_gp2,
+ msm_mux_gcc_gp3,
+ msm_mux_gcc_gp4,
+ msm_mux_gcc_gp5,
+ msm_mux_gpio,
+ msm_mux_gps,
+ msm_mux_grfc,
+ msm_mux_hs1_mi2s,
+ msm_mux_hs2_mi2s,
+ msm_mux_hs3_mi2s,
+ msm_mux_jitter_bist,
+ msm_mux_lpass_slimbus,
+ msm_mux_m_voc,
+ msm_mux_mdp_vsync,
+ msm_mux_mdp_vsync0,
+ msm_mux_mdp_vsync1,
+ msm_mux_mdp_vsync2,
+ msm_mux_mdp_vsync3,
+ msm_mux_mdp_vsync4,
+ msm_mux_mdp_vsync5,
+ msm_mux_mss_lte,
+ msm_mux_nav_pps,
+ msm_mux_pa_indicator,
+ msm_mux_pci_e0,
+ msm_mux_pci_e1,
+ msm_mux_pci_e2,
+ msm_mux_pci_e3,
+ msm_mux_phase_flag,
+ msm_mux_pll_bist,
+ msm_mux_pll_bypassnl,
+ msm_mux_pll_reset,
+ msm_mux_pri_mi2s,
+ msm_mux_pri_mi2s_ws,
+ msm_mux_prng_rosc,
+ msm_mux_qdss_cti,
+ msm_mux_qdss_gpio,
+ msm_mux_qlink,
+ msm_mux_qspi0,
+ msm_mux_qspi0_clk,
+ msm_mux_qspi0_cs,
+ msm_mux_qspi1,
+ msm_mux_qspi1_clk,
+ msm_mux_qspi1_cs,
+ msm_mux_qua_mi2s,
+ msm_mux_qup0,
+ msm_mux_qup1,
+ msm_mux_qup2,
+ msm_mux_qup3,
+ msm_mux_qup4,
+ msm_mux_qup5,
+ msm_mux_qup6,
+ msm_mux_qup7,
+ msm_mux_qup8,
+ msm_mux_qup9,
+ msm_mux_qup10,
+ msm_mux_qup11,
+ msm_mux_qup12,
+ msm_mux_qup13,
+ msm_mux_qup14,
+ msm_mux_qup15,
+ msm_mux_qup16,
+ msm_mux_qup17,
+ msm_mux_qup18,
+ msm_mux_qup19,
+ msm_mux_qup_l4,
+ msm_mux_qup_l5,
+ msm_mux_qup_l6,
+ msm_mux_rgmii,
+ msm_mux_sd_write,
+ msm_mux_sdc4,
+ msm_mux_sdc4_clk,
+ msm_mux_sdc4_cmd,
+ msm_mux_sec_mi2s,
+ msm_mux_sp_cmu,
+ msm_mux_spkr_i2s,
+ msm_mux_ter_mi2s,
+ msm_mux_tgu,
+ msm_mux_tsense_pwm1,
+ msm_mux_tsense_pwm2,
+ msm_mux_tsif1,
+ msm_mux_tsif2,
+ msm_mux_uim1,
+ msm_mux_uim2,
+ msm_mux_uim_batt,
+ msm_mux_usb0_phy,
+ msm_mux_usb1_phy,
+ msm_mux_usb2phy_ac,
+ msm_mux_vfr_1,
+ msm_mux_vsense_trigger,
+ msm_mux_wlan1_adc,
+ msm_mux_wlan2_adc,
+ msm_mux_wmss_reset,
+ msm_mux__,
+};
+
+static const char * const adsp_ext_groups[] = {
+ "gpio115",
+};
+
+static const char * const agera_pll_groups[] = {
+ "gpio37",
+};
+
+static const char * const aoss_cti_groups[] = {
+ "gpio113",
+};
+
+static const char * const atest_char_groups[] = {
+ "gpio133", "gpio134", "gpio135", "gpio140", "gpio142",
+};
+
+static const char * const atest_tsens2_groups[] = {
+ "gpio62",
+};
+
+static const char * const atest_tsens_groups[] = {
+ "gpio93",
+};
+
+static const char * const atest_usb0_groups[] = {
+ "gpio90", "gpio91", "gpio92", "gpio93", "gpio94",
+};
+
+static const char * const atest_usb1_groups[] = {
+ "gpio60", "gpio62", "gpio63", "gpio64", "gpio65",
+};
+
+static const char * const atest_usb2_groups[] = {
+ "gpio34", "gpio95", "gpio102", "gpio121", "gpio122",
+};
+
+static const char * const atest_usb3_groups[] = {
+ "gpio68", "gpio71", "gpio72", "gpio73", "gpio74",
+};
+
+static const char * const atest_usb4_groups[] = {
+ "gpio75", "gpio76", "gpio77", "gpio78", "gpio88",
+};
+
+static const char * const audio_ref_groups[] = {
+ "gpio148",
+};
+
+static const char * const btfm_slimbus_groups[] = {
+ "gpio153", "gpio154",
+};
+
+static const char * const cam_mclk_groups[] = {
+ "gpio13", "gpio14", "gpio15", "gpio16", "gpio25", "gpio179", "gpio180",
+ "gpio181",
+};
+
+static const char * const cci_async_groups[] = {
+ "gpio24", "gpio25", "gpio26", "gpio176", "gpio185", "gpio186",
+};
+
+static const char * const cci_i2c_groups[] = {
+ "gpio0", "gpio1", "gpio2", "gpio3", "gpio17", "gpio18", "gpio19",
+ "gpio20", "gpio31", "gpio32", "gpio33", "gpio34", "gpio39", "gpio40",
+ "gpio41", "gpio42",
+};
+
+static const char * const cci_timer0_groups[] = {
+ "gpio21",
+};
+
+static const char * const cci_timer1_groups[] = {
+ "gpio22",
+};
+
+static const char * const cci_timer2_groups[] = {
+ "gpio23",
+};
+
+static const char * const cci_timer3_groups[] = {
+ "gpio24",
+};
+
+static const char * const cci_timer4_groups[] = {
+ "gpio178",
+};
+
+static const char * const cci_timer5_groups[] = {
+ "gpio182",
+};
+
+static const char * const cci_timer6_groups[] = {
+ "gpio183",
+};
+
+static const char * const cci_timer7_groups[] = {
+ "gpio184",
+};
+
+static const char * const cci_timer8_groups[] = {
+ "gpio185",
+};
+
+static const char * const cci_timer9_groups[] = {
+ "gpio186",
+};
+
+static const char * const cri_trng_groups[] = {
+ "gpio159",
+ "gpio160",
+ "gpio161",
+};
+
+static const char * const dbg_out_groups[] = {
+ "gpio34",
+};
+
+static const char * const ddr_bist_groups[] = {
+ "gpio98", "gpio99", "gpio145", "gpio146",
+};
+
+static const char * const ddr_pxi_groups[] = {
+ "gpio60", "gpio62", "gpio63", "gpio64", "gpio65", "gpio68", "gpio71",
+ "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77", "gpio78",
+ "gpio88", "gpio90",
+};
+
+static const char * const debug_hot_groups[] = {
+ "gpio7",
+};
+
+static const char * const dp_hot_groups[] = {
+ "gpio189",
+};
+
+static const char * const edp_hot_groups[] = {
+ "gpio10",
+};
+
+static const char * const edp_lcd_groups[] = {
+ "gpio11",
+};
+
+static const char * const emac_phy_groups[] = {
+ "gpio124",
+};
+
+static const char * const emac_pps_groups[] = {
+ "gpio81",
+};
+
+static const char * const gcc_gp1_groups[] = {
+ "gpio131", "gpio136",
+};
+
+static const char * const gcc_gp2_groups[] = {
+ "gpio21", "gpio137",
+};
+
+static const char * const gcc_gp3_groups[] = {
+ "gpio22", "gpio138",
+};
+
+static const char * const gcc_gp4_groups[] = {
+ "gpio139", "gpio182",
+};
+
+static const char * const gcc_gp5_groups[] = {
+ "gpio140", "gpio183",
+};
+
+static const char * const gpio_groups[] = {
+ "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7",
+ "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio12", "gpio13",
+ "gpio14", "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20",
+ "gpio21", "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27",
+ "gpio28", "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34",
+ "gpio35", "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41",
+ "gpio42", "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48",
+ "gpio49", "gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55",
+ "gpio56", "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62",
+ "gpio63", "gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69",
+ "gpio70", "gpio71", "gpio72", "gpio73", "gpio74", "gpio75", "gpio76",
+ "gpio77", "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83",
+ "gpio84", "gpio85", "gpio86", "gpio87", "gpio88", "gpio89", "gpio90",
+ "gpio91", "gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97",
+ "gpio98", "gpio99", "gpio100", "gpio101", "gpio102", "gpio103",
+ "gpio104", "gpio105", "gpio106", "gpio107", "gpio108", "gpio109",
+ "gpio110", "gpio111", "gpio112", "gpio113", "gpio114", "gpio115",
+ "gpio116", "gpio117", "gpio118", "gpio119", "gpio120", "gpio121",
+ "gpio122", "gpio123", "gpio124", "gpio125", "gpio126", "gpio127",
+ "gpio128", "gpio129", "gpio130", "gpio131", "gpio132", "gpio133",
+ "gpio134", "gpio135", "gpio136", "gpio137", "gpio138", "gpio139",
+ "gpio140", "gpio141", "gpio142", "gpio143", "gpio144", "gpio145",
+ "gpio146", "gpio147", "gpio148", "gpio149", "gpio150", "gpio151",
+ "gpio152", "gpio153", "gpio154", "gpio155", "gpio156", "gpio157",
+ "gpio158", "gpio159", "gpio160", "gpio161", "gpio162", "gpio163",
+ "gpio164", "gpio165", "gpio166", "gpio167", "gpio168", "gpio169",
+ "gpio170", "gpio171", "gpio172", "gpio173", "gpio174", "gpio175",
+ "gpio176", "gpio177", "gpio177", "gpio178", "gpio179", "gpio180",
+ "gpio181", "gpio182", "gpio183", "gpio184", "gpio185", "gpio186",
+ "gpio186", "gpio187", "gpio187", "gpio188", "gpio188", "gpio189",
+};
+
+static const char * const gps_groups[] = {
+ "gpio60", "gpio76", "gpio77", "gpio81", "gpio82",
+};
+
+static const char * const grfc_groups[] = {
+ "gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio71", "gpio72",
+ "gpio73", "gpio74", "gpio75", "gpio76", "gpio77", "gpio78", "gpio79",
+ "gpio80", "gpio81", "gpio82",
+};
+
+static const char * const hs1_mi2s_groups[] = {
+ "gpio155", "gpio156", "gpio157", "gpio158", "gpio159",
+};
+
+static const char * const hs2_mi2s_groups[] = {
+ "gpio160", "gpio161", "gpio162", "gpio163", "gpio164",
+};
+
+static const char * const hs3_mi2s_groups[] = {
+ "gpio125", "gpio165", "gpio166", "gpio167", "gpio168",
+};
+
+static const char * const jitter_bist_groups[] = {
+ "gpio129",
+};
+
+static const char * const lpass_slimbus_groups[] = {
+ "gpio149", "gpio150", "gpio151", "gpio152",
+};
+
+static const char * const m_voc_groups[] = {
+ "gpio10",
+};
+
+static const char * const mdp_vsync0_groups[] = {
+ "gpio89",
+};
+
+static const char * const mdp_vsync1_groups[] = {
+ "gpio89",
+};
+
+static const char * const mdp_vsync2_groups[] = {
+ "gpio89",
+};
+
+static const char * const mdp_vsync3_groups[] = {
+ "gpio89",
+};
+
+static const char * const mdp_vsync4_groups[] = {
+ "gpio89",
+};
+
+static const char * const mdp_vsync5_groups[] = {
+ "gpio89",
+};
+
+static const char * const mdp_vsync_groups[] = {
+ "gpio8", "gpio9", "gpio10", "gpio60", "gpio82",
+};
+
+static const char * const mss_lte_groups[] = {
+ "gpio69", "gpio70",
+};
+
+static const char * const nav_pps_groups[] = {
+ "gpio60", "gpio60", "gpio76", "gpio76", "gpio77", "gpio77", "gpio81",
+ "gpio81", "gpio82", "gpio82",
+};
+
+static const char * const pa_indicator_groups[] = {
+ "gpio68",
+};
+
+static const char * const pci_e0_groups[] = {
+ "gpio35", "gpio36",
+};
+
+static const char * const pci_e1_groups[] = {
+ "gpio102", "gpio103",
+};
+
+static const char * const pci_e2_groups[] = {
+ "gpio175", "gpio176",
+};
+
+static const char * const pci_e3_groups[] = {
+ "gpio178", "gpio179",
+};
+
+static const char * const phase_flag_groups[] = {
+ "gpio4", "gpio5", "gpio6", "gpio7", "gpio33", "gpio53", "gpio54",
+ "gpio102", "gpio120", "gpio121", "gpio122", "gpio123", "gpio125",
+ "gpio148", "gpio149", "gpio150", "gpio151", "gpio152", "gpio155",
+ "gpio156", "gpio157", "gpio158", "gpio159", "gpio160", "gpio161",
+ "gpio162", "gpio163", "gpio164", "gpio165", "gpio166", "gpio167",
+ "gpio168",
+};
+
+static const char * const pll_bist_groups[] = {
+ "gpio130",
+};
+
+static const char * const pll_bypassnl_groups[] = {
+ "gpio100",
+};
+
+static const char * const pll_reset_groups[] = {
+ "gpio101",
+};
+
+static const char * const pri_mi2s_groups[] = {
+ "gpio143", "gpio144", "gpio146", "gpio147",
+};
+
+static const char * const pri_mi2s_ws_groups[] = {
+ "gpio145",
+};
+
+static const char * const prng_rosc_groups[] = {
+ "gpio163",
+};
+
+static const char * const qdss_cti_groups[] = {
+ "gpio49", "gpio50", "gpio81", "gpio82", "gpio89", "gpio90", "gpio141",
+ "gpio142",
+};
+
+static const char * const qdss_gpio_groups[] = {
+ "gpio13", "gpio14", "gpio15", "gpio16", "gpio17", "gpio18", "gpio19",
+ "gpio20", "gpio21", "gpio22", "gpio23", "gpio24", "gpio25", "gpio26",
+ "gpio27", "gpio28", "gpio29", "gpio30", "gpio39", "gpio40", "gpio41",
+ "gpio42", "gpio92", "gpio114", "gpio115", "gpio116", "gpio117",
+ "gpio118", "gpio119", "gpio120", "gpio121", "gpio130", "gpio132",
+ "gpio133", "gpio134", "gpio135",
+};
+
+static const char * const qlink_groups[] = {
+ "gpio61", "gpio62",
+};
+
+static const char * const qspi0_groups[] = {
+ "gpio89", "gpio90", "gpio91", "gpio93",
+};
+
+static const char * const qspi0_clk_groups[] = {
+ "gpio92",
+};
+
+static const char * const qspi0_cs_groups[] = {
+ "gpio88", "gpio94",
+};
+
+static const char * const qspi1_groups[] = {
+ "gpio56", "gpio57", "gpio161", "gpio162",
+};
+
+static const char * const qspi1_clk_groups[] = {
+ "gpio163",
+};
+
+static const char * const qspi1_cs_groups[] = {
+ "gpio55", "gpio164",
+};
+
+static const char * const qua_mi2s_groups[] = {
+ "gpio136", "gpio137", "gpio138", "gpio139", "gpio140", "gpio141",
+ "gpio142",
+};
+
+static const char * const qup0_groups[] = {
+ "gpio0", "gpio1", "gpio2", "gpio3",
+};
+
+static const char * const qup10_groups[] = {
+ "gpio9", "gpio10", "gpio11", "gpio12",
+};
+
+static const char * const qup11_groups[] = {
+ "gpio92", "gpio93", "gpio94", "gpio95",
+};
+
+static const char * const qup12_groups[] = {
+ "gpio83", "gpio84", "gpio85", "gpio86",
+};
+
+static const char * const qup13_groups[] = {
+ "gpio43", "gpio44", "gpio45", "gpio46",
+};
+
+static const char * const qup14_groups[] = {
+ "gpio47", "gpio48", "gpio49", "gpio50",
+};
+
+static const char * const qup15_groups[] = {
+ "gpio27", "gpio28", "gpio29", "gpio30",
+};
+
+static const char * const qup16_groups[] = {
+ "gpio83", "gpio84", "gpio85", "gpio86",
+};
+
+static const char * const qup17_groups[] = {
+ "gpio55", "gpio56", "gpio57", "gpio58",
+};
+
+static const char * const qup18_groups[] = {
+ "gpio23", "gpio24", "gpio25", "gpio26",
+};
+
+static const char * const qup19_groups[] = {
+ "gpio181", "gpio182", "gpio183", "gpio184",
+};
+
+static const char * const qup1_groups[] = {
+ "gpio114", "gpio115", "gpio116", "gpio117",
+};
+
+static const char * const qup2_groups[] = {
+ "gpio126", "gpio127", "gpio128", "gpio129",
+};
+
+static const char * const qup3_groups[] = {
+ "gpio144", "gpio145", "gpio146", "gpio147",
+};
+
+static const char * const qup4_groups[] = {
+ "gpio51", "gpio52", "gpio53", "gpio54",
+};
+
+static const char * const qup5_groups[] = {
+ "gpio119", "gpio120", "gpio121", "gpio122",
+};
+
+static const char * const qup6_groups[] = {
+ "gpio4", "gpio5", "gpio6", "gpio7",
+};
+
+static const char * const qup7_groups[] = {
+ "gpio98", "gpio99", "gpio100", "gpio101",
+};
+
+static const char * const qup8_groups[] = {
+ "gpio88", "gpio89", "gpio90", "gpio91",
+};
+
+static const char * const qup9_groups[] = {
+ "gpio39", "gpio40", "gpio41", "gpio42",
+};
+
+static const char * const qup_l4_groups[] = {
+ "gpio35", "gpio59", "gpio60", "gpio95",
+};
+
+static const char * const qup_l5_groups[] = {
+ "gpio7", "gpio33", "gpio36", "gpio96",
+};
+
+static const char * const qup_l6_groups[] = {
+ "gpio6", "gpio34", "gpio37", "gpio97",
+};
+
+static const char * const rgmii_groups[] = {
+ "gpio4", "gpio5", "gpio6", "gpio7", "gpio59", "gpio114", "gpio115",
+ "gpio116", "gpio117", "gpio118", "gpio119", "gpio120", "gpio121",
+ "gpio122",
+};
+
+static const char * const sd_write_groups[] = {
+ "gpio97",
+};
+
+static const char * const sdc4_groups[] = {
+ "gpio91", "gpio93", "gpio94", "gpio95",
+};
+
+static const char * const sdc4_clk_groups[] = {
+ "gpio92",
+};
+
+static const char * const sdc4_cmd_groups[] = {
+ "gpio90",
+};
+
+static const char * const sec_mi2s_groups[] = {
+ "gpio126", "gpio127", "gpio128", "gpio129", "gpio130",
+};
+
+static const char * const sp_cmu_groups[] = {
+ "gpio162",
+};
+
+static const char * const spkr_i2s_groups[] = {
+ "gpio148", "gpio149", "gpio150", "gpio151", "gpio152",
+};
+
+static const char * const ter_mi2s_groups[] = {
+ "gpio131", "gpio132", "gpio133", "gpio134", "gpio135",
+};
+
+static const char * const tgu_groups[] = {
+ "gpio89", "gpio90", "gpio91", "gpio88", "gpio74", "gpio77", "gpio76",
+ "gpio75",
+};
+
+static const char * const tsense_pwm1_groups[] = {
+ "gpio150",
+};
+
+static const char * const tsense_pwm2_groups[] = {
+ "gpio150",
+};
+
+static const char * const tsif1_groups[] = {
+ "gpio88", "gpio89", "gpio90", "gpio91", "gpio97",
+};
+
+static const char * const tsif2_groups[] = {
+ "gpio92", "gpio93", "gpio94", "gpio95", "gpio96",
+};
+
+static const char * const uim1_groups[] = {
+ "gpio109", "gpio110", "gpio111", "gpio112",
+};
+
+static const char * const uim2_groups[] = {
+ "gpio105", "gpio106", "gpio107", "gpio108",
+};
+
+static const char * const uim_batt_groups[] = {
+ "gpio113",
+};
+
+static const char * const usb0_phy_groups[] = {
+ "gpio38",
+};
+
+static const char * const usb1_phy_groups[] = {
+ "gpio58",
+};
+
+static const char * const usb2phy_ac_groups[] = {
+ "gpio47", "gpio48", "gpio113", "gpio123",
+};
+
+static const char * const vfr_1_groups[] = {
+ "gpio91",
+};
+
+static const char * const vsense_trigger_groups[] = {
+ "gpio62",
+};
+
+static const char * const wlan1_adc_groups[] = {
+ "gpio64", "gpio63",
+};
+
+static const char * const wlan2_adc_groups[] = {
+ "gpio68", "gpio65",
+};
+
+static const char * const wmss_reset_groups[] = {
+ "gpio63",
+};
+
+static const struct msm_function sc8180x_functions[] = {
+ FUNCTION(adsp_ext),
+ FUNCTION(agera_pll),
+ FUNCTION(aoss_cti),
+ FUNCTION(atest_char),
+ FUNCTION(atest_tsens),
+ FUNCTION(atest_tsens2),
+ FUNCTION(atest_usb0),
+ FUNCTION(atest_usb1),
+ FUNCTION(atest_usb2),
+ FUNCTION(atest_usb3),
+ FUNCTION(atest_usb4),
+ FUNCTION(audio_ref),
+ FUNCTION(btfm_slimbus),
+ FUNCTION(cam_mclk),
+ FUNCTION(cci_async),
+ FUNCTION(cci_i2c),
+ FUNCTION(cci_timer0),
+ FUNCTION(cci_timer1),
+ FUNCTION(cci_timer2),
+ FUNCTION(cci_timer3),
+ FUNCTION(cci_timer4),
+ FUNCTION(cci_timer5),
+ FUNCTION(cci_timer6),
+ FUNCTION(cci_timer7),
+ FUNCTION(cci_timer8),
+ FUNCTION(cci_timer9),
+ FUNCTION(cri_trng),
+ FUNCTION(dbg_out),
+ FUNCTION(ddr_bist),
+ FUNCTION(ddr_pxi),
+ FUNCTION(debug_hot),
+ FUNCTION(dp_hot),
+ FUNCTION(edp_hot),
+ FUNCTION(edp_lcd),
+ FUNCTION(emac_phy),
+ FUNCTION(emac_pps),
+ FUNCTION(gcc_gp1),
+ FUNCTION(gcc_gp2),
+ FUNCTION(gcc_gp3),
+ FUNCTION(gcc_gp4),
+ FUNCTION(gcc_gp5),
+ FUNCTION(gpio),
+ FUNCTION(gps),
+ FUNCTION(grfc),
+ FUNCTION(hs1_mi2s),
+ FUNCTION(hs2_mi2s),
+ FUNCTION(hs3_mi2s),
+ FUNCTION(jitter_bist),
+ FUNCTION(lpass_slimbus),
+ FUNCTION(m_voc),
+ FUNCTION(mdp_vsync),
+ FUNCTION(mdp_vsync0),
+ FUNCTION(mdp_vsync1),
+ FUNCTION(mdp_vsync2),
+ FUNCTION(mdp_vsync3),
+ FUNCTION(mdp_vsync4),
+ FUNCTION(mdp_vsync5),
+ FUNCTION(mss_lte),
+ FUNCTION(nav_pps),
+ FUNCTION(pa_indicator),
+ FUNCTION(pci_e0),
+ FUNCTION(pci_e1),
+ FUNCTION(pci_e2),
+ FUNCTION(pci_e3),
+ FUNCTION(phase_flag),
+ FUNCTION(pll_bist),
+ FUNCTION(pll_bypassnl),
+ FUNCTION(pll_reset),
+ FUNCTION(pri_mi2s),
+ FUNCTION(pri_mi2s_ws),
+ FUNCTION(prng_rosc),
+ FUNCTION(qdss_cti),
+ FUNCTION(qdss_gpio),
+ FUNCTION(qlink),
+ FUNCTION(qspi0),
+ FUNCTION(qspi0_clk),
+ FUNCTION(qspi0_cs),
+ FUNCTION(qspi1),
+ FUNCTION(qspi1_clk),
+ FUNCTION(qspi1_cs),
+ FUNCTION(qua_mi2s),
+ FUNCTION(qup0),
+ FUNCTION(qup1),
+ FUNCTION(qup2),
+ FUNCTION(qup3),
+ FUNCTION(qup4),
+ FUNCTION(qup5),
+ FUNCTION(qup6),
+ FUNCTION(qup7),
+ FUNCTION(qup8),
+ FUNCTION(qup9),
+ FUNCTION(qup10),
+ FUNCTION(qup11),
+ FUNCTION(qup12),
+ FUNCTION(qup13),
+ FUNCTION(qup14),
+ FUNCTION(qup15),
+ FUNCTION(qup16),
+ FUNCTION(qup17),
+ FUNCTION(qup18),
+ FUNCTION(qup19),
+ FUNCTION(qup_l4),
+ FUNCTION(qup_l5),
+ FUNCTION(qup_l6),
+ FUNCTION(rgmii),
+ FUNCTION(sd_write),
+ FUNCTION(sdc4),
+ FUNCTION(sdc4_clk),
+ FUNCTION(sdc4_cmd),
+ FUNCTION(sec_mi2s),
+ FUNCTION(sp_cmu),
+ FUNCTION(spkr_i2s),
+ FUNCTION(ter_mi2s),
+ FUNCTION(tgu),
+ FUNCTION(tsense_pwm1),
+ FUNCTION(tsense_pwm2),
+ FUNCTION(tsif1),
+ FUNCTION(tsif2),
+ FUNCTION(uim1),
+ FUNCTION(uim2),
+ FUNCTION(uim_batt),
+ FUNCTION(usb0_phy),
+ FUNCTION(usb1_phy),
+ FUNCTION(usb2phy_ac),
+ FUNCTION(vfr_1),
+ FUNCTION(vsense_trigger),
+ FUNCTION(wlan1_adc),
+ FUNCTION(wlan2_adc),
+ FUNCTION(wmss_reset),
+};
+
+/* Every pin is maintained as a single group, and missing or non-existing pin
+ * would be maintained as dummy group to synchronize pin group index with
+ * pin descriptor registered with pinctrl core.
+ * Clients would not be able to request these dummy pin groups.
+ */
+static const struct msm_pingroup sc8180x_groups[] = {
+ [0] = PINGROUP(0, WEST, qup0, cci_i2c, _, _, _, _, _, _, _),
+ [1] = PINGROUP(1, WEST, qup0, cci_i2c, _, _, _, _, _, _, _),
+ [2] = PINGROUP(2, WEST, qup0, cci_i2c, _, _, _, _, _, _, _),
+ [3] = PINGROUP(3, WEST, qup0, cci_i2c, _, _, _, _, _, _, _),
+ [4] = PINGROUP(4, WEST, qup6, rgmii, _, phase_flag, _, _, _, _, _),
+ [5] = PINGROUP(5, WEST, qup6, rgmii, _, phase_flag, _, _, _, _, _),
+ [6] = PINGROUP(6, WEST, qup6, rgmii, qup_l6, _, phase_flag, _, _, _, _),
+ [7] = PINGROUP(7, WEST, qup6, debug_hot, rgmii, qup_l5, _, phase_flag, _, _, _),
+ [8] = PINGROUP(8, EAST, mdp_vsync, _, _, _, _, _, _, _, _),
+ [9] = PINGROUP(9, EAST, mdp_vsync, qup10, _, _, _, _, _, _, _),
+ [10] = PINGROUP(10, EAST, edp_hot, m_voc, mdp_vsync, qup10, _, _, _, _, _),
+ [11] = PINGROUP(11, EAST, edp_lcd, qup10, _, _, _, _, _, _, _),
+ [12] = PINGROUP(12, EAST, qup10, _, _, _, _, _, _, _, _),
+ [13] = PINGROUP(13, EAST, cam_mclk, qdss_gpio, _, _, _, _, _, _, _),
+ [14] = PINGROUP(14, EAST, cam_mclk, qdss_gpio, _, _, _, _, _, _, _),
+ [15] = PINGROUP(15, EAST, cam_mclk, qdss_gpio, _, _, _, _, _, _, _),
+ [16] = PINGROUP(16, EAST, cam_mclk, qdss_gpio, _, _, _, _, _, _, _),
+ [17] = PINGROUP(17, EAST, cci_i2c, qdss_gpio, _, _, _, _, _, _, _),
+ [18] = PINGROUP(18, EAST, cci_i2c, qdss_gpio, _, _, _, _, _, _, _),
+ [19] = PINGROUP(19, EAST, cci_i2c, qdss_gpio, _, _, _, _, _, _, _),
+ [20] = PINGROUP(20, EAST, cci_i2c, qdss_gpio, _, _, _, _, _, _, _),
+ [21] = PINGROUP(21, EAST, cci_timer0, gcc_gp2, qdss_gpio, _, _, _, _, _, _),
+ [22] = PINGROUP(22, EAST, cci_timer1, gcc_gp3, qdss_gpio, _, _, _, _, _, _),
+ [23] = PINGROUP(23, EAST, cci_timer2, qup18, qdss_gpio, _, _, _, _, _, _),
+ [24] = PINGROUP(24, EAST, cci_timer3, cci_async, qup18, qdss_gpio, _, _, _, _, _),
+ [25] = PINGROUP(25, EAST, cam_mclk, cci_async, qup18, qdss_gpio, _, _, _, _, _),
+ [26] = PINGROUP(26, EAST, cci_async, qup18, qdss_gpio, _, _, _, _, _, _),
+ [27] = PINGROUP(27, EAST, qup15, _, qdss_gpio, _, _, _, _, _, _),
+ [28] = PINGROUP(28, EAST, qup15, qdss_gpio, _, _, _, _, _, _, _),
+ [29] = PINGROUP(29, EAST, qup15, qdss_gpio, _, _, _, _, _, _, _),
+ [30] = PINGROUP(30, EAST, qup15, qdss_gpio, _, _, _, _, _, _, _),
+ [31] = PINGROUP(31, EAST, cci_i2c, _, _, _, _, _, _, _, _),
+ [32] = PINGROUP(32, EAST, cci_i2c, _, _, _, _, _, _, _, _),
+ [33] = PINGROUP(33, EAST, cci_i2c, qup_l5, _, phase_flag, _, _, _, _, _),
+ [34] = PINGROUP(34, EAST, cci_i2c, qup_l6, dbg_out, atest_usb2, _, _, _, _, _),
+ [35] = PINGROUP(35, SOUTH, pci_e0, qup_l4, _, _, _, _, _, _, _),
+ [36] = PINGROUP(36, SOUTH, pci_e0, qup_l5, _, _, _, _, _, _, _),
+ [37] = PINGROUP(37, SOUTH, qup_l6, agera_pll, _, _, _, _, _, _, _),
+ [38] = PINGROUP(38, SOUTH, usb0_phy, _, _, _, _, _, _, _, _),
+ [39] = PINGROUP(39, EAST, qup9, cci_i2c, qdss_gpio, _, _, _, _, _, _),
+ [40] = PINGROUP(40, EAST, qup9, cci_i2c, qdss_gpio, _, _, _, _, _, _),
+ [41] = PINGROUP(41, EAST, qup9, cci_i2c, qdss_gpio, _, _, _, _, _, _),
+ [42] = PINGROUP(42, EAST, qup9, cci_i2c, qdss_gpio, _, _, _, _, _, _),
+ [43] = PINGROUP(43, EAST, qup13, _, _, _, _, _, _, _, _),
+ [44] = PINGROUP(44, EAST, qup13, _, _, _, _, _, _, _, _),
+ [45] = PINGROUP(45, EAST, qup13, _, _, _, _, _, _, _, _),
+ [46] = PINGROUP(46, EAST, qup13, _, _, _, _, _, _, _, _),
+ [47] = PINGROUP(47, EAST, qup14, usb2phy_ac, _, _, _, _, _, _, _),
+ [48] = PINGROUP(48, EAST, qup14, usb2phy_ac, _, _, _, _, _, _, _),
+ [49] = PINGROUP(49, EAST, qup14, qdss_cti, _, _, _, _, _, _, _),
+ [50] = PINGROUP(50, EAST, qup14, qdss_cti, _, _, _, _, _, _, _),
+ [51] = PINGROUP(51, WEST, qup4, _, _, _, _, _, _, _, _),
+ [52] = PINGROUP(52, WEST, qup4, _, _, _, _, _, _, _, _),
+ [53] = PINGROUP(53, WEST, qup4, _, phase_flag, _, _, _, _, _, _),
+ [54] = PINGROUP(54, WEST, qup4, _, _, phase_flag, _, _, _, _, _),
+ [55] = PINGROUP(55, WEST, qup17, qspi1_cs, _, _, _, _, _, _, _),
+ [56] = PINGROUP(56, WEST, qup17, qspi1, _, _, _, _, _, _, _),
+ [57] = PINGROUP(57, WEST, qup17, qspi1, _, _, _, _, _, _, _),
+ [58] = PINGROUP(58, WEST, usb1_phy, qup17, _, _, _, _, _, _, _),
+ [59] = PINGROUP(59, WEST, rgmii, qup_l4, _, _, _, _, _, _, _),
+ [60] = PINGROUP(60, EAST, gps, nav_pps, nav_pps, qup_l4, mdp_vsync, atest_usb1, ddr_pxi, _, _),
+ [61] = PINGROUP(61, EAST, qlink, _, _, _, _, _, _, _, _),
+ [62] = PINGROUP(62, EAST, qlink, atest_tsens2, atest_usb1, ddr_pxi, vsense_trigger, _, _, _, _),
+ [63] = PINGROUP(63, EAST, wmss_reset, _, atest_usb1, ddr_pxi, wlan1_adc, _, _, _, _),
+ [64] = PINGROUP(64, EAST, grfc, _, atest_usb1, ddr_pxi, wlan1_adc, _, _, _, _),
+ [65] = PINGROUP(65, EAST, grfc, atest_usb1, ddr_pxi, wlan2_adc, _, _, _, _, _),
+ [66] = PINGROUP(66, EAST, grfc, _, _, _, _, _, _, _, _),
+ [67] = PINGROUP(67, EAST, grfc, _, _, _, _, _, _, _, _),
+ [68] = PINGROUP(68, EAST, grfc, pa_indicator, atest_usb3, ddr_pxi, wlan2_adc, _, _, _, _),
+ [69] = PINGROUP(69, EAST, mss_lte, _, _, _, _, _, _, _, _),
+ [70] = PINGROUP(70, EAST, mss_lte, _, _, _, _, _, _, _, _),
+ [71] = PINGROUP(71, EAST, _, grfc, atest_usb3, ddr_pxi, _, _, _, _, _),
+ [72] = PINGROUP(72, EAST, _, grfc, atest_usb3, ddr_pxi, _, _, _, _, _),
+ [73] = PINGROUP(73, EAST, _, grfc, atest_usb3, ddr_pxi, _, _, _, _, _),
+ [74] = PINGROUP(74, EAST, _, grfc, tgu, atest_usb3, ddr_pxi, _, _, _, _),
+ [75] = PINGROUP(75, EAST, _, grfc, tgu, atest_usb4, ddr_pxi, _, _, _, _),
+ [76] = PINGROUP(76, EAST, _, grfc, gps, nav_pps, nav_pps, tgu, atest_usb4, ddr_pxi, _),
+ [77] = PINGROUP(77, EAST, _, grfc, gps, nav_pps, nav_pps, tgu, atest_usb4, ddr_pxi, _),
+ [78] = PINGROUP(78, EAST, _, grfc, _, atest_usb4, ddr_pxi, _, _, _, _),
+ [79] = PINGROUP(79, EAST, _, grfc, _, _, _, _, _, _, _),
+ [80] = PINGROUP(80, EAST, _, grfc, _, _, _, _, _, _, _),
+ [81] = PINGROUP(81, EAST, _, grfc, gps, nav_pps, nav_pps, qdss_cti, _, emac_pps, _),
+ [82] = PINGROUP(82, EAST, _, grfc, gps, nav_pps, nav_pps, mdp_vsync, qdss_cti, _, _),
+ [83] = PINGROUP(83, EAST, qup12, qup16, _, _, _, _, _, _, _),
+ [84] = PINGROUP(84, EAST, qup12, qup16, _, _, _, _, _, _, _),
+ [85] = PINGROUP(85, EAST, qup12, qup16, _, _, _, _, _, _, _),
+ [86] = PINGROUP(86, EAST, qup12, qup16, _, _, _, _, _, _, _),
+ [87] = PINGROUP(87, SOUTH, _, _, _, _, _, _, _, _, _),
+ [88] = PINGROUP(88, EAST, tsif1, qup8, qspi0_cs, tgu, atest_usb4, ddr_pxi, _, _, _),
+ [89] = PINGROUP(89, EAST, tsif1, qup8, qspi0, mdp_vsync0, mdp_vsync1, mdp_vsync2, mdp_vsync3, mdp_vsync4, mdp_vsync5),
+ [90] = PINGROUP(90, EAST, tsif1, qup8, qspi0, sdc4_cmd, tgu, qdss_cti, atest_usb0, ddr_pxi, _),
+ [91] = PINGROUP(91, EAST, tsif1, qup8, qspi0, sdc4, vfr_1, tgu, atest_usb0, _, _),
+ [92] = PINGROUP(92, EAST, tsif2, qup11, qspi0_clk, sdc4_clk, qdss_gpio, atest_usb0, _, _, _),
+ [93] = PINGROUP(93, EAST, tsif2, qup11, qspi0, sdc4, atest_tsens, atest_usb0, _, _, _),
+ [94] = PINGROUP(94, EAST, tsif2, qup11, qspi0_cs, sdc4, _, atest_usb0, _, _, _),
+ [95] = PINGROUP(95, EAST, tsif2, qup11, sdc4, qup_l4, atest_usb2, _, _, _, _),
+ [96] = PINGROUP(96, WEST, tsif2, qup_l5, _, _, _, _, _, _, _),
+ [97] = PINGROUP(97, WEST, sd_write, tsif1, qup_l6, _, _, _, _, _, _),
+ [98] = PINGROUP(98, WEST, qup7, ddr_bist, _, _, _, _, _, _, _),
+ [99] = PINGROUP(99, WEST, qup7, ddr_bist, _, _, _, _, _, _, _),
+ [100] = PINGROUP(100, WEST, qup7, pll_bypassnl, _, _, _, _, _, _, _),
+ [101] = PINGROUP(101, WEST, qup7, pll_reset, _, _, _, _, _, _, _),
+ [102] = PINGROUP(102, SOUTH, pci_e1, _, phase_flag, atest_usb2, _, _, _, _, _),
+ [103] = PINGROUP(103, SOUTH, pci_e1, _, _, _, _, _, _, _, _),
+ [104] = PINGROUP(104, SOUTH, _, _, _, _, _, _, _, _, _),
+ [105] = PINGROUP(105, WEST, uim2, _, _, _, _, _, _, _, _),
+ [106] = PINGROUP(106, WEST, uim2, _, _, _, _, _, _, _, _),
+ [107] = PINGROUP(107, WEST, uim2, _, _, _, _, _, _, _, _),
+ [108] = PINGROUP(108, WEST, uim2, _, _, _, _, _, _, _, _),
+ [109] = PINGROUP(109, WEST, uim1, _, _, _, _, _, _, _, _),
+ [110] = PINGROUP(110, WEST, uim1, _, _, _, _, _, _, _, _),
+ [111] = PINGROUP(111, WEST, uim1, _, _, _, _, _, _, _, _),
+ [112] = PINGROUP(112, WEST, uim1, _, _, _, _, _, _, _, _),
+ [113] = PINGROUP(113, WEST, uim_batt, usb2phy_ac, aoss_cti, _, _, _, _, _, _),
+ [114] = PINGROUP(114, WEST, qup1, rgmii, _, qdss_gpio, _, _, _, _, _),
+ [115] = PINGROUP(115, WEST, qup1, rgmii, adsp_ext, _, qdss_gpio, _, _, _, _),
+ [116] = PINGROUP(116, WEST, qup1, rgmii, _, qdss_gpio, _, _, _, _, _),
+ [117] = PINGROUP(117, WEST, qup1, rgmii, _, qdss_gpio, _, _, _, _, _),
+ [118] = PINGROUP(118, WEST, rgmii, _, qdss_gpio, _, _, _, _, _, _),
+ [119] = PINGROUP(119, WEST, qup5, rgmii, _, qdss_gpio, _, _, _, _, _),
+ [120] = PINGROUP(120, WEST, qup5, rgmii, _, phase_flag, qdss_gpio, _, _, _, _),
+ [121] = PINGROUP(121, WEST, qup5, rgmii, _, phase_flag, qdss_gpio, atest_usb2, _, _, _),
+ [122] = PINGROUP(122, WEST, qup5, rgmii, _, phase_flag, atest_usb2, _, _, _, _),
+ [123] = PINGROUP(123, SOUTH, usb2phy_ac, _, phase_flag, _, _, _, _, _, _),
+ [124] = PINGROUP(124, SOUTH, emac_phy, _, _, _, _, _, _, _, _),
+ [125] = PINGROUP(125, WEST, hs3_mi2s, _, phase_flag, _, _, _, _, _, _),
+ [126] = PINGROUP(126, WEST, sec_mi2s, qup2, _, _, _, _, _, _, _),
+ [127] = PINGROUP(127, WEST, sec_mi2s, qup2, _, _, _, _, _, _, _),
+ [128] = PINGROUP(128, WEST, sec_mi2s, qup2, _, _, _, _, _, _, _),
+ [129] = PINGROUP(129, WEST, sec_mi2s, qup2, jitter_bist, _, _, _, _, _, _),
+ [130] = PINGROUP(130, WEST, sec_mi2s, pll_bist, _, qdss_gpio, _, _, _, _, _),
+ [131] = PINGROUP(131, WEST, ter_mi2s, gcc_gp1, _, _, _, _, _, _, _),
+ [132] = PINGROUP(132, WEST, ter_mi2s, _, qdss_gpio, _, _, _, _, _, _),
+ [133] = PINGROUP(133, WEST, ter_mi2s, _, qdss_gpio, atest_char, _, _, _, _, _),
+ [134] = PINGROUP(134, WEST, ter_mi2s, _, qdss_gpio, atest_char, _, _, _, _, _),
+ [135] = PINGROUP(135, WEST, ter_mi2s, _, qdss_gpio, atest_char, _, _, _, _, _),
+ [136] = PINGROUP(136, WEST, qua_mi2s, gcc_gp1, _, _, _, _, _, _, _),
+ [137] = PINGROUP(137, WEST, qua_mi2s, gcc_gp2, _, _, _, _, _, _, _),
+ [138] = PINGROUP(138, WEST, qua_mi2s, gcc_gp3, _, _, _, _, _, _, _),
+ [139] = PINGROUP(139, WEST, qua_mi2s, gcc_gp4, _, _, _, _, _, _, _),
+ [140] = PINGROUP(140, WEST, qua_mi2s, gcc_gp5, _, atest_char, _, _, _, _, _),
+ [141] = PINGROUP(141, WEST, qua_mi2s, qdss_cti, _, _, _, _, _, _, _),
+ [142] = PINGROUP(142, WEST, qua_mi2s, _, _, qdss_cti, atest_char, _, _, _, _),
+ [143] = PINGROUP(143, WEST, pri_mi2s, _, _, _, _, _, _, _, _),
+ [144] = PINGROUP(144, WEST, pri_mi2s, qup3, _, _, _, _, _, _, _),
+ [145] = PINGROUP(145, WEST, pri_mi2s_ws, qup3, ddr_bist, _, _, _, _, _, _),
+ [146] = PINGROUP(146, WEST, pri_mi2s, qup3, ddr_bist, _, _, _, _, _, _),
+ [147] = PINGROUP(147, WEST, pri_mi2s, qup3, _, _, _, _, _, _, _),
+ [148] = PINGROUP(148, WEST, spkr_i2s, audio_ref, _, phase_flag, _, _, _, _, _),
+ [149] = PINGROUP(149, WEST, lpass_slimbus, spkr_i2s, _, phase_flag, _, _, _, _, _),
+ [150] = PINGROUP(150, WEST, lpass_slimbus, spkr_i2s, _, phase_flag, tsense_pwm1, tsense_pwm2, _, _, _),
+ [151] = PINGROUP(151, WEST, lpass_slimbus, spkr_i2s, _, phase_flag, _, _, _, _, _),
+ [152] = PINGROUP(152, WEST, lpass_slimbus, spkr_i2s, _, phase_flag, _, _, _, _, _),
+ [153] = PINGROUP(153, WEST, btfm_slimbus, _, _, _, _, _, _, _, _),
+ [154] = PINGROUP(154, WEST, btfm_slimbus, _, _, _, _, _, _, _, _),
+ [155] = PINGROUP(155, WEST, hs1_mi2s, _, phase_flag, _, _, _, _, _, _),
+ [156] = PINGROUP(156, WEST, hs1_mi2s, _, phase_flag, _, _, _, _, _, _),
+ [157] = PINGROUP(157, WEST, hs1_mi2s, _, phase_flag, _, _, _, _, _, _),
+ [158] = PINGROUP(158, WEST, hs1_mi2s, _, phase_flag, _, _, _, _, _, _),
+ [159] = PINGROUP(159, WEST, hs1_mi2s, cri_trng, _, phase_flag, _, _, _, _, _),
+ [160] = PINGROUP(160, WEST, hs2_mi2s, cri_trng, _, phase_flag, _, _, _, _, _),
+ [161] = PINGROUP(161, WEST, hs2_mi2s, qspi1, cri_trng, _, phase_flag, _, _, _, _),
+ [162] = PINGROUP(162, WEST, hs2_mi2s, qspi1, sp_cmu, _, phase_flag, _, _, _, _),
+ [163] = PINGROUP(163, WEST, hs2_mi2s, qspi1_clk, prng_rosc, _, phase_flag, _, _, _, _),
+ [164] = PINGROUP(164, WEST, hs2_mi2s, qspi1_cs, _, phase_flag, _, _, _, _, _),
+ [165] = PINGROUP(165, WEST, hs3_mi2s, _, phase_flag, _, _, _, _, _, _),
+ [166] = PINGROUP(166, WEST, hs3_mi2s, _, phase_flag, _, _, _, _, _, _),
+ [167] = PINGROUP(167, WEST, hs3_mi2s, _, phase_flag, _, _, _, _, _, _),
+ [168] = PINGROUP(168, WEST, hs3_mi2s, _, phase_flag, _, _, _, _, _, _),
+ [169] = PINGROUP(169, SOUTH, _, _, _, _, _, _, _, _, _),
+ [170] = PINGROUP(170, SOUTH, _, _, _, _, _, _, _, _, _),
+ [171] = PINGROUP(171, SOUTH, _, _, _, _, _, _, _, _, _),
+ [172] = PINGROUP(172, SOUTH, _, _, _, _, _, _, _, _, _),
+ [173] = PINGROUP(173, SOUTH, _, _, _, _, _, _, _, _, _),
+ [174] = PINGROUP(174, SOUTH, _, _, _, _, _, _, _, _, _),
+ [175] = PINGROUP(175, SOUTH, pci_e2, _, _, _, _, _, _, _, _),
+ [176] = PINGROUP(176, SOUTH, pci_e2, cci_async, _, _, _, _, _, _, _),
+ [177] = PINGROUP_OFFSET(177, SOUTH, 0x1e000, _, _, _, _, _, _, _, _, _),
+ [178] = PINGROUP_OFFSET(178, SOUTH, 0x1e000, pci_e3, cci_timer4, _, _, _, _, _, _, _),
+ [179] = PINGROUP_OFFSET(179, SOUTH, 0x1e000, pci_e3, cam_mclk, _, _, _, _, _, _, _),
+ [180] = PINGROUP_OFFSET(180, SOUTH, 0x1e000, cam_mclk, _, _, _, _, _, _, _, _),
+ [181] = PINGROUP_OFFSET(181, SOUTH, 0x1e000, qup19, cam_mclk, _, _, _, _, _, _, _),
+ [182] = PINGROUP_OFFSET(182, SOUTH, 0x1e000, qup19, cci_timer5, gcc_gp4, _, _, _, _, _, _),
+ [183] = PINGROUP_OFFSET(183, SOUTH, 0x1e000, qup19, cci_timer6, gcc_gp5, _, _, _, _, _, _),
+ [184] = PINGROUP_OFFSET(184, SOUTH, 0x1e000, qup19, cci_timer7, _, _, _, _, _, _, _),
+ [185] = PINGROUP_OFFSET(185, SOUTH, 0x1e000, cci_timer8, cci_async, _, _, _, _, _, _, _),
+ [186] = PINGROUP_OFFSET(186, SOUTH, 0x1e000, cci_timer9, cci_async, _, _, _, _, _, _, _),
+ [187] = PINGROUP_OFFSET(187, SOUTH, 0x1e000, _, _, _, _, _, _, _, _, _),
+ [188] = PINGROUP_OFFSET(188, SOUTH, 0x1e000, _, _, _, _, _, _, _, _, _),
+ [189] = PINGROUP_OFFSET(189, SOUTH, 0x1e000, dp_hot, _, _, _, _, _, _, _, _),
+ [190] = UFS_RESET(ufs_reset),
+ [191] = SDC_QDSD_PINGROUP(sdc2_clk, 0x4b2000, 14, 6),
+ [192] = SDC_QDSD_PINGROUP(sdc2_cmd, 0x4b2000, 11, 3),
+ [193] = SDC_QDSD_PINGROUP(sdc2_data, 0x4b2000, 9, 0),
+};
+
+static const struct msm_gpio_wakeirq_map sc8180x_pdc_map[] = {
+ { 3, 31 }, { 5, 32 }, { 8, 33 }, { 9, 34 }, { 10, 100 }, { 12, 104 },
+ { 24, 37 }, { 26, 38 }, { 27, 41 }, { 28, 42 }, { 30, 39 }, { 36, 43 },
+ { 37, 43 }, { 38, 45 }, { 39, 118 }, { 39, 125 }, { 41, 47 },
+ { 42, 48 }, { 46, 50 }, { 47, 49 }, { 48, 51 }, { 49, 53 }, { 50, 52 },
+ { 51, 116 }, { 51, 123 }, { 53, 54 }, { 54, 55 }, { 55, 56 },
+ { 56, 57 }, { 58, 58 }, { 60, 60 }, { 68, 62 }, { 70, 63 }, { 76, 86 },
+ { 77, 36 }, { 81, 64 }, { 83, 65 }, { 86, 67 }, { 87, 84 }, { 88, 117 },
+ { 88, 124 }, { 90, 69 }, { 91, 70 }, { 93, 75 }, { 95, 72 }, { 97, 74 },
+ { 101, 76 }, { 103, 77 }, { 104, 78 }, { 114, 82 }, { 117, 85 },
+ { 118, 101 }, { 119, 87 }, { 120, 88 }, { 121, 89 }, { 122, 90 },
+ { 123, 91 }, { 124, 92 }, { 125, 93 }, { 129, 94 }, { 132, 105 },
+ { 133, 35 }, { 134, 36 }, { 136, 97 }, { 142, 103 }, { 144, 115 },
+ { 144, 122 }, { 147, 106 }, { 150, 107 }, { 152, 108 }, { 153, 109 },
+ { 177, 111 }, { 180, 112 }, { 184, 113 }, { 189, 114 }
+};
+
+static struct msm_pinctrl_soc_data sc8180x_pinctrl = {
+ .tiles = sc8180x_tiles,
+ .ntiles = ARRAY_SIZE(sc8180x_tiles),
+ .pins = sc8180x_pins,
+ .npins = ARRAY_SIZE(sc8180x_pins),
+ .functions = sc8180x_functions,
+ .nfunctions = ARRAY_SIZE(sc8180x_functions),
+ .groups = sc8180x_groups,
+ .ngroups = ARRAY_SIZE(sc8180x_groups),
+ .ngpios = 191,
+ .wakeirq_map = sc8180x_pdc_map,
+ .nwakeirq_map = ARRAY_SIZE(sc8180x_pdc_map),
+};
+
+static int sc8180x_pinctrl_probe(struct platform_device *pdev)
+{
+ return msm_pinctrl_probe(pdev, &sc8180x_pinctrl);
+}
+
+static const struct of_device_id sc8180x_pinctrl_of_match[] = {
+ { .compatible = "qcom,sc8180x-tlmm", },
+ { },
+};
+MODULE_DEVICE_TABLE(of, sc8180x_pinctrl_of_match);
+
+static struct platform_driver sc8180x_pinctrl_driver = {
+ .driver = {
+ .name = "sc8180x-pinctrl",
+ .of_match_table = sc8180x_pinctrl_of_match,
+ },
+ .probe = sc8180x_pinctrl_probe,
+ .remove = msm_pinctrl_remove,
+};
+
+static int __init sc8180x_pinctrl_init(void)
+{
+ return platform_driver_register(&sc8180x_pinctrl_driver);
+}
+arch_initcall(sc8180x_pinctrl_init);
+
+static void __exit sc8180x_pinctrl_exit(void)
+{
+ platform_driver_unregister(&sc8180x_pinctrl_driver);
+}
+module_exit(sc8180x_pinctrl_exit);
+
+MODULE_DESCRIPTION("QTI SC8180x pinctrl driver");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/pinctrl/qcom/pinctrl-sdm845.c b/drivers/pinctrl/qcom/pinctrl-sdm845.c
index 2834d2c..c51793f 100644
--- a/drivers/pinctrl/qcom/pinctrl-sdm845.c
+++ b/drivers/pinctrl/qcom/pinctrl-sdm845.c
@@ -1310,7 +1310,6 @@
.ngpios = 151,
.wakeirq_map = sdm845_pdc_map,
.nwakeirq_map = ARRAY_SIZE(sdm845_pdc_map),
-
};
static const struct msm_pinctrl_soc_data sdm845_acpi_pinctrl = {
diff --git a/drivers/pinctrl/qcom/pinctrl-sm8350.c b/drivers/pinctrl/qcom/pinctrl-sm8350.c
new file mode 100644
index 0000000..a406ed0e
--- /dev/null
+++ b/drivers/pinctrl/qcom/pinctrl-sm8350.c
@@ -0,0 +1,1649 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2020-2021, Linaro Limited
+ */
+
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/pinctrl/pinctrl.h>
+
+#include "pinctrl-msm.h"
+
+#define FUNCTION(fname) \
+ [msm_mux_##fname] = { \
+ .name = #fname, \
+ .groups = fname##_groups, \
+ .ngroups = ARRAY_SIZE(fname##_groups), \
+ }
+
+#define REG_SIZE 0x1000
+
+#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9) \
+ { \
+ .name = "gpio" #id, \
+ .pins = gpio##id##_pins, \
+ .npins = (unsigned int)ARRAY_SIZE(gpio##id##_pins), \
+ .funcs = (int[]){ \
+ msm_mux_gpio, /* gpio mode */ \
+ msm_mux_##f1, \
+ msm_mux_##f2, \
+ msm_mux_##f3, \
+ msm_mux_##f4, \
+ msm_mux_##f5, \
+ msm_mux_##f6, \
+ msm_mux_##f7, \
+ msm_mux_##f8, \
+ msm_mux_##f9 \
+ }, \
+ .nfuncs = 10, \
+ .ctl_reg = REG_SIZE * id, \
+ .io_reg = REG_SIZE * id + 0x4, \
+ .intr_cfg_reg = REG_SIZE * id + 0x8, \
+ .intr_status_reg = REG_SIZE * id + 0xc, \
+ .intr_target_reg = REG_SIZE * id + 0x8, \
+ .mux_bit = 2, \
+ .pull_bit = 0, \
+ .drv_bit = 6, \
+ .oe_bit = 9, \
+ .in_bit = 0, \
+ .out_bit = 1, \
+ .intr_enable_bit = 0, \
+ .intr_status_bit = 0, \
+ .intr_target_bit = 5, \
+ .intr_target_kpss_val = 3, \
+ .intr_raw_status_bit = 4, \
+ .intr_polarity_bit = 1, \
+ .intr_detection_bit = 2, \
+ .intr_detection_width = 2, \
+ }
+
+#define SDC_PINGROUP(pg_name, ctl, pull, drv) \
+ { \
+ .name = #pg_name, \
+ .pins = pg_name##_pins, \
+ .npins = (unsigned int)ARRAY_SIZE(pg_name##_pins), \
+ .ctl_reg = ctl, \
+ .io_reg = 0, \
+ .intr_cfg_reg = 0, \
+ .intr_status_reg = 0, \
+ .intr_target_reg = 0, \
+ .mux_bit = -1, \
+ .pull_bit = pull, \
+ .drv_bit = drv, \
+ .oe_bit = -1, \
+ .in_bit = -1, \
+ .out_bit = -1, \
+ .intr_enable_bit = -1, \
+ .intr_status_bit = -1, \
+ .intr_target_bit = -1, \
+ .intr_raw_status_bit = -1, \
+ .intr_polarity_bit = -1, \
+ .intr_detection_bit = -1, \
+ .intr_detection_width = -1, \
+ }
+
+#define UFS_RESET(pg_name, offset) \
+ { \
+ .name = #pg_name, \
+ .pins = pg_name##_pins, \
+ .npins = (unsigned int)ARRAY_SIZE(pg_name##_pins), \
+ .ctl_reg = offset, \
+ .io_reg = offset + 0x4, \
+ .intr_cfg_reg = 0, \
+ .intr_status_reg = 0, \
+ .intr_target_reg = 0, \
+ .mux_bit = -1, \
+ .pull_bit = 3, \
+ .drv_bit = 0, \
+ .oe_bit = -1, \
+ .in_bit = -1, \
+ .out_bit = 0, \
+ .intr_enable_bit = -1, \
+ .intr_status_bit = -1, \
+ .intr_target_bit = -1, \
+ .intr_raw_status_bit = -1, \
+ .intr_polarity_bit = -1, \
+ .intr_detection_bit = -1, \
+ .intr_detection_width = -1, \
+ }
+
+static const struct pinctrl_pin_desc sm8350_pins[] = {
+ PINCTRL_PIN(0, "GPIO_0"),
+ PINCTRL_PIN(1, "GPIO_1"),
+ PINCTRL_PIN(2, "GPIO_2"),
+ PINCTRL_PIN(3, "GPIO_3"),
+ PINCTRL_PIN(4, "GPIO_4"),
+ PINCTRL_PIN(5, "GPIO_5"),
+ PINCTRL_PIN(6, "GPIO_6"),
+ PINCTRL_PIN(7, "GPIO_7"),
+ PINCTRL_PIN(8, "GPIO_8"),
+ PINCTRL_PIN(9, "GPIO_9"),
+ PINCTRL_PIN(10, "GPIO_10"),
+ PINCTRL_PIN(11, "GPIO_11"),
+ PINCTRL_PIN(12, "GPIO_12"),
+ PINCTRL_PIN(13, "GPIO_13"),
+ PINCTRL_PIN(14, "GPIO_14"),
+ PINCTRL_PIN(15, "GPIO_15"),
+ PINCTRL_PIN(16, "GPIO_16"),
+ PINCTRL_PIN(17, "GPIO_17"),
+ PINCTRL_PIN(18, "GPIO_18"),
+ PINCTRL_PIN(19, "GPIO_19"),
+ PINCTRL_PIN(20, "GPIO_20"),
+ PINCTRL_PIN(21, "GPIO_21"),
+ PINCTRL_PIN(22, "GPIO_22"),
+ PINCTRL_PIN(23, "GPIO_23"),
+ PINCTRL_PIN(24, "GPIO_24"),
+ PINCTRL_PIN(25, "GPIO_25"),
+ PINCTRL_PIN(26, "GPIO_26"),
+ PINCTRL_PIN(27, "GPIO_27"),
+ PINCTRL_PIN(28, "GPIO_28"),
+ PINCTRL_PIN(29, "GPIO_29"),
+ PINCTRL_PIN(30, "GPIO_30"),
+ PINCTRL_PIN(31, "GPIO_31"),
+ PINCTRL_PIN(32, "GPIO_32"),
+ PINCTRL_PIN(33, "GPIO_33"),
+ PINCTRL_PIN(34, "GPIO_34"),
+ PINCTRL_PIN(35, "GPIO_35"),
+ PINCTRL_PIN(36, "GPIO_36"),
+ PINCTRL_PIN(37, "GPIO_37"),
+ PINCTRL_PIN(38, "GPIO_38"),
+ PINCTRL_PIN(39, "GPIO_39"),
+ PINCTRL_PIN(40, "GPIO_40"),
+ PINCTRL_PIN(41, "GPIO_41"),
+ PINCTRL_PIN(42, "GPIO_42"),
+ PINCTRL_PIN(43, "GPIO_43"),
+ PINCTRL_PIN(44, "GPIO_44"),
+ PINCTRL_PIN(45, "GPIO_45"),
+ PINCTRL_PIN(46, "GPIO_46"),
+ PINCTRL_PIN(47, "GPIO_47"),
+ PINCTRL_PIN(48, "GPIO_48"),
+ PINCTRL_PIN(49, "GPIO_49"),
+ PINCTRL_PIN(50, "GPIO_50"),
+ PINCTRL_PIN(51, "GPIO_51"),
+ PINCTRL_PIN(52, "GPIO_52"),
+ PINCTRL_PIN(53, "GPIO_53"),
+ PINCTRL_PIN(54, "GPIO_54"),
+ PINCTRL_PIN(55, "GPIO_55"),
+ PINCTRL_PIN(56, "GPIO_56"),
+ PINCTRL_PIN(57, "GPIO_57"),
+ PINCTRL_PIN(58, "GPIO_58"),
+ PINCTRL_PIN(59, "GPIO_59"),
+ PINCTRL_PIN(60, "GPIO_60"),
+ PINCTRL_PIN(61, "GPIO_61"),
+ PINCTRL_PIN(62, "GPIO_62"),
+ PINCTRL_PIN(63, "GPIO_63"),
+ PINCTRL_PIN(64, "GPIO_64"),
+ PINCTRL_PIN(65, "GPIO_65"),
+ PINCTRL_PIN(66, "GPIO_66"),
+ PINCTRL_PIN(67, "GPIO_67"),
+ PINCTRL_PIN(68, "GPIO_68"),
+ PINCTRL_PIN(69, "GPIO_69"),
+ PINCTRL_PIN(70, "GPIO_70"),
+ PINCTRL_PIN(71, "GPIO_71"),
+ PINCTRL_PIN(72, "GPIO_72"),
+ PINCTRL_PIN(73, "GPIO_73"),
+ PINCTRL_PIN(74, "GPIO_74"),
+ PINCTRL_PIN(75, "GPIO_75"),
+ PINCTRL_PIN(76, "GPIO_76"),
+ PINCTRL_PIN(77, "GPIO_77"),
+ PINCTRL_PIN(78, "GPIO_78"),
+ PINCTRL_PIN(79, "GPIO_79"),
+ PINCTRL_PIN(80, "GPIO_80"),
+ PINCTRL_PIN(81, "GPIO_81"),
+ PINCTRL_PIN(82, "GPIO_82"),
+ PINCTRL_PIN(83, "GPIO_83"),
+ PINCTRL_PIN(84, "GPIO_84"),
+ PINCTRL_PIN(85, "GPIO_85"),
+ PINCTRL_PIN(86, "GPIO_86"),
+ PINCTRL_PIN(87, "GPIO_87"),
+ PINCTRL_PIN(88, "GPIO_88"),
+ PINCTRL_PIN(89, "GPIO_89"),
+ PINCTRL_PIN(90, "GPIO_90"),
+ PINCTRL_PIN(91, "GPIO_91"),
+ PINCTRL_PIN(92, "GPIO_92"),
+ PINCTRL_PIN(93, "GPIO_93"),
+ PINCTRL_PIN(94, "GPIO_94"),
+ PINCTRL_PIN(95, "GPIO_95"),
+ PINCTRL_PIN(96, "GPIO_96"),
+ PINCTRL_PIN(97, "GPIO_97"),
+ PINCTRL_PIN(98, "GPIO_98"),
+ PINCTRL_PIN(99, "GPIO_99"),
+ PINCTRL_PIN(100, "GPIO_100"),
+ PINCTRL_PIN(101, "GPIO_101"),
+ PINCTRL_PIN(102, "GPIO_102"),
+ PINCTRL_PIN(103, "GPIO_103"),
+ PINCTRL_PIN(104, "GPIO_104"),
+ PINCTRL_PIN(105, "GPIO_105"),
+ PINCTRL_PIN(106, "GPIO_106"),
+ PINCTRL_PIN(107, "GPIO_107"),
+ PINCTRL_PIN(108, "GPIO_108"),
+ PINCTRL_PIN(109, "GPIO_109"),
+ PINCTRL_PIN(110, "GPIO_110"),
+ PINCTRL_PIN(111, "GPIO_111"),
+ PINCTRL_PIN(112, "GPIO_112"),
+ PINCTRL_PIN(113, "GPIO_113"),
+ PINCTRL_PIN(114, "GPIO_114"),
+ PINCTRL_PIN(115, "GPIO_115"),
+ PINCTRL_PIN(116, "GPIO_116"),
+ PINCTRL_PIN(117, "GPIO_117"),
+ PINCTRL_PIN(118, "GPIO_118"),
+ PINCTRL_PIN(119, "GPIO_119"),
+ PINCTRL_PIN(120, "GPIO_120"),
+ PINCTRL_PIN(121, "GPIO_121"),
+ PINCTRL_PIN(122, "GPIO_122"),
+ PINCTRL_PIN(123, "GPIO_123"),
+ PINCTRL_PIN(124, "GPIO_124"),
+ PINCTRL_PIN(125, "GPIO_125"),
+ PINCTRL_PIN(126, "GPIO_126"),
+ PINCTRL_PIN(127, "GPIO_127"),
+ PINCTRL_PIN(128, "GPIO_128"),
+ PINCTRL_PIN(129, "GPIO_129"),
+ PINCTRL_PIN(130, "GPIO_130"),
+ PINCTRL_PIN(131, "GPIO_131"),
+ PINCTRL_PIN(132, "GPIO_132"),
+ PINCTRL_PIN(133, "GPIO_133"),
+ PINCTRL_PIN(134, "GPIO_134"),
+ PINCTRL_PIN(135, "GPIO_135"),
+ PINCTRL_PIN(136, "GPIO_136"),
+ PINCTRL_PIN(137, "GPIO_137"),
+ PINCTRL_PIN(138, "GPIO_138"),
+ PINCTRL_PIN(139, "GPIO_139"),
+ PINCTRL_PIN(140, "GPIO_140"),
+ PINCTRL_PIN(141, "GPIO_141"),
+ PINCTRL_PIN(142, "GPIO_142"),
+ PINCTRL_PIN(143, "GPIO_143"),
+ PINCTRL_PIN(144, "GPIO_144"),
+ PINCTRL_PIN(145, "GPIO_145"),
+ PINCTRL_PIN(146, "GPIO_146"),
+ PINCTRL_PIN(147, "GPIO_147"),
+ PINCTRL_PIN(148, "GPIO_148"),
+ PINCTRL_PIN(149, "GPIO_149"),
+ PINCTRL_PIN(150, "GPIO_150"),
+ PINCTRL_PIN(151, "GPIO_151"),
+ PINCTRL_PIN(152, "GPIO_152"),
+ PINCTRL_PIN(153, "GPIO_153"),
+ PINCTRL_PIN(154, "GPIO_154"),
+ PINCTRL_PIN(155, "GPIO_155"),
+ PINCTRL_PIN(156, "GPIO_156"),
+ PINCTRL_PIN(157, "GPIO_157"),
+ PINCTRL_PIN(158, "GPIO_158"),
+ PINCTRL_PIN(159, "GPIO_159"),
+ PINCTRL_PIN(160, "GPIO_160"),
+ PINCTRL_PIN(161, "GPIO_161"),
+ PINCTRL_PIN(162, "GPIO_162"),
+ PINCTRL_PIN(163, "GPIO_163"),
+ PINCTRL_PIN(164, "GPIO_164"),
+ PINCTRL_PIN(165, "GPIO_165"),
+ PINCTRL_PIN(166, "GPIO_166"),
+ PINCTRL_PIN(167, "GPIO_167"),
+ PINCTRL_PIN(168, "GPIO_168"),
+ PINCTRL_PIN(169, "GPIO_169"),
+ PINCTRL_PIN(170, "GPIO_170"),
+ PINCTRL_PIN(171, "GPIO_171"),
+ PINCTRL_PIN(172, "GPIO_172"),
+ PINCTRL_PIN(173, "GPIO_173"),
+ PINCTRL_PIN(174, "GPIO_174"),
+ PINCTRL_PIN(175, "GPIO_175"),
+ PINCTRL_PIN(176, "GPIO_176"),
+ PINCTRL_PIN(177, "GPIO_177"),
+ PINCTRL_PIN(178, "GPIO_178"),
+ PINCTRL_PIN(179, "GPIO_179"),
+ PINCTRL_PIN(180, "GPIO_180"),
+ PINCTRL_PIN(181, "GPIO_181"),
+ PINCTRL_PIN(182, "GPIO_182"),
+ PINCTRL_PIN(183, "GPIO_183"),
+ PINCTRL_PIN(184, "GPIO_184"),
+ PINCTRL_PIN(185, "GPIO_185"),
+ PINCTRL_PIN(186, "GPIO_186"),
+ PINCTRL_PIN(187, "GPIO_187"),
+ PINCTRL_PIN(188, "GPIO_188"),
+ PINCTRL_PIN(189, "GPIO_189"),
+ PINCTRL_PIN(190, "GPIO_190"),
+ PINCTRL_PIN(191, "GPIO_191"),
+ PINCTRL_PIN(192, "GPIO_192"),
+ PINCTRL_PIN(193, "GPIO_193"),
+ PINCTRL_PIN(194, "GPIO_194"),
+ PINCTRL_PIN(195, "GPIO_195"),
+ PINCTRL_PIN(196, "GPIO_196"),
+ PINCTRL_PIN(197, "GPIO_197"),
+ PINCTRL_PIN(198, "GPIO_198"),
+ PINCTRL_PIN(199, "GPIO_199"),
+ PINCTRL_PIN(200, "GPIO_200"),
+ PINCTRL_PIN(201, "GPIO_201"),
+ PINCTRL_PIN(202, "GPIO_202"),
+ PINCTRL_PIN(203, "UFS_RESET"),
+ PINCTRL_PIN(204, "SDC2_CLK"),
+ PINCTRL_PIN(205, "SDC2_CMD"),
+ PINCTRL_PIN(206, "SDC2_DATA"),
+};
+
+#define DECLARE_MSM_GPIO_PINS(pin) \
+ static const unsigned int gpio##pin##_pins[] = { pin }
+DECLARE_MSM_GPIO_PINS(0);
+DECLARE_MSM_GPIO_PINS(1);
+DECLARE_MSM_GPIO_PINS(2);
+DECLARE_MSM_GPIO_PINS(3);
+DECLARE_MSM_GPIO_PINS(4);
+DECLARE_MSM_GPIO_PINS(5);
+DECLARE_MSM_GPIO_PINS(6);
+DECLARE_MSM_GPIO_PINS(7);
+DECLARE_MSM_GPIO_PINS(8);
+DECLARE_MSM_GPIO_PINS(9);
+DECLARE_MSM_GPIO_PINS(10);
+DECLARE_MSM_GPIO_PINS(11);
+DECLARE_MSM_GPIO_PINS(12);
+DECLARE_MSM_GPIO_PINS(13);
+DECLARE_MSM_GPIO_PINS(14);
+DECLARE_MSM_GPIO_PINS(15);
+DECLARE_MSM_GPIO_PINS(16);
+DECLARE_MSM_GPIO_PINS(17);
+DECLARE_MSM_GPIO_PINS(18);
+DECLARE_MSM_GPIO_PINS(19);
+DECLARE_MSM_GPIO_PINS(20);
+DECLARE_MSM_GPIO_PINS(21);
+DECLARE_MSM_GPIO_PINS(22);
+DECLARE_MSM_GPIO_PINS(23);
+DECLARE_MSM_GPIO_PINS(24);
+DECLARE_MSM_GPIO_PINS(25);
+DECLARE_MSM_GPIO_PINS(26);
+DECLARE_MSM_GPIO_PINS(27);
+DECLARE_MSM_GPIO_PINS(28);
+DECLARE_MSM_GPIO_PINS(29);
+DECLARE_MSM_GPIO_PINS(30);
+DECLARE_MSM_GPIO_PINS(31);
+DECLARE_MSM_GPIO_PINS(32);
+DECLARE_MSM_GPIO_PINS(33);
+DECLARE_MSM_GPIO_PINS(34);
+DECLARE_MSM_GPIO_PINS(35);
+DECLARE_MSM_GPIO_PINS(36);
+DECLARE_MSM_GPIO_PINS(37);
+DECLARE_MSM_GPIO_PINS(38);
+DECLARE_MSM_GPIO_PINS(39);
+DECLARE_MSM_GPIO_PINS(40);
+DECLARE_MSM_GPIO_PINS(41);
+DECLARE_MSM_GPIO_PINS(42);
+DECLARE_MSM_GPIO_PINS(43);
+DECLARE_MSM_GPIO_PINS(44);
+DECLARE_MSM_GPIO_PINS(45);
+DECLARE_MSM_GPIO_PINS(46);
+DECLARE_MSM_GPIO_PINS(47);
+DECLARE_MSM_GPIO_PINS(48);
+DECLARE_MSM_GPIO_PINS(49);
+DECLARE_MSM_GPIO_PINS(50);
+DECLARE_MSM_GPIO_PINS(51);
+DECLARE_MSM_GPIO_PINS(52);
+DECLARE_MSM_GPIO_PINS(53);
+DECLARE_MSM_GPIO_PINS(54);
+DECLARE_MSM_GPIO_PINS(55);
+DECLARE_MSM_GPIO_PINS(56);
+DECLARE_MSM_GPIO_PINS(57);
+DECLARE_MSM_GPIO_PINS(58);
+DECLARE_MSM_GPIO_PINS(59);
+DECLARE_MSM_GPIO_PINS(60);
+DECLARE_MSM_GPIO_PINS(61);
+DECLARE_MSM_GPIO_PINS(62);
+DECLARE_MSM_GPIO_PINS(63);
+DECLARE_MSM_GPIO_PINS(64);
+DECLARE_MSM_GPIO_PINS(65);
+DECLARE_MSM_GPIO_PINS(66);
+DECLARE_MSM_GPIO_PINS(67);
+DECLARE_MSM_GPIO_PINS(68);
+DECLARE_MSM_GPIO_PINS(69);
+DECLARE_MSM_GPIO_PINS(70);
+DECLARE_MSM_GPIO_PINS(71);
+DECLARE_MSM_GPIO_PINS(72);
+DECLARE_MSM_GPIO_PINS(73);
+DECLARE_MSM_GPIO_PINS(74);
+DECLARE_MSM_GPIO_PINS(75);
+DECLARE_MSM_GPIO_PINS(76);
+DECLARE_MSM_GPIO_PINS(77);
+DECLARE_MSM_GPIO_PINS(78);
+DECLARE_MSM_GPIO_PINS(79);
+DECLARE_MSM_GPIO_PINS(80);
+DECLARE_MSM_GPIO_PINS(81);
+DECLARE_MSM_GPIO_PINS(82);
+DECLARE_MSM_GPIO_PINS(83);
+DECLARE_MSM_GPIO_PINS(84);
+DECLARE_MSM_GPIO_PINS(85);
+DECLARE_MSM_GPIO_PINS(86);
+DECLARE_MSM_GPIO_PINS(87);
+DECLARE_MSM_GPIO_PINS(88);
+DECLARE_MSM_GPIO_PINS(89);
+DECLARE_MSM_GPIO_PINS(90);
+DECLARE_MSM_GPIO_PINS(91);
+DECLARE_MSM_GPIO_PINS(92);
+DECLARE_MSM_GPIO_PINS(93);
+DECLARE_MSM_GPIO_PINS(94);
+DECLARE_MSM_GPIO_PINS(95);
+DECLARE_MSM_GPIO_PINS(96);
+DECLARE_MSM_GPIO_PINS(97);
+DECLARE_MSM_GPIO_PINS(98);
+DECLARE_MSM_GPIO_PINS(99);
+DECLARE_MSM_GPIO_PINS(100);
+DECLARE_MSM_GPIO_PINS(101);
+DECLARE_MSM_GPIO_PINS(102);
+DECLARE_MSM_GPIO_PINS(103);
+DECLARE_MSM_GPIO_PINS(104);
+DECLARE_MSM_GPIO_PINS(105);
+DECLARE_MSM_GPIO_PINS(106);
+DECLARE_MSM_GPIO_PINS(107);
+DECLARE_MSM_GPIO_PINS(108);
+DECLARE_MSM_GPIO_PINS(109);
+DECLARE_MSM_GPIO_PINS(110);
+DECLARE_MSM_GPIO_PINS(111);
+DECLARE_MSM_GPIO_PINS(112);
+DECLARE_MSM_GPIO_PINS(113);
+DECLARE_MSM_GPIO_PINS(114);
+DECLARE_MSM_GPIO_PINS(115);
+DECLARE_MSM_GPIO_PINS(116);
+DECLARE_MSM_GPIO_PINS(117);
+DECLARE_MSM_GPIO_PINS(118);
+DECLARE_MSM_GPIO_PINS(119);
+DECLARE_MSM_GPIO_PINS(120);
+DECLARE_MSM_GPIO_PINS(121);
+DECLARE_MSM_GPIO_PINS(122);
+DECLARE_MSM_GPIO_PINS(123);
+DECLARE_MSM_GPIO_PINS(124);
+DECLARE_MSM_GPIO_PINS(125);
+DECLARE_MSM_GPIO_PINS(126);
+DECLARE_MSM_GPIO_PINS(127);
+DECLARE_MSM_GPIO_PINS(128);
+DECLARE_MSM_GPIO_PINS(129);
+DECLARE_MSM_GPIO_PINS(130);
+DECLARE_MSM_GPIO_PINS(131);
+DECLARE_MSM_GPIO_PINS(132);
+DECLARE_MSM_GPIO_PINS(133);
+DECLARE_MSM_GPIO_PINS(134);
+DECLARE_MSM_GPIO_PINS(135);
+DECLARE_MSM_GPIO_PINS(136);
+DECLARE_MSM_GPIO_PINS(137);
+DECLARE_MSM_GPIO_PINS(138);
+DECLARE_MSM_GPIO_PINS(139);
+DECLARE_MSM_GPIO_PINS(140);
+DECLARE_MSM_GPIO_PINS(141);
+DECLARE_MSM_GPIO_PINS(142);
+DECLARE_MSM_GPIO_PINS(143);
+DECLARE_MSM_GPIO_PINS(144);
+DECLARE_MSM_GPIO_PINS(145);
+DECLARE_MSM_GPIO_PINS(146);
+DECLARE_MSM_GPIO_PINS(147);
+DECLARE_MSM_GPIO_PINS(148);
+DECLARE_MSM_GPIO_PINS(149);
+DECLARE_MSM_GPIO_PINS(150);
+DECLARE_MSM_GPIO_PINS(151);
+DECLARE_MSM_GPIO_PINS(152);
+DECLARE_MSM_GPIO_PINS(153);
+DECLARE_MSM_GPIO_PINS(154);
+DECLARE_MSM_GPIO_PINS(155);
+DECLARE_MSM_GPIO_PINS(156);
+DECLARE_MSM_GPIO_PINS(157);
+DECLARE_MSM_GPIO_PINS(158);
+DECLARE_MSM_GPIO_PINS(159);
+DECLARE_MSM_GPIO_PINS(160);
+DECLARE_MSM_GPIO_PINS(161);
+DECLARE_MSM_GPIO_PINS(162);
+DECLARE_MSM_GPIO_PINS(163);
+DECLARE_MSM_GPIO_PINS(164);
+DECLARE_MSM_GPIO_PINS(165);
+DECLARE_MSM_GPIO_PINS(166);
+DECLARE_MSM_GPIO_PINS(167);
+DECLARE_MSM_GPIO_PINS(168);
+DECLARE_MSM_GPIO_PINS(169);
+DECLARE_MSM_GPIO_PINS(170);
+DECLARE_MSM_GPIO_PINS(171);
+DECLARE_MSM_GPIO_PINS(172);
+DECLARE_MSM_GPIO_PINS(173);
+DECLARE_MSM_GPIO_PINS(174);
+DECLARE_MSM_GPIO_PINS(175);
+DECLARE_MSM_GPIO_PINS(176);
+DECLARE_MSM_GPIO_PINS(177);
+DECLARE_MSM_GPIO_PINS(178);
+DECLARE_MSM_GPIO_PINS(179);
+DECLARE_MSM_GPIO_PINS(180);
+DECLARE_MSM_GPIO_PINS(181);
+DECLARE_MSM_GPIO_PINS(182);
+DECLARE_MSM_GPIO_PINS(183);
+DECLARE_MSM_GPIO_PINS(184);
+DECLARE_MSM_GPIO_PINS(185);
+DECLARE_MSM_GPIO_PINS(186);
+DECLARE_MSM_GPIO_PINS(187);
+DECLARE_MSM_GPIO_PINS(188);
+DECLARE_MSM_GPIO_PINS(189);
+DECLARE_MSM_GPIO_PINS(190);
+DECLARE_MSM_GPIO_PINS(191);
+DECLARE_MSM_GPIO_PINS(192);
+DECLARE_MSM_GPIO_PINS(193);
+DECLARE_MSM_GPIO_PINS(194);
+DECLARE_MSM_GPIO_PINS(195);
+DECLARE_MSM_GPIO_PINS(196);
+DECLARE_MSM_GPIO_PINS(197);
+DECLARE_MSM_GPIO_PINS(198);
+DECLARE_MSM_GPIO_PINS(199);
+DECLARE_MSM_GPIO_PINS(200);
+DECLARE_MSM_GPIO_PINS(201);
+DECLARE_MSM_GPIO_PINS(202);
+
+static const unsigned int ufs_reset_pins[] = { 203 };
+static const unsigned int sdc2_clk_pins[] = { 204 };
+static const unsigned int sdc2_cmd_pins[] = { 205 };
+static const unsigned int sdc2_data_pins[] = { 206 };
+
+enum sm8350_functions {
+ msm_mux_atest_char,
+ msm_mux_atest_usb,
+ msm_mux_audio_ref,
+ msm_mux_cam_mclk,
+ msm_mux_cci_async,
+ msm_mux_cci_i2c,
+ msm_mux_cci_timer,
+ msm_mux_cmu_rng,
+ msm_mux_coex_uart1,
+ msm_mux_coex_uart2,
+ msm_mux_cri_trng,
+ msm_mux_cri_trng0,
+ msm_mux_cri_trng1,
+ msm_mux_dbg_out,
+ msm_mux_ddr_bist,
+ msm_mux_ddr_pxi0,
+ msm_mux_ddr_pxi1,
+ msm_mux_ddr_pxi2,
+ msm_mux_ddr_pxi3,
+ msm_mux_dp_hot,
+ msm_mux_dp_lcd,
+ msm_mux_gcc_gp1,
+ msm_mux_gcc_gp2,
+ msm_mux_gcc_gp3,
+ msm_mux_gpio,
+ msm_mux_ibi_i3c,
+ msm_mux_jitter_bist,
+ msm_mux_lpass_slimbus,
+ msm_mux_mdp_vsync,
+ msm_mux_mdp_vsync0,
+ msm_mux_mdp_vsync1,
+ msm_mux_mdp_vsync2,
+ msm_mux_mdp_vsync3,
+ msm_mux_mi2s0_data0,
+ msm_mux_mi2s0_data1,
+ msm_mux_mi2s0_sck,
+ msm_mux_mi2s0_ws,
+ msm_mux_mi2s1_data0,
+ msm_mux_mi2s1_data1,
+ msm_mux_mi2s1_sck,
+ msm_mux_mi2s1_ws,
+ msm_mux_mi2s2_data0,
+ msm_mux_mi2s2_data1,
+ msm_mux_mi2s2_sck,
+ msm_mux_mi2s2_ws,
+ msm_mux_mss_grfc0,
+ msm_mux_mss_grfc1,
+ msm_mux_mss_grfc10,
+ msm_mux_mss_grfc11,
+ msm_mux_mss_grfc12,
+ msm_mux_mss_grfc2,
+ msm_mux_mss_grfc3,
+ msm_mux_mss_grfc4,
+ msm_mux_mss_grfc5,
+ msm_mux_mss_grfc6,
+ msm_mux_mss_grfc7,
+ msm_mux_mss_grfc8,
+ msm_mux_mss_grfc9,
+ msm_mux_nav_gpio,
+ msm_mux_pa_indicator,
+ msm_mux_pcie0_clkreqn,
+ msm_mux_pcie1_clkreqn,
+ msm_mux_phase_flag,
+ msm_mux_pll_bist,
+ msm_mux_pll_clk,
+ msm_mux_pri_mi2s,
+ msm_mux_prng_rosc,
+ msm_mux_qdss_cti,
+ msm_mux_qdss_gpio,
+ msm_mux_qlink0_enable,
+ msm_mux_qlink0_request,
+ msm_mux_qlink0_wmss,
+ msm_mux_qlink1_enable,
+ msm_mux_qlink1_request,
+ msm_mux_qlink1_wmss,
+ msm_mux_qlink2_enable,
+ msm_mux_qlink2_request,
+ msm_mux_qlink2_wmss,
+ msm_mux_qspi0,
+ msm_mux_qspi1,
+ msm_mux_qspi2,
+ msm_mux_qspi3,
+ msm_mux_qspi_clk,
+ msm_mux_qspi_cs,
+ msm_mux_qup0,
+ msm_mux_qup1,
+ msm_mux_qup10,
+ msm_mux_qup11,
+ msm_mux_qup12,
+ msm_mux_qup13,
+ msm_mux_qup14,
+ msm_mux_qup15,
+ msm_mux_qup16,
+ msm_mux_qup17,
+ msm_mux_qup18,
+ msm_mux_qup19,
+ msm_mux_qup2,
+ msm_mux_qup3,
+ msm_mux_qup4,
+ msm_mux_qup5,
+ msm_mux_qup6,
+ msm_mux_qup7,
+ msm_mux_qup8,
+ msm_mux_qup9,
+ msm_mux_qup_l4,
+ msm_mux_qup_l5,
+ msm_mux_qup_l6,
+ msm_mux_sd_write,
+ msm_mux_sdc40,
+ msm_mux_sdc41,
+ msm_mux_sdc42,
+ msm_mux_sdc43,
+ msm_mux_sdc4_clk,
+ msm_mux_sdc4_cmd,
+ msm_mux_sec_mi2s,
+ msm_mux_tb_trig,
+ msm_mux_tgu_ch0,
+ msm_mux_tgu_ch1,
+ msm_mux_tgu_ch2,
+ msm_mux_tgu_ch3,
+ msm_mux_tsense_pwm1,
+ msm_mux_tsense_pwm2,
+ msm_mux_uim0_clk,
+ msm_mux_uim0_data,
+ msm_mux_uim0_present,
+ msm_mux_uim0_reset,
+ msm_mux_uim1_clk,
+ msm_mux_uim1_data,
+ msm_mux_uim1_present,
+ msm_mux_uim1_reset,
+ msm_mux_usb2phy_ac,
+ msm_mux_usb_phy,
+ msm_mux_vfr_0,
+ msm_mux_vfr_1,
+ msm_mux_vsense_trigger,
+ msm_mux__,
+};
+
+static const char * const gpio_groups[] = {
+ "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7",
+ "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14",
+ "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21",
+ "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28",
+ "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35",
+ "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42",
+ "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49",
+ "gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56",
+ "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63",
+ "gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69", "gpio70",
+ "gpio71", "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77",
+ "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", "gpio84",
+ "gpio85", "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", "gpio91",
+ "gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97", "gpio98",
+ "gpio99", "gpio100", "gpio101", "gpio102", "gpio103", "gpio104",
+ "gpio105", "gpio106", "gpio107", "gpio108", "gpio109", "gpio110",
+ "gpio111", "gpio112", "gpio113", "gpio114", "gpio115", "gpio116",
+ "gpio117", "gpio118", "gpio119", "gpio120", "gpio121", "gpio122",
+ "gpio123", "gpio124", "gpio125", "gpio126", "gpio127", "gpio128",
+ "gpio129", "gpio130", "gpio131", "gpio132", "gpio133", "gpio134",
+ "gpio135", "gpio136", "gpio137", "gpio138", "gpio139", "gpio140",
+ "gpio141", "gpio142", "gpio143", "gpio144", "gpio145", "gpio146",
+ "gpio147", "gpio148", "gpio149", "gpio150", "gpio151", "gpio152",
+ "gpio153", "gpio154", "gpio155", "gpio156", "gpio157", "gpio158",
+ "gpio159", "gpio160", "gpio161", "gpio162", "gpio163", "gpio164",
+ "gpio165", "gpio166", "gpio167", "gpio168", "gpio169", "gpio170",
+ "gpio171", "gpio172", "gpio173", "gpio174", "gpio175", "gpio176",
+ "gpio177", "gpio178", "gpio179", "gpio180", "gpio181", "gpio182",
+ "gpio183", "gpio184", "gpio185", "gpio186", "gpio187", "gpio188",
+ "gpio189", "gpio190", "gpio191", "gpio192", "gpio193", "gpio194",
+ "gpio195", "gpio196", "gpio197", "gpio198", "gpio199", "gpio200",
+ "gpio201", "gpio202",
+};
+
+static const char * const atest_char_groups[] = {
+ "gpio85", "gpio86", "gpio87", "gpio115", "gpio117",
+};
+
+static const char * const atest_usb_groups[] = {
+ "gpio55", "gpio80", "gpio81", "gpio151", "gpio152",
+ "gpio153", "gpio154", "gpio158", "gpio159", "gpio161",
+};
+
+static const char * const audio_ref_groups[] = {
+ "gpio124",
+};
+
+static const char * const cam_mclk_groups[] = {
+ "gpio100", "gpio101", "gpio102", "gpio103", "gpio104", "gpio105",
+};
+
+static const char * const cci_async_groups[] = {
+ "gpio106", "gpio118", "gpio119",
+};
+
+static const char * const cci_i2c_groups[] = {
+ "gpio107", "gpio108", "gpio109", "gpio110", "gpio111", "gpio112",
+ "gpio113", "gpio114",
+};
+
+static const char * const cci_timer_groups[] = {
+ "gpio115", "gpio116", "gpio117", "gpio118", "gpio119",
+};
+
+static const char * const cmu_rng_groups[] = {
+ "gpio174", "gpio175", "gpio176", "gpio177",
+};
+
+static const char * const coex_uart1_groups[] = {
+ "gpio151", "gpio152",
+};
+
+static const char * const coex_uart2_groups[] = {
+ "gpio153", "gpio154",
+};
+
+static const char * const cri_trng_groups[] = {
+ "gpio186",
+};
+
+static const char * const cri_trng0_groups[] = {
+ "gpio183",
+};
+
+static const char * const cri_trng1_groups[] = {
+ "gpio184",
+};
+
+static const char * const dbg_out_groups[] = {
+ "gpio14",
+};
+
+static const char * const ddr_bist_groups[] = {
+ "gpio36", "gpio37", "gpio40", "gpio41",
+};
+
+static const char * const ddr_pxi0_groups[] = {
+ "gpio51", "gpio52",
+};
+
+static const char * const ddr_pxi1_groups[] = {
+ "gpio48", "gpio49",
+};
+
+static const char * const ddr_pxi2_groups[] = {
+ "gpio45", "gpio47",
+};
+
+static const char * const ddr_pxi3_groups[] = {
+ "gpio43", "gpio44",
+};
+
+static const char * const dp_hot_groups[] = {
+ "gpio87",
+};
+
+static const char * const dp_lcd_groups[] = {
+ "gpio83",
+};
+
+static const char * const gcc_gp1_groups[] = {
+ "gpio115", "gpio129",
+};
+
+static const char * const gcc_gp2_groups[] = {
+ "gpio116", "gpio130",
+};
+
+static const char * const gcc_gp3_groups[] = {
+ "gpio117", "gpio131",
+};
+
+static const char * const ibi_i3c_groups[] = {
+ "gpio36", "gpio37", "gpio56", "gpio57", "gpio60", "gpio61",
+};
+
+static const char * const jitter_bist_groups[] = {
+ "gpio80",
+};
+
+static const char * const lpass_slimbus_groups[] = {
+ "gpio129", "gpio130",
+};
+
+static const char * const mdp_vsync_groups[] = {
+ "gpio15", "gpio26", "gpio82", "gpio83", "gpio84",
+};
+
+static const char * const mdp_vsync0_groups[] = {
+ "gpio86",
+};
+
+static const char * const mdp_vsync1_groups[] = {
+ "gpio86",
+};
+
+static const char * const mdp_vsync2_groups[] = {
+ "gpio87",
+};
+
+static const char * const mdp_vsync3_groups[] = {
+ "gpio87",
+};
+
+static const char * const mi2s0_data0_groups[] = {
+ "gpio126",
+};
+
+static const char * const mi2s0_data1_groups[] = {
+ "gpio127",
+};
+
+static const char * const mi2s0_sck_groups[] = {
+ "gpio125",
+};
+
+static const char * const mi2s0_ws_groups[] = {
+ "gpio128",
+};
+
+static const char * const mi2s1_data0_groups[] = {
+ "gpio130",
+};
+
+static const char * const mi2s1_data1_groups[] = {
+ "gpio131",
+};
+
+static const char * const mi2s1_sck_groups[] = {
+ "gpio129",
+};
+
+static const char * const mi2s1_ws_groups[] = {
+ "gpio132",
+};
+
+static const char * const mi2s2_data0_groups[] = {
+ "gpio121",
+};
+
+static const char * const mi2s2_data1_groups[] = {
+ "gpio124",
+};
+
+static const char * const mi2s2_sck_groups[] = {
+ "gpio120",
+};
+
+static const char * const mi2s2_ws_groups[] = {
+ "gpio122",
+};
+
+static const char * const mss_grfc0_groups[] = {
+ "gpio141", "gpio158",
+};
+
+static const char * const mss_grfc1_groups[] = {
+ "gpio142",
+};
+
+static const char * const mss_grfc10_groups[] = {
+ "gpio153",
+};
+
+static const char * const mss_grfc11_groups[] = {
+ "gpio154",
+};
+
+static const char * const mss_grfc12_groups[] = {
+ "gpio157",
+};
+
+static const char * const mss_grfc2_groups[] = {
+ "gpio143",
+};
+
+static const char * const mss_grfc3_groups[] = {
+ "gpio144",
+};
+
+static const char * const mss_grfc4_groups[] = {
+ "gpio145",
+};
+
+static const char * const mss_grfc5_groups[] = {
+ "gpio146",
+};
+
+static const char * const mss_grfc6_groups[] = {
+ "gpio147",
+};
+
+static const char * const mss_grfc7_groups[] = {
+ "gpio148",
+};
+
+static const char * const mss_grfc8_groups[] = {
+ "gpio149",
+};
+
+static const char * const mss_grfc9_groups[] = {
+ "gpio150",
+};
+
+static const char * const nav_gpio_groups[] = {
+ "gpio155", "gpio156", "gpio157",
+};
+
+static const char * const pa_indicator_groups[] = {
+ "gpio157",
+};
+
+static const char * const pcie0_clkreqn_groups[] = {
+ "gpio95",
+};
+
+static const char * const pcie1_clkreqn_groups[] = {
+ "gpio98",
+};
+
+static const char * const phase_flag_groups[] = {
+ "gpio12", "gpio13", "gpio16", "gpio17", "gpio28", "gpio29", "gpio30",
+ "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", "gpio72", "gpio73",
+ "gpio74", "gpio75", "gpio76", "gpio77", "gpio78", "gpio79", "gpio103",
+ "gpio104", "gpio105", "gpio106", "gpio107", "gpio108", "gpio109",
+ "gpio110", "gpio111", "gpio112", "gpio113", "gpio114",
+};
+
+static const char * const pll_bist_groups[] = {
+ "gpio81",
+};
+
+static const char * const pll_clk_groups[] = {
+ "gpio81",
+};
+
+static const char * const pri_mi2s_groups[] = {
+ "gpio123",
+};
+
+static const char * const prng_rosc_groups[] = {
+ "gpio185",
+};
+
+static const char * const qdss_cti_groups[] = {
+ "gpio14", "gpio27", "gpio87", "gpio88", "gpio89", "gpio90", "gpio91", "gpio92",
+};
+
+static const char * const qdss_gpio_groups[] = {
+ "gpio100", "gpio101", "gpio102", "gpio103", "gpio104", "gpio105", "gpio106", "gpio107",
+ "gpio108", "gpio109", "gpio110", "gpio111", "gpio112", "gpio113", "gpio114", "gpio115",
+ "gpio116", "gpio117", "gpio183", "gpio184", "gpio185", "gpio186", "gpio187", "gpio188",
+ "gpio189", "gpio190", "gpio191", "gpio192", "gpio193", "gpio194", "gpio195", "gpio196",
+ "gpio197", "gpio198", "gpio199", "gpio200",
+};
+
+static const char * const qlink0_enable_groups[] = {
+ "gpio160",
+};
+
+static const char * const qlink0_request_groups[] = {
+ "gpio159",
+};
+
+static const char * const qlink0_wmss_groups[] = {
+ "gpio161",
+};
+
+static const char * const qlink1_enable_groups[] = {
+ "gpio163",
+};
+
+static const char * const qlink1_request_groups[] = {
+ "gpio162",
+};
+
+static const char * const qlink1_wmss_groups[] = {
+ "gpio164",
+};
+
+static const char * const qlink2_enable_groups[] = {
+ "gpio166",
+};
+
+static const char * const qlink2_request_groups[] = {
+ "gpio165",
+};
+
+static const char * const qlink2_wmss_groups[] = {
+ "gpio167",
+};
+
+static const char * const qspi0_groups[] = {
+ "gpio44",
+};
+
+static const char * const qspi1_groups[] = {
+ "gpio45",
+};
+
+static const char * const qspi2_groups[] = {
+ "gpio48",
+};
+
+static const char * const qspi3_groups[] = {
+ "gpio49",
+};
+
+static const char * const qspi_clk_groups[] = {
+ "gpio50",
+};
+
+static const char * const qspi_cs_groups[] = {
+ "gpio47", "gpio51",
+};
+
+static const char * const qup0_groups[] = {
+ "gpio4", "gpio5", "gpio6", "gpio7",
+};
+
+static const char * const qup1_groups[] = {
+ "gpio8", "gpio9", "gpio10", "gpio11",
+};
+
+static const char * const qup10_groups[] = {
+ "gpio44", "gpio45", "gpio46", "gpio47",
+};
+
+static const char * const qup11_groups[] = {
+ "gpio48", "gpio49", "gpio50", "gpio51",
+};
+
+static const char * const qup12_groups[] = {
+ "gpio52", "gpio53", "gpio54", "gpio55",
+};
+
+static const char * const qup13_groups[] = {
+ "gpio0", "gpio1", "gpio2", "gpio3",
+};
+
+static const char * const qup14_groups[] = {
+ "gpio56", "gpio57", "gpio58", "gpio59",
+};
+
+static const char * const qup15_groups[] = {
+ "gpio60", "gpio61", "gpio62", "gpio63",
+};
+
+static const char * const qup16_groups[] = {
+ "gpio64", "gpio65", "gpio66", "gpio67",
+};
+
+static const char * const qup17_groups[] = {
+ "gpio72", "gpio73", "gpio74", "gpio75",
+};
+
+static const char * const qup18_groups[] = {
+ "gpio68", "gpio69", "gpio70", "gpio71",
+};
+
+static const char * const qup19_groups[] = {
+ "gpio76", "gpio77", "gpio78", "gpio79",
+};
+
+static const char * const qup2_groups[] = {
+ "gpio12", "gpio13", "gpio14", "gpio15",
+};
+
+static const char * const qup3_groups[] = {
+ "gpio16", "gpio17", "gpio18", "gpio19",
+};
+
+static const char * const qup4_groups[] = {
+ "gpio20", "gpio21", "gpio22", "gpio23",
+};
+
+static const char * const qup5_groups[] = {
+ "gpio24", "gpio25", "gpio26", "gpio27",
+};
+
+static const char * const qup6_groups[] = {
+ "gpio28", "gpio29", "gpio30", "gpio31",
+};
+
+static const char * const qup7_groups[] = {
+ "gpio32", "gpio33", "gpio34", "gpio35",
+};
+
+static const char * const qup8_groups[] = {
+ "gpio36", "gpio37", "gpio38", "gpio39",
+};
+
+static const char * const qup9_groups[] = {
+ "gpio40", "gpio41", "gpio42", "gpio43",
+};
+
+static const char * const qup_l4_groups[] = {
+ "gpio2", "gpio6", "gpio58", "gpio63",
+};
+
+static const char * const qup_l5_groups[] = {
+ "gpio3", "gpio7", "gpio59", "gpio66",
+};
+
+static const char * const qup_l6_groups[] = {
+ "gpio10", "gpio42", "gpio62", "gpio67",
+};
+
+static const char * const sd_write_groups[] = {
+ "gpio93",
+};
+
+static const char * const sdc40_groups[] = {
+ "gpio44",
+};
+
+static const char * const sdc41_groups[] = {
+ "gpio45",
+};
+
+static const char * const sdc42_groups[] = {
+ "gpio48",
+};
+
+static const char * const sdc43_groups[] = {
+ "gpio49",
+};
+
+static const char * const sdc4_clk_groups[] = {
+ "gpio50",
+};
+
+static const char * const sdc4_cmd_groups[] = {
+ "gpio51",
+};
+
+static const char * const sec_mi2s_groups[] = {
+ "gpio124",
+};
+
+static const char * const tb_trig_groups[] = {
+ "gpio64", "gpio136",
+};
+
+static const char * const tgu_ch0_groups[] = {
+ "gpio99",
+};
+
+static const char * const tgu_ch1_groups[] = {
+ "gpio100",
+};
+
+static const char * const tgu_ch2_groups[] = {
+ "gpio101",
+};
+
+static const char * const tgu_ch3_groups[] = {
+ "gpio102",
+};
+
+static const char * const tsense_pwm1_groups[] = {
+ "gpio88",
+};
+
+static const char * const tsense_pwm2_groups[] = {
+ "gpio88",
+};
+
+static const char * const uim0_clk_groups[] = {
+ "gpio138",
+};
+
+static const char * const uim0_data_groups[] = {
+ "gpio137",
+};
+
+static const char * const uim0_present_groups[] = {
+ "gpio140",
+};
+
+static const char * const uim0_reset_groups[] = {
+ "gpio139",
+};
+
+static const char * const uim1_clk_groups[] = {
+ "gpio134",
+};
+
+static const char * const uim1_data_groups[] = {
+ "gpio133",
+};
+
+static const char * const uim1_present_groups[] = {
+ "gpio136",
+};
+
+static const char * const uim1_reset_groups[] = {
+ "gpio135",
+};
+
+static const char * const usb2phy_ac_groups[] = {
+ "gpio39", "gpio80",
+};
+
+static const char * const usb_phy_groups[] = {
+ "gpio81",
+};
+
+static const char * const vfr_0_groups[] = {
+ "gpio84",
+};
+
+static const char * const vfr_1_groups[] = {
+ "gpio90",
+};
+
+static const char * const vsense_trigger_groups[] = {
+ "gpio78",
+};
+
+static const struct msm_function sm8350_functions[] = {
+ FUNCTION(atest_char),
+ FUNCTION(atest_usb),
+ FUNCTION(audio_ref),
+ FUNCTION(cam_mclk),
+ FUNCTION(cci_async),
+ FUNCTION(cci_i2c),
+ FUNCTION(cci_timer),
+ FUNCTION(cmu_rng),
+ FUNCTION(coex_uart1),
+ FUNCTION(coex_uart2),
+ FUNCTION(cri_trng),
+ FUNCTION(cri_trng0),
+ FUNCTION(cri_trng1),
+ FUNCTION(dbg_out),
+ FUNCTION(ddr_bist),
+ FUNCTION(ddr_pxi0),
+ FUNCTION(ddr_pxi1),
+ FUNCTION(ddr_pxi2),
+ FUNCTION(ddr_pxi3),
+ FUNCTION(dp_hot),
+ FUNCTION(dp_lcd),
+ FUNCTION(gcc_gp1),
+ FUNCTION(gcc_gp2),
+ FUNCTION(gcc_gp3),
+ FUNCTION(gpio),
+ FUNCTION(ibi_i3c),
+ FUNCTION(jitter_bist),
+ FUNCTION(lpass_slimbus),
+ FUNCTION(mdp_vsync),
+ FUNCTION(mdp_vsync0),
+ FUNCTION(mdp_vsync1),
+ FUNCTION(mdp_vsync2),
+ FUNCTION(mdp_vsync3),
+ FUNCTION(mi2s0_data0),
+ FUNCTION(mi2s0_data1),
+ FUNCTION(mi2s0_sck),
+ FUNCTION(mi2s0_ws),
+ FUNCTION(mi2s1_data0),
+ FUNCTION(mi2s1_data1),
+ FUNCTION(mi2s1_sck),
+ FUNCTION(mi2s1_ws),
+ FUNCTION(mi2s2_data0),
+ FUNCTION(mi2s2_data1),
+ FUNCTION(mi2s2_sck),
+ FUNCTION(mi2s2_ws),
+ FUNCTION(mss_grfc0),
+ FUNCTION(mss_grfc1),
+ FUNCTION(mss_grfc10),
+ FUNCTION(mss_grfc11),
+ FUNCTION(mss_grfc12),
+ FUNCTION(mss_grfc2),
+ FUNCTION(mss_grfc3),
+ FUNCTION(mss_grfc4),
+ FUNCTION(mss_grfc5),
+ FUNCTION(mss_grfc6),
+ FUNCTION(mss_grfc7),
+ FUNCTION(mss_grfc8),
+ FUNCTION(mss_grfc9),
+ FUNCTION(nav_gpio),
+ FUNCTION(pa_indicator),
+ FUNCTION(pcie0_clkreqn),
+ FUNCTION(pcie1_clkreqn),
+ FUNCTION(phase_flag),
+ FUNCTION(pll_bist),
+ FUNCTION(pll_clk),
+ FUNCTION(pri_mi2s),
+ FUNCTION(prng_rosc),
+ FUNCTION(qdss_cti),
+ FUNCTION(qdss_gpio),
+ FUNCTION(qlink0_enable),
+ FUNCTION(qlink0_request),
+ FUNCTION(qlink0_wmss),
+ FUNCTION(qlink1_enable),
+ FUNCTION(qlink1_request),
+ FUNCTION(qlink1_wmss),
+ FUNCTION(qlink2_enable),
+ FUNCTION(qlink2_request),
+ FUNCTION(qlink2_wmss),
+ FUNCTION(qspi0),
+ FUNCTION(qspi1),
+ FUNCTION(qspi2),
+ FUNCTION(qspi3),
+ FUNCTION(qspi_clk),
+ FUNCTION(qspi_cs),
+ FUNCTION(qup0),
+ FUNCTION(qup1),
+ FUNCTION(qup10),
+ FUNCTION(qup11),
+ FUNCTION(qup12),
+ FUNCTION(qup13),
+ FUNCTION(qup14),
+ FUNCTION(qup15),
+ FUNCTION(qup16),
+ FUNCTION(qup17),
+ FUNCTION(qup18),
+ FUNCTION(qup19),
+ FUNCTION(qup2),
+ FUNCTION(qup3),
+ FUNCTION(qup4),
+ FUNCTION(qup5),
+ FUNCTION(qup6),
+ FUNCTION(qup7),
+ FUNCTION(qup8),
+ FUNCTION(qup9),
+ FUNCTION(qup_l4),
+ FUNCTION(qup_l5),
+ FUNCTION(qup_l6),
+ FUNCTION(sd_write),
+ FUNCTION(sdc40),
+ FUNCTION(sdc41),
+ FUNCTION(sdc42),
+ FUNCTION(sdc43),
+ FUNCTION(sdc4_clk),
+ FUNCTION(sdc4_cmd),
+ FUNCTION(sec_mi2s),
+ FUNCTION(tb_trig),
+ FUNCTION(tgu_ch0),
+ FUNCTION(tgu_ch1),
+ FUNCTION(tgu_ch2),
+ FUNCTION(tgu_ch3),
+ FUNCTION(tsense_pwm1),
+ FUNCTION(tsense_pwm2),
+ FUNCTION(uim0_clk),
+ FUNCTION(uim0_data),
+ FUNCTION(uim0_present),
+ FUNCTION(uim0_reset),
+ FUNCTION(uim1_clk),
+ FUNCTION(uim1_data),
+ FUNCTION(uim1_present),
+ FUNCTION(uim1_reset),
+ FUNCTION(usb2phy_ac),
+ FUNCTION(usb_phy),
+ FUNCTION(vfr_0),
+ FUNCTION(vfr_1),
+ FUNCTION(vsense_trigger),
+};
+
+/* Every pin is maintained as a single group, and missing or non-existing pin
+ * would be maintained as dummy group to synchronize pin group index with
+ * pin descriptor registered with pinctrl core.
+ * Clients would not be able to request these dummy pin groups.
+ */
+static const struct msm_pingroup sm8350_groups[] = {
+ [0] = PINGROUP(0, qup13, _, _, _, _, _, _, _, _),
+ [1] = PINGROUP(1, qup13, _, _, _, _, _, _, _, _),
+ [2] = PINGROUP(2, qup13, qup_l4, _, _, _, _, _, _, _),
+ [3] = PINGROUP(3, qup13, qup_l5, _, _, _, _, _, _, _),
+ [4] = PINGROUP(4, qup0, _, _, _, _, _, _, _, _),
+ [5] = PINGROUP(5, qup0, _, _, _, _, _, _, _, _),
+ [6] = PINGROUP(6, qup0, qup_l4, _, _, _, _, _, _, _),
+ [7] = PINGROUP(7, qup0, qup_l5, _, _, _, _, _, _, _),
+ [8] = PINGROUP(8, qup1, _, _, _, _, _, _, _, _),
+ [9] = PINGROUP(9, qup1, _, _, _, _, _, _, _, _),
+ [10] = PINGROUP(10, qup1, qup_l6, _, _, _, _, _, _, _),
+ [11] = PINGROUP(11, qup1, _, _, _, _, _, _, _, _),
+ [12] = PINGROUP(12, qup2, phase_flag, _, _, _, _, _, _, _),
+ [13] = PINGROUP(13, qup2, phase_flag, _, _, _, _, _, _, _),
+ [14] = PINGROUP(14, qup2, qdss_cti, dbg_out, _, _, _, _, _, _),
+ [15] = PINGROUP(15, qup2, mdp_vsync, _, _, _, _, _, _, _),
+ [16] = PINGROUP(16, qup3, phase_flag, _, _, _, _, _, _, _),
+ [17] = PINGROUP(17, qup3, phase_flag, _, _, _, _, _, _, _),
+ [18] = PINGROUP(18, qup3, _, _, _, _, _, _, _, _),
+ [19] = PINGROUP(19, qup3, _, _, _, _, _, _, _, _),
+ [20] = PINGROUP(20, qup4, _, _, _, _, _, _, _, _),
+ [21] = PINGROUP(21, qup4, _, _, _, _, _, _, _, _),
+ [22] = PINGROUP(22, qup4, _, _, _, _, _, _, _, _),
+ [23] = PINGROUP(23, qup4, _, _, _, _, _, _, _, _),
+ [24] = PINGROUP(24, qup5, _, _, _, _, _, _, _, _),
+ [25] = PINGROUP(25, qup5, _, _, _, _, _, _, _, _),
+ [26] = PINGROUP(26, qup5, mdp_vsync, _, _, _, _, _, _, _),
+ [27] = PINGROUP(27, qup5, qdss_cti, _, _, _, _, _, _, _),
+ [28] = PINGROUP(28, qup6, phase_flag, _, _, _, _, _, _, _),
+ [29] = PINGROUP(29, qup6, phase_flag, _, _, _, _, _, _, _),
+ [30] = PINGROUP(30, qup6, phase_flag, _, _, _, _, _, _, _),
+ [31] = PINGROUP(31, qup6, phase_flag, _, _, _, _, _, _, _),
+ [32] = PINGROUP(32, qup7, phase_flag, _, _, _, _, _, _, _),
+ [33] = PINGROUP(33, qup7, phase_flag, _, _, _, _, _, _, _),
+ [34] = PINGROUP(34, qup7, phase_flag, _, _, _, _, _, _, _),
+ [35] = PINGROUP(35, qup7, phase_flag, _, _, _, _, _, _, _),
+ [36] = PINGROUP(36, qup8, ibi_i3c, ddr_bist, _, _, _, _, _, _),
+ [37] = PINGROUP(37, qup8, ibi_i3c, ddr_bist, _, _, _, _, _, _),
+ [38] = PINGROUP(38, qup8, _, _, _, _, _, _, _, _),
+ [39] = PINGROUP(39, qup8, usb2phy_ac, _, _, _, _, _, _, _),
+ [40] = PINGROUP(40, qup9, ddr_bist, _, _, _, _, _, _, _),
+ [41] = PINGROUP(41, qup9, ddr_bist, _, _, _, _, _, _, _),
+ [42] = PINGROUP(42, qup9, qup_l6, _, _, _, _, _, _, _),
+ [43] = PINGROUP(43, qup9, ddr_pxi3, _, _, _, _, _, _, _),
+ [44] = PINGROUP(44, qup10, qspi0, sdc40, ddr_pxi3, _, _, _, _, _),
+ [45] = PINGROUP(45, qup10, qspi1, sdc41, ddr_pxi2, _, _, _, _, _),
+ [46] = PINGROUP(46, qup10, _, _, _, _, _, _, _, _),
+ [47] = PINGROUP(47, qup10, qspi_cs, ddr_pxi2, _, _, _, _, _, _),
+ [48] = PINGROUP(48, qup11, qspi2, sdc42, ddr_pxi1, _, _, _, _, _),
+ [49] = PINGROUP(49, qup11, qspi3, sdc43, ddr_pxi1, _, _, _, _, _),
+ [50] = PINGROUP(50, qup11, qspi_clk, sdc4_clk, _, _, _, _, _, _),
+ [51] = PINGROUP(51, qup11, qspi_cs, sdc4_cmd, ddr_pxi0, _, _, _, _, _),
+ [52] = PINGROUP(52, qup12, ddr_pxi0, _, _, _, _, _, _, _),
+ [53] = PINGROUP(53, qup12, _, _, _, _, _, _, _, _),
+ [54] = PINGROUP(54, qup12, _, _, _, _, _, _, _, _),
+ [55] = PINGROUP(55, qup12, atest_usb, _, _, _, _, _, _, _),
+ [56] = PINGROUP(56, qup14, ibi_i3c, _, _, _, _, _, _, _),
+ [57] = PINGROUP(57, qup14, ibi_i3c, _, _, _, _, _, _, _),
+ [58] = PINGROUP(58, qup14, qup_l4, _, _, _, _, _, _, _),
+ [59] = PINGROUP(59, qup14, qup_l5, _, _, _, _, _, _, _),
+ [60] = PINGROUP(60, qup15, ibi_i3c, _, _, _, _, _, _, _),
+ [61] = PINGROUP(61, qup15, ibi_i3c, _, _, _, _, _, _, _),
+ [62] = PINGROUP(62, qup15, qup_l6, _, _, _, _, _, _, _),
+ [63] = PINGROUP(63, qup15, qup_l4, _, _, _, _, _, _, _),
+ [64] = PINGROUP(64, qup16, tb_trig, _, _, _, _, _, _, _),
+ [65] = PINGROUP(65, qup16, _, _, _, _, _, _, _, _),
+ [66] = PINGROUP(66, qup16, qup_l5, _, _, _, _, _, _, _),
+ [67] = PINGROUP(67, qup16, qup_l6, _, _, _, _, _, _, _),
+ [68] = PINGROUP(68, qup18, _, _, _, _, _, _, _, _),
+ [69] = PINGROUP(69, qup18, _, _, _, _, _, _, _, _),
+ [70] = PINGROUP(70, qup18, _, _, _, _, _, _, _, _),
+ [71] = PINGROUP(71, qup18, _, _, _, _, _, _, _, _),
+ [72] = PINGROUP(72, qup17, phase_flag, _, _, _, _, _, _, _),
+ [73] = PINGROUP(73, qup17, phase_flag, _, _, _, _, _, _, _),
+ [74] = PINGROUP(74, qup17, phase_flag, _, _, _, _, _, _, _),
+ [75] = PINGROUP(75, qup17, phase_flag, _, _, _, _, _, _, _),
+ [76] = PINGROUP(76, qup19, phase_flag, _, _, _, _, _, _, _),
+ [77] = PINGROUP(77, qup19, phase_flag, _, _, _, _, _, _, _),
+ [78] = PINGROUP(78, qup19, phase_flag, _, vsense_trigger, _, _, _, _, _),
+ [79] = PINGROUP(79, qup19, phase_flag, _, _, _, _, _, _, _),
+ [80] = PINGROUP(80, usb2phy_ac, jitter_bist, atest_usb, _, _, _, _, _, _),
+ [81] = PINGROUP(81, usb_phy, pll_bist, pll_clk, atest_usb, _, _, _, _, _),
+ [82] = PINGROUP(82, mdp_vsync, _, _, _, _, _, _, _, _),
+ [83] = PINGROUP(83, mdp_vsync, dp_lcd, _, _, _, _, _, _, _),
+ [84] = PINGROUP(84, mdp_vsync, vfr_0, _, _, _, _, _, _, _),
+ [85] = PINGROUP(85, atest_char, _, _, _, _, _, _, _, _),
+ [86] = PINGROUP(86, mdp_vsync0, mdp_vsync1, atest_char, _, _, _, _, _, _),
+ [87] = PINGROUP(87, dp_hot, mdp_vsync2, mdp_vsync3, qdss_cti, atest_char, _, _, _, _),
+ [88] = PINGROUP(88, qdss_cti, tsense_pwm1, tsense_pwm2, _, _, _, _, _, _),
+ [89] = PINGROUP(89, qdss_cti, _, _, _, _, _, _, _, _),
+ [90] = PINGROUP(90, vfr_1, qdss_cti, _, _, _, _, _, _, _),
+ [91] = PINGROUP(91, qdss_cti, _, _, _, _, _, _, _, _),
+ [92] = PINGROUP(92, qdss_cti, _, _, _, _, _, _, _, _),
+ [93] = PINGROUP(93, sd_write, _, _, _, _, _, _, _, _),
+ [94] = PINGROUP(94, _, _, _, _, _, _, _, _, _),
+ [95] = PINGROUP(95, pcie0_clkreqn, _, _, _, _, _, _, _, _),
+ [96] = PINGROUP(96, _, _, _, _, _, _, _, _, _),
+ [97] = PINGROUP(97, _, _, _, _, _, _, _, _, _),
+ [98] = PINGROUP(98, pcie1_clkreqn, _, _, _, _, _, _, _, _),
+ [99] = PINGROUP(99, tgu_ch0, _, _, _, _, _, _, _, _),
+ [100] = PINGROUP(100, cam_mclk, tgu_ch1, qdss_gpio, _, _, _, _, _, _),
+ [101] = PINGROUP(101, cam_mclk, tgu_ch2, qdss_gpio, _, _, _, _, _, _),
+ [102] = PINGROUP(102, cam_mclk, tgu_ch3, qdss_gpio, _, _, _, _, _, _),
+ [103] = PINGROUP(103, cam_mclk, phase_flag, _, qdss_gpio, _, _, _, _, _),
+ [104] = PINGROUP(104, cam_mclk, phase_flag, _, qdss_gpio, _, _, _, _, _),
+ [105] = PINGROUP(105, cam_mclk, phase_flag, _, qdss_gpio, _, _, _, _, _),
+ [106] = PINGROUP(106, cci_async, phase_flag, _, qdss_gpio, _, _, _, _, _),
+ [107] = PINGROUP(107, cci_i2c, phase_flag, _, qdss_gpio, _, _, _, _, _),
+ [108] = PINGROUP(108, cci_i2c, phase_flag, _, qdss_gpio, _, _, _, _, _),
+ [109] = PINGROUP(109, cci_i2c, phase_flag, _, qdss_gpio, _, _, _, _, _),
+ [110] = PINGROUP(110, cci_i2c, phase_flag, _, qdss_gpio, _, _, _, _, _),
+ [111] = PINGROUP(111, cci_i2c, phase_flag, _, qdss_gpio, _, _, _, _, _),
+ [112] = PINGROUP(112, cci_i2c, phase_flag, _, qdss_gpio, _, _, _, _, _),
+ [113] = PINGROUP(113, cci_i2c, phase_flag, _, qdss_gpio, _, _, _, _, _),
+ [114] = PINGROUP(114, cci_i2c, phase_flag, _, qdss_gpio, _, _, _, _, _),
+ [115] = PINGROUP(115, cci_timer, gcc_gp1, qdss_gpio, atest_char, _, _, _, _, _),
+ [116] = PINGROUP(116, cci_timer, gcc_gp2, qdss_gpio, _, _, _, _, _, _),
+ [117] = PINGROUP(117, cci_timer, gcc_gp3, qdss_gpio, atest_char, _, _, _, _, _),
+ [118] = PINGROUP(118, cci_timer, cci_async, _, _, _, _, _, _, _),
+ [119] = PINGROUP(119, cci_timer, cci_async, _, _, _, _, _, _, _),
+ [120] = PINGROUP(120, mi2s2_sck, _, _, _, _, _, _, _, _),
+ [121] = PINGROUP(121, mi2s2_data0, _, _, _, _, _, _, _, _),
+ [122] = PINGROUP(122, mi2s2_ws, _, _, _, _, _, _, _, _),
+ [123] = PINGROUP(123, pri_mi2s, _, _, _, _, _, _, _, _),
+ [124] = PINGROUP(124, sec_mi2s, audio_ref, mi2s2_data1, _, _, _, _, _, _),
+ [125] = PINGROUP(125, mi2s0_sck, _, _, _, _, _, _, _, _),
+ [126] = PINGROUP(126, mi2s0_data0, _, _, _, _, _, _, _, _),
+ [127] = PINGROUP(127, mi2s0_data1, _, _, _, _, _, _, _, _),
+ [128] = PINGROUP(128, mi2s0_ws, _, _, _, _, _, _, _, _),
+ [129] = PINGROUP(129, lpass_slimbus, mi2s1_sck, gcc_gp1, _, _, _, _, _, _),
+ [130] = PINGROUP(130, lpass_slimbus, mi2s1_data0, gcc_gp2, _, _, _, _, _, _),
+ [131] = PINGROUP(131, mi2s1_data1, gcc_gp3, _, _, _, _, _, _, _),
+ [132] = PINGROUP(132, mi2s1_ws, _, _, _, _, _, _, _, _),
+ [133] = PINGROUP(133, uim1_data, _, _, _, _, _, _, _, _),
+ [134] = PINGROUP(134, uim1_clk, _, _, _, _, _, _, _, _),
+ [135] = PINGROUP(135, uim1_reset, _, _, _, _, _, _, _, _),
+ [136] = PINGROUP(136, uim1_present, tb_trig, _, _, _, _, _, _, _),
+ [137] = PINGROUP(137, uim0_data, _, _, _, _, _, _, _, _),
+ [138] = PINGROUP(138, uim0_clk, _, _, _, _, _, _, _, _),
+ [139] = PINGROUP(139, uim0_reset, _, _, _, _, _, _, _, _),
+ [140] = PINGROUP(140, uim0_present, _, _, _, _, _, _, _, _),
+ [141] = PINGROUP(141, _, mss_grfc0, _, _, _, _, _, _, _),
+ [142] = PINGROUP(142, _, mss_grfc1, _, _, _, _, _, _, _),
+ [143] = PINGROUP(143, _, mss_grfc2, _, _, _, _, _, _, _),
+ [144] = PINGROUP(144, _, mss_grfc3, _, _, _, _, _, _, _),
+ [145] = PINGROUP(145, _, mss_grfc4, _, _, _, _, _, _, _),
+ [146] = PINGROUP(146, _, mss_grfc5, _, _, _, _, _, _, _),
+ [147] = PINGROUP(147, _, mss_grfc6, _, _, _, _, _, _, _),
+ [148] = PINGROUP(148, _, mss_grfc7, _, _, _, _, _, _, _),
+ [149] = PINGROUP(149, _, mss_grfc8, _, _, _, _, _, _, _),
+ [150] = PINGROUP(150, _, mss_grfc9, _, _, _, _, _, _, _),
+ [151] = PINGROUP(151, coex_uart1, atest_usb, _, _, _, _, _, _, _),
+ [152] = PINGROUP(152, coex_uart1, atest_usb, _, _, _, _, _, _, _),
+ [153] = PINGROUP(153, coex_uart2, mss_grfc10, atest_usb, _, _, _, _, _, _),
+ [154] = PINGROUP(154, coex_uart2, mss_grfc11, atest_usb, _, _, _, _, _, _),
+ [155] = PINGROUP(155, nav_gpio, _, _, _, _, _, _, _, _),
+ [156] = PINGROUP(156, nav_gpio, _, _, _, _, _, _, _, _),
+ [157] = PINGROUP(157, mss_grfc12, pa_indicator, nav_gpio, _, _, _, _, _, _),
+ [158] = PINGROUP(158, mss_grfc0, atest_usb, _, _, _, _, _, _, _),
+ [159] = PINGROUP(159, qlink0_request, atest_usb, _, _, _, _, _, _, _),
+ [160] = PINGROUP(160, qlink0_enable, _, _, _, _, _, _, _, _),
+ [161] = PINGROUP(161, qlink0_wmss, atest_usb, _, _, _, _, _, _, _),
+ [162] = PINGROUP(162, qlink1_request, _, _, _, _, _, _, _, _),
+ [163] = PINGROUP(163, qlink1_enable, _, _, _, _, _, _, _, _),
+ [164] = PINGROUP(164, qlink1_wmss, _, _, _, _, _, _, _, _),
+ [165] = PINGROUP(165, qlink2_request, _, _, _, _, _, _, _, _),
+ [166] = PINGROUP(166, qlink2_enable, _, _, _, _, _, _, _, _),
+ [167] = PINGROUP(167, qlink2_wmss, _, _, _, _, _, _, _, _),
+ [168] = PINGROUP(168, _, _, _, _, _, _, _, _, _),
+ [169] = PINGROUP(169, _, _, _, _, _, _, _, _, _),
+ [170] = PINGROUP(170, _, _, _, _, _, _, _, _, _),
+ [171] = PINGROUP(171, _, _, _, _, _, _, _, _, _),
+ [172] = PINGROUP(172, _, _, _, _, _, _, _, _, _),
+ [173] = PINGROUP(173, _, _, _, _, _, _, _, _, _),
+ [174] = PINGROUP(174, cmu_rng, _, _, _, _, _, _, _, _),
+ [175] = PINGROUP(175, cmu_rng, _, _, _, _, _, _, _, _),
+ [176] = PINGROUP(176, cmu_rng, _, _, _, _, _, _, _, _),
+ [177] = PINGROUP(177, cmu_rng, _, _, _, _, _, _, _, _),
+ [178] = PINGROUP(178, _, _, _, _, _, _, _, _, _),
+ [179] = PINGROUP(179, _, _, _, _, _, _, _, _, _),
+ [180] = PINGROUP(180, _, _, _, _, _, _, _, _, _),
+ [181] = PINGROUP(181, _, _, _, _, _, _, _, _, _),
+ [182] = PINGROUP(182, _, _, _, _, _, _, _, _, _),
+ [183] = PINGROUP(183, cri_trng0, qdss_gpio, _, _, _, _, _, _, _),
+ [184] = PINGROUP(184, cri_trng1, qdss_gpio, _, _, _, _, _, _, _),
+ [185] = PINGROUP(185, prng_rosc, qdss_gpio, _, _, _, _, _, _, _),
+ [186] = PINGROUP(186, cri_trng, qdss_gpio, _, _, _, _, _, _, _),
+ [187] = PINGROUP(187, qdss_gpio, _, _, _, _, _, _, _, _),
+ [188] = PINGROUP(188, qdss_gpio, _, _, _, _, _, _, _, _),
+ [189] = PINGROUP(189, qdss_gpio, _, _, _, _, _, _, _, _),
+ [190] = PINGROUP(190, qdss_gpio, _, _, _, _, _, _, _, _),
+ [191] = PINGROUP(191, qdss_gpio, _, _, _, _, _, _, _, _),
+ [192] = PINGROUP(192, qdss_gpio, _, _, _, _, _, _, _, _),
+ [193] = PINGROUP(193, qdss_gpio, _, _, _, _, _, _, _, _),
+ [194] = PINGROUP(194, qdss_gpio, _, _, _, _, _, _, _, _),
+ [195] = PINGROUP(195, qdss_gpio, _, _, _, _, _, _, _, _),
+ [196] = PINGROUP(196, qdss_gpio, _, _, _, _, _, _, _, _),
+ [197] = PINGROUP(197, qdss_gpio, _, _, _, _, _, _, _, _),
+ [198] = PINGROUP(198, qdss_gpio, _, _, _, _, _, _, _, _),
+ [199] = PINGROUP(199, qdss_gpio, _, _, _, _, _, _, _, _),
+ [200] = PINGROUP(200, qdss_gpio, _, _, _, _, _, _, _, _),
+ [201] = PINGROUP(201, _, _, _, _, _, _, _, _, _),
+ [202] = PINGROUP(202, _, _, _, _, _, _, _, _, _),
+ [203] = UFS_RESET(ufs_reset, 0x1d8000),
+ [204] = SDC_PINGROUP(sdc2_clk, 0x1cf000, 14, 6),
+ [205] = SDC_PINGROUP(sdc2_cmd, 0x1cf000, 11, 3),
+ [206] = SDC_PINGROUP(sdc2_data, 0x1cf000, 9, 0),
+};
+
+static const struct msm_pinctrl_soc_data sm8350_tlmm = {
+ .pins = sm8350_pins,
+ .npins = ARRAY_SIZE(sm8350_pins),
+ .functions = sm8350_functions,
+ .nfunctions = ARRAY_SIZE(sm8350_functions),
+ .groups = sm8350_groups,
+ .ngroups = ARRAY_SIZE(sm8350_groups),
+ .ngpios = 204,
+};
+
+static int sm8350_tlmm_probe(struct platform_device *pdev)
+{
+ return msm_pinctrl_probe(pdev, &sm8350_tlmm);
+}
+
+static const struct of_device_id sm8350_tlmm_of_match[] = {
+ { .compatible = "qcom,sm8350-tlmm", },
+ { },
+};
+
+static struct platform_driver sm8350_tlmm_driver = {
+ .driver = {
+ .name = "sm8350-tlmm",
+ .of_match_table = sm8350_tlmm_of_match,
+ },
+ .probe = sm8350_tlmm_probe,
+ .remove = msm_pinctrl_remove,
+};
+
+static int __init sm8350_tlmm_init(void)
+{
+ return platform_driver_register(&sm8350_tlmm_driver);
+}
+arch_initcall(sm8350_tlmm_init);
+
+static void __exit sm8350_tlmm_exit(void)
+{
+ platform_driver_unregister(&sm8350_tlmm_driver);
+}
+module_exit(sm8350_tlmm_exit);
+
+MODULE_DESCRIPTION("QTI SM8350 TLMM driver");
+MODULE_LICENSE("GPL v2");
+MODULE_DEVICE_TABLE(of, sm8350_tlmm_of_match);
diff --git a/drivers/pinctrl/qcom/pinctrl-spmi-mpp.c b/drivers/pinctrl/qcom/pinctrl-spmi-mpp.c
index 48602db..3c213f7 100644
--- a/drivers/pinctrl/qcom/pinctrl-spmi-mpp.c
+++ b/drivers/pinctrl/qcom/pinctrl-spmi-mpp.c
@@ -912,6 +912,7 @@
}
static const struct of_device_id pmic_mpp_of_match[] = {
+ { .compatible = "qcom,pm8019-mpp" }, /* 6 MPP's */
{ .compatible = "qcom,pm8841-mpp" }, /* 4 MPP's */
{ .compatible = "qcom,pm8916-mpp" }, /* 4 MPP's */
{ .compatible = "qcom,pm8941-mpp" }, /* 8 MPP's */
diff --git a/drivers/pinctrl/qcom/pinctrl-ssbi-mpp.c b/drivers/pinctrl/qcom/pinctrl-ssbi-mpp.c
index 681d8dc..92e7f26 100644
--- a/drivers/pinctrl/qcom/pinctrl-ssbi-mpp.c
+++ b/drivers/pinctrl/qcom/pinctrl-ssbi-mpp.c
@@ -617,7 +617,6 @@
}
break;
}
-
}
static void pm8xxx_mpp_dbg_show(struct seq_file *s, struct gpio_chip *chip)
diff --git a/drivers/pinctrl/ralink/pinctrl-rt2880.c b/drivers/pinctrl/ralink/pinctrl-rt2880.c
index 42b1c6c..1f4bca8 100644
--- a/drivers/pinctrl/ralink/pinctrl-rt2880.c
+++ b/drivers/pinctrl/ralink/pinctrl-rt2880.c
@@ -193,7 +193,6 @@
static int rt2880_pinmux_index(struct rt2880_priv *p)
{
- struct rt2880_pmx_func **f;
struct rt2880_pmx_group *mux = p->groups;
int i, j, c = 0;
@@ -207,7 +206,7 @@
p->group_names = devm_kcalloc(p->dev, p->group_count,
sizeof(char *), GFP_KERNEL);
if (!p->group_names)
- return -1;
+ return -ENOMEM;
for (i = 0; i < p->group_count; i++) {
p->group_names[i] = p->groups[i].name;
@@ -218,31 +217,31 @@
p->func_count++;
/* allocate our function and group mapping index buffers */
- f = p->func = devm_kcalloc(p->dev,
- p->func_count,
- sizeof(*p->func),
- GFP_KERNEL);
+ p->func = devm_kcalloc(p->dev, p->func_count,
+ sizeof(*p->func), GFP_KERNEL);
gpio_func.groups = devm_kcalloc(p->dev, p->group_count, sizeof(int),
GFP_KERNEL);
- if (!f || !gpio_func.groups)
- return -1;
+ if (!p->func || !gpio_func.groups)
+ return -ENOMEM;
/* add a backpointer to the function so it knows its group */
gpio_func.group_count = p->group_count;
for (i = 0; i < gpio_func.group_count; i++)
gpio_func.groups[i] = i;
- f[c] = &gpio_func;
+ p->func[c] = &gpio_func;
c++;
/* add remaining functions */
for (i = 0; i < p->group_count; i++) {
for (j = 0; j < p->groups[i].func_count; j++) {
- f[c] = &p->groups[i].func[j];
- f[c]->groups = devm_kzalloc(p->dev, sizeof(int),
+ p->func[c] = &p->groups[i].func[j];
+ p->func[c]->groups = devm_kzalloc(p->dev, sizeof(int),
GFP_KERNEL);
- f[c]->groups[0] = i;
- f[c]->group_count = 1;
+ if (!p->func[c]->groups)
+ return -ENOMEM;
+ p->func[c]->groups[0] = i;
+ p->func[c]->group_count = 1;
c++;
}
}
@@ -280,10 +279,8 @@
/* the pads needed to tell pinctrl about our pins */
p->pads = devm_kcalloc(p->dev, p->max_pins,
sizeof(struct pinctrl_pin_desc), GFP_KERNEL);
- if (!p->pads || !p->gpio) {
- dev_err(p->dev, "Failed to allocate gpio data\n");
+ if (!p->pads || !p->gpio)
return -ENOMEM;
- }
memset(p->gpio, 1, sizeof(u8) * p->max_pins);
for (i = 0; i < p->func_count; i++) {
@@ -318,6 +315,7 @@
{
struct rt2880_priv *p;
struct pinctrl_dev *dev;
+ int err;
if (!rt2880_pinmux_data)
return -ENOTSUPP;
@@ -333,19 +331,20 @@
platform_set_drvdata(pdev, p);
/* init the device */
- if (rt2880_pinmux_index(p)) {
+ err = rt2880_pinmux_index(p);
+ if (err) {
dev_err(&pdev->dev, "failed to load index\n");
- return -EINVAL;
+ return err;
}
- if (rt2880_pinmux_pins(p)) {
+
+ err = rt2880_pinmux_pins(p);
+ if (err) {
dev_err(&pdev->dev, "failed to load pins\n");
- return -EINVAL;
+ return err;
}
dev = pinctrl_register(p->desc, &pdev->dev, p);
- if (IS_ERR(dev))
- return PTR_ERR(dev);
- return 0;
+ return PTR_ERR_OR_ZERO(dev);
}
static const struct of_device_id rt2880_pinmux_match[] = {
@@ -362,7 +361,7 @@
},
};
-int __init rt2880_pinmux_init(void)
+static int __init rt2880_pinmux_init(void)
{
return platform_driver_register(&rt2880_pinmux_driver);
}
diff --git a/drivers/pinctrl/renesas/Kconfig b/drivers/pinctrl/renesas/Kconfig
index e941b84..4b84a74 100644
--- a/drivers/pinctrl/renesas/Kconfig
+++ b/drivers/pinctrl/renesas/Kconfig
@@ -36,6 +36,7 @@
select PINCTRL_PFC_R8A77980 if ARCH_R8A77980
select PINCTRL_PFC_R8A77990 if ARCH_R8A77990
select PINCTRL_PFC_R8A77995 if ARCH_R8A77995
+ select PINCTRL_PFC_R8A779A0 if ARCH_R8A779A0
select PINCTRL_PFC_SH7203 if CPU_SUBTYPE_SH7203
select PINCTRL_PFC_SH7264 if CPU_SUBTYPE_SH7264
select PINCTRL_PFC_SH7269 if CPU_SUBTYPE_SH7269
@@ -142,6 +143,10 @@
bool "pin control support for R-Car V3M" if COMPILE_TEST
select PINCTRL_SH_PFC
+config PINCTRL_PFC_R8A779A0
+ bool "pin control support for R-Car V3U" if COMPILE_TEST
+ select PINCTRL_SH_PFC
+
config PINCTRL_PFC_R8A7740
bool "pin control support for R-Mobile A1" if COMPILE_TEST
select PINCTRL_SH_PFC_GPIO
diff --git a/drivers/pinctrl/renesas/Makefile b/drivers/pinctrl/renesas/Makefile
index 1f6d7dd..3535632 100644
--- a/drivers/pinctrl/renesas/Makefile
+++ b/drivers/pinctrl/renesas/Makefile
@@ -29,6 +29,7 @@
obj-$(CONFIG_PINCTRL_PFC_R8A77980) += pfc-r8a77980.o
obj-$(CONFIG_PINCTRL_PFC_R8A77990) += pfc-r8a77990.o
obj-$(CONFIG_PINCTRL_PFC_R8A77995) += pfc-r8a77995.o
+obj-$(CONFIG_PINCTRL_PFC_R8A779A0) += pfc-r8a779a0.o
obj-$(CONFIG_PINCTRL_PFC_SH7203) += pfc-sh7203.o
obj-$(CONFIG_PINCTRL_PFC_SH7264) += pfc-sh7264.o
obj-$(CONFIG_PINCTRL_PFC_SH7269) += pfc-sh7269.o
diff --git a/drivers/pinctrl/renesas/core.c b/drivers/pinctrl/renesas/core.c
index 2cc4572..2bfd300 100644
--- a/drivers/pinctrl/renesas/core.c
+++ b/drivers/pinctrl/renesas/core.c
@@ -175,13 +175,25 @@
return sh_pfc_read_raw_reg(sh_pfc_phys_to_virt(pfc, reg), 32);
}
+static void sh_pfc_unlock_reg(struct sh_pfc *pfc, u32 reg, u32 data)
+{
+ u32 unlock;
+
+ if (!pfc->info->unlock_reg)
+ return;
+
+ if (pfc->info->unlock_reg >= 0x80000000UL)
+ unlock = pfc->info->unlock_reg;
+ else
+ /* unlock_reg is a mask */
+ unlock = reg & ~pfc->info->unlock_reg;
+
+ sh_pfc_write_raw_reg(sh_pfc_phys_to_virt(pfc, unlock), 32, ~data);
+}
+
void sh_pfc_write(struct sh_pfc *pfc, u32 reg, u32 data)
{
- if (pfc->info->unlock_reg)
- sh_pfc_write_raw_reg(
- sh_pfc_phys_to_virt(pfc, pfc->info->unlock_reg), 32,
- ~data);
-
+ sh_pfc_unlock_reg(pfc, reg, data);
sh_pfc_write_raw_reg(sh_pfc_phys_to_virt(pfc, reg), 32, data);
}
@@ -227,11 +239,7 @@
data &= mask;
data |= value;
- if (pfc->info->unlock_reg)
- sh_pfc_write_raw_reg(
- sh_pfc_phys_to_virt(pfc, pfc->info->unlock_reg), 32,
- ~data);
-
+ sh_pfc_unlock_reg(pfc, crp->reg, data);
sh_pfc_write_raw_reg(mapped_reg, crp->reg_width, data);
}
@@ -638,6 +646,12 @@
.data = &r8a77995_pinmux_info,
},
#endif
+#ifdef CONFIG_PINCTRL_PFC_R8A779A0
+ {
+ .compatible = "renesas,pfc-r8a779a0",
+ .data = &r8a779a0_pinmux_info,
+ },
+#endif
#ifdef CONFIG_PINCTRL_PFC_SH73A0
{
.compatible = "renesas,pfc-sh73a0",
@@ -1052,6 +1066,10 @@
{
unsigned int i;
+ if (!IS_ENABLED(CONFIG_SUPERH) &&
+ !of_find_matching_node(NULL, pdrv->driver.of_match_table))
+ return;
+
sh_pfc_regs = kcalloc(SH_PFC_MAX_REGS, sizeof(*sh_pfc_regs),
GFP_KERNEL);
if (!sh_pfc_regs)
diff --git a/drivers/pinctrl/renesas/pfc-r8a77950.c b/drivers/pinctrl/renesas/pfc-r8a77950.c
index 32b66b9..32fe8ca 100644
--- a/drivers/pinctrl/renesas/pfc-r8a77950.c
+++ b/drivers/pinctrl/renesas/pfc-r8a77950.c
@@ -1668,7 +1668,6 @@
PIN_AVB_RX_CTL, PIN_AVB_RXC, PIN_AVB_RD0,
PIN_AVB_RD1, PIN_AVB_RD2, PIN_AVB_RD3,
PIN_AVB_TXCREFCLK,
-
};
static const unsigned int avb_mii_mux[] = {
AVB_TX_CTL_MARK, AVB_TXC_MARK, AVB_TD0_MARK,
diff --git a/drivers/pinctrl/renesas/pfc-r8a77951.c b/drivers/pinctrl/renesas/pfc-r8a77951.c
index cf14420..bdd605e 100644
--- a/drivers/pinctrl/renesas/pfc-r8a77951.c
+++ b/drivers/pinctrl/renesas/pfc-r8a77951.c
@@ -1727,7 +1727,6 @@
PIN_AVB_RX_CTL, PIN_AVB_RXC, PIN_AVB_RD0,
PIN_AVB_RD1, PIN_AVB_RD2, PIN_AVB_RD3,
PIN_AVB_TXCREFCLK,
-
};
static const unsigned int avb_mii_mux[] = {
AVB_TX_CTL_MARK, AVB_TXC_MARK, AVB_TD0_MARK,
diff --git a/drivers/pinctrl/renesas/pfc-r8a7796.c b/drivers/pinctrl/renesas/pfc-r8a7796.c
index 38d9635..96b5b15 100644
--- a/drivers/pinctrl/renesas/pfc-r8a7796.c
+++ b/drivers/pinctrl/renesas/pfc-r8a7796.c
@@ -1731,7 +1731,6 @@
PIN_AVB_RX_CTL, PIN_AVB_RXC, PIN_AVB_RD0,
PIN_AVB_RD1, PIN_AVB_RD2, PIN_AVB_RD3,
PIN_AVB_TXCREFCLK,
-
};
static const unsigned int avb_mii_mux[] = {
AVB_TX_CTL_MARK, AVB_TXC_MARK, AVB_TD0_MARK,
diff --git a/drivers/pinctrl/renesas/pfc-r8a77965.c b/drivers/pinctrl/renesas/pfc-r8a77965.c
index 92f231b..f15e293 100644
--- a/drivers/pinctrl/renesas/pfc-r8a77965.c
+++ b/drivers/pinctrl/renesas/pfc-r8a77965.c
@@ -1736,7 +1736,6 @@
PIN_AVB_RX_CTL, PIN_AVB_RXC, PIN_AVB_RD0,
PIN_AVB_RD1, PIN_AVB_RD2, PIN_AVB_RD3,
PIN_AVB_TXCREFCLK,
-
};
static const unsigned int avb_mii_mux[] = {
AVB_TX_CTL_MARK, AVB_TXC_MARK, AVB_TD0_MARK,
diff --git a/drivers/pinctrl/renesas/pfc-r8a779a0.c b/drivers/pinctrl/renesas/pfc-r8a779a0.c
new file mode 100644
index 0000000..2250ccd
--- /dev/null
+++ b/drivers/pinctrl/renesas/pfc-r8a779a0.c
@@ -0,0 +1,4460 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * R8A779A0 processor support - PFC hardware block.
+ *
+ * Copyright (C) 2020 Renesas Electronics Corp.
+ *
+ * This file is based on the drivers/pinctrl/renesas/pfc-r8a7795.c
+ */
+
+#include <linux/errno.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+
+#include "core.h"
+#include "sh_pfc.h"
+
+#define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | SH_PFC_PIN_CFG_PULL_UP_DOWN)
+
+#define CPU_ALL_GP(fn, sfx) \
+ PORT_GP_CFG_15(0, fn, sfx, CFG_FLAGS), \
+ PORT_GP_CFG_1(0, 15, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
+ PORT_GP_CFG_1(0, 16, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
+ PORT_GP_CFG_1(0, 17, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
+ PORT_GP_CFG_1(0, 18, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
+ PORT_GP_CFG_1(0, 19, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
+ PORT_GP_CFG_1(0, 20, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
+ PORT_GP_CFG_1(0, 21, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
+ PORT_GP_CFG_1(0, 22, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
+ PORT_GP_CFG_1(0, 23, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
+ PORT_GP_CFG_1(0, 24, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
+ PORT_GP_CFG_1(0, 25, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
+ PORT_GP_CFG_1(0, 26, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
+ PORT_GP_CFG_1(0, 27, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
+ PORT_GP_CFG_31(1, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
+ PORT_GP_CFG_2(2, fn, sfx, CFG_FLAGS), \
+ PORT_GP_CFG_1(2, 2, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
+ PORT_GP_CFG_1(2, 3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
+ PORT_GP_CFG_1(2, 4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
+ PORT_GP_CFG_1(2, 5, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
+ PORT_GP_CFG_1(2, 6, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
+ PORT_GP_CFG_1(2, 7, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
+ PORT_GP_CFG_1(2, 8, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
+ PORT_GP_CFG_1(2, 9, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
+ PORT_GP_CFG_1(2, 10, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
+ PORT_GP_CFG_1(2, 11, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
+ PORT_GP_CFG_1(2, 12, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
+ PORT_GP_CFG_1(2, 13, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
+ PORT_GP_CFG_1(2, 14, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
+ PORT_GP_CFG_1(2, 15, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
+ PORT_GP_CFG_1(2, 16, fn, sfx, CFG_FLAGS), \
+ PORT_GP_CFG_1(2, 17, fn, sfx, CFG_FLAGS), \
+ PORT_GP_CFG_1(2, 18, fn, sfx, CFG_FLAGS), \
+ PORT_GP_CFG_1(2, 19, fn, sfx, CFG_FLAGS), \
+ PORT_GP_CFG_1(2, 20, fn, sfx, CFG_FLAGS), \
+ PORT_GP_CFG_1(2, 21, fn, sfx, CFG_FLAGS), \
+ PORT_GP_CFG_1(2, 22, fn, sfx, CFG_FLAGS), \
+ PORT_GP_CFG_1(2, 23, fn, sfx, CFG_FLAGS), \
+ PORT_GP_CFG_1(2, 24, fn, sfx, CFG_FLAGS), \
+ PORT_GP_CFG_17(3, fn, sfx, CFG_FLAGS), \
+ PORT_GP_CFG_18(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_25_33),\
+ PORT_GP_CFG_1(4, 18, fn, sfx, CFG_FLAGS), \
+ PORT_GP_CFG_1(4, 19, fn, sfx, CFG_FLAGS), \
+ PORT_GP_CFG_1(4, 20, fn, sfx, CFG_FLAGS), \
+ PORT_GP_CFG_1(4, 21, fn, sfx, CFG_FLAGS), \
+ PORT_GP_CFG_1(4, 22, fn, sfx, CFG_FLAGS), \
+ PORT_GP_CFG_1(4, 23, fn, sfx, CFG_FLAGS), \
+ PORT_GP_CFG_1(4, 24, fn, sfx, CFG_FLAGS), \
+ PORT_GP_CFG_1(4, 25, fn, sfx, CFG_FLAGS), \
+ PORT_GP_CFG_1(4, 26, fn, sfx, CFG_FLAGS), \
+ PORT_GP_CFG_18(5, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_25_33),\
+ PORT_GP_CFG_1(5, 18, fn, sfx, CFG_FLAGS), \
+ PORT_GP_CFG_1(5, 19, fn, sfx, CFG_FLAGS), \
+ PORT_GP_CFG_1(5, 20, fn, sfx, CFG_FLAGS), \
+ PORT_GP_CFG_18(6, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_25_33),\
+ PORT_GP_CFG_1(6, 18, fn, sfx, CFG_FLAGS), \
+ PORT_GP_CFG_1(6, 19, fn, sfx, CFG_FLAGS), \
+ PORT_GP_CFG_1(6, 20, fn, sfx, CFG_FLAGS), \
+ PORT_GP_CFG_18(7, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_25_33),\
+ PORT_GP_CFG_1(7, 18, fn, sfx, CFG_FLAGS), \
+ PORT_GP_CFG_1(7, 19, fn, sfx, CFG_FLAGS), \
+ PORT_GP_CFG_1(7, 20, fn, sfx, CFG_FLAGS), \
+ PORT_GP_CFG_18(8, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_25_33),\
+ PORT_GP_CFG_1(8, 18, fn, sfx, CFG_FLAGS), \
+ PORT_GP_CFG_1(8, 19, fn, sfx, CFG_FLAGS), \
+ PORT_GP_CFG_1(8, 20, fn, sfx, CFG_FLAGS), \
+ PORT_GP_CFG_18(9, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_25_33),\
+ PORT_GP_CFG_1(9, 18, fn, sfx, CFG_FLAGS), \
+ PORT_GP_CFG_1(9, 19, fn, sfx, CFG_FLAGS), \
+ PORT_GP_CFG_1(9, 20, fn, sfx, CFG_FLAGS)
+
+#define CPU_ALL_NOGP(fn) \
+ PIN_NOGP_CFG(PRESETOUT_N, "PRESETOUT#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
+ PIN_NOGP_CFG(EXTALR, "EXTALR", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
+ PIN_NOGP_CFG(DCUTRST_N_LPDRST_N, "DCUTRST#_LPDRST#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
+ PIN_NOGP_CFG(DCUTCK_LPDCLK, "DCUTCK_LPDCLK", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
+ PIN_NOGP_CFG(DCUTMS, "DCUTMS", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
+ PIN_NOGP_CFG(DCUTDI_LPDI, "DCUTDI_LPDI", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN)
+
+/*
+ * F_() : just information
+ * FM() : macro for FN_xxx / xxx_MARK
+ */
+
+/* GPSR0 */
+#define GPSR0_27 FM(MMC_D7)
+#define GPSR0_26 FM(MMC_D6)
+#define GPSR0_25 FM(MMC_D5)
+#define GPSR0_24 FM(MMC_D4)
+#define GPSR0_23 FM(MMC_SD_CLK)
+#define GPSR0_22 FM(MMC_SD_D3)
+#define GPSR0_21 FM(MMC_SD_D2)
+#define GPSR0_20 FM(MMC_SD_D1)
+#define GPSR0_19 FM(MMC_SD_D0)
+#define GPSR0_18 FM(MMC_SD_CMD)
+#define GPSR0_17 FM(MMC_DS)
+#define GPSR0_16 FM(SD_CD)
+#define GPSR0_15 FM(SD_WP)
+#define GPSR0_14 FM(RPC_INT_N)
+#define GPSR0_13 FM(RPC_WP_N)
+#define GPSR0_12 FM(RPC_RESET_N)
+#define GPSR0_11 FM(QSPI1_SSL)
+#define GPSR0_10 FM(QSPI1_IO3)
+#define GPSR0_9 FM(QSPI1_IO2)
+#define GPSR0_8 FM(QSPI1_MISO_IO1)
+#define GPSR0_7 FM(QSPI1_MOSI_IO0)
+#define GPSR0_6 FM(QSPI1_SPCLK)
+#define GPSR0_5 FM(QSPI0_SSL)
+#define GPSR0_4 FM(QSPI0_IO3)
+#define GPSR0_3 FM(QSPI0_IO2)
+#define GPSR0_2 FM(QSPI0_MISO_IO1)
+#define GPSR0_1 FM(QSPI0_MOSI_IO0)
+#define GPSR0_0 FM(QSPI0_SPCLK)
+
+/* GPSR1 */
+#define GPSR1_30 F_(GP1_30, IP3SR1_27_24)
+#define GPSR1_29 F_(GP1_29, IP3SR1_23_20)
+#define GPSR1_28 F_(GP1_28, IP3SR1_19_16)
+#define GPSR1_27 F_(IRQ3, IP3SR1_15_12)
+#define GPSR1_26 F_(IRQ2, IP3SR1_11_8)
+#define GPSR1_25 F_(IRQ1, IP3SR1_7_4)
+#define GPSR1_24 F_(IRQ0, IP3SR1_3_0)
+#define GPSR1_23 F_(MSIOF2_SS2, IP2SR1_31_28)
+#define GPSR1_22 F_(MSIOF2_SS1, IP2SR1_27_24)
+#define GPSR1_21 F_(MSIOF2_SYNC, IP2SR1_23_20)
+#define GPSR1_20 F_(MSIOF2_SCK, IP2SR1_19_16)
+#define GPSR1_19 F_(MSIOF2_TXD, IP2SR1_15_12)
+#define GPSR1_18 F_(MSIOF2_RXD, IP2SR1_11_8)
+#define GPSR1_17 F_(MSIOF1_SS2, IP2SR1_7_4)
+#define GPSR1_16 F_(MSIOF1_SS1, IP2SR1_3_0)
+#define GPSR1_15 F_(MSIOF1_SYNC, IP1SR1_31_28)
+#define GPSR1_14 F_(MSIOF1_SCK, IP1SR1_27_24)
+#define GPSR1_13 F_(MSIOF1_TXD, IP1SR1_23_20)
+#define GPSR1_12 F_(MSIOF1_RXD, IP1SR1_19_16)
+#define GPSR1_11 F_(MSIOF0_SS2, IP1SR1_15_12)
+#define GPSR1_10 F_(MSIOF0_SS1, IP1SR1_11_8)
+#define GPSR1_9 F_(MSIOF0_SYNC, IP1SR1_7_4)
+#define GPSR1_8 F_(MSIOF0_SCK, IP1SR1_3_0)
+#define GPSR1_7 F_(MSIOF0_TXD, IP0SR1_31_28)
+#define GPSR1_6 F_(MSIOF0_RXD, IP0SR1_27_24)
+#define GPSR1_5 F_(HTX0, IP0SR1_23_20)
+#define GPSR1_4 F_(HCTS0_N, IP0SR1_19_16)
+#define GPSR1_3 F_(HRTS0_N, IP0SR1_15_12)
+#define GPSR1_2 F_(HSCK0, IP0SR1_11_8)
+#define GPSR1_1 F_(HRX0, IP0SR1_7_4)
+#define GPSR1_0 F_(SCIF_CLK, IP0SR1_3_0)
+
+/* GPSR2 */
+#define GPSR2_24 FM(TCLK2_A)
+#define GPSR2_23 F_(TCLK1_A, IP2SR2_31_28)
+#define GPSR2_22 F_(TPU0TO1, IP2SR2_27_24)
+#define GPSR2_21 F_(TPU0TO0, IP2SR2_23_20)
+#define GPSR2_20 F_(CLK_EXTFXR, IP2SR2_19_16)
+#define GPSR2_19 F_(RXDB_EXTFXR, IP2SR2_15_12)
+#define GPSR2_18 F_(FXR_TXDB, IP2SR2_11_8)
+#define GPSR2_17 F_(RXDA_EXTFXR_A, IP2SR2_7_4)
+#define GPSR2_16 F_(FXR_TXDA_A, IP2SR2_3_0)
+#define GPSR2_15 F_(GP2_15, IP1SR2_31_28)
+#define GPSR2_14 F_(GP2_14, IP1SR2_27_24)
+#define GPSR2_13 F_(GP2_13, IP1SR2_23_20)
+#define GPSR2_12 F_(GP2_12, IP1SR2_19_16)
+#define GPSR2_11 F_(GP2_11, IP1SR2_15_12)
+#define GPSR2_10 F_(GP2_10, IP1SR2_11_8)
+#define GPSR2_9 F_(GP2_09, IP1SR2_7_4)
+#define GPSR2_8 F_(GP2_08, IP1SR2_3_0)
+#define GPSR2_7 F_(GP2_07, IP0SR2_31_28)
+#define GPSR2_6 F_(GP2_06, IP0SR2_27_24)
+#define GPSR2_5 F_(GP2_05, IP0SR2_23_20)
+#define GPSR2_4 F_(GP2_04, IP0SR2_19_16)
+#define GPSR2_3 F_(GP2_03, IP0SR2_15_12)
+#define GPSR2_2 F_(GP2_02, IP0SR2_11_8)
+#define GPSR2_1 F_(IPC_CLKOUT, IP0SR2_7_4)
+#define GPSR2_0 F_(IPC_CLKIN, IP0SR2_3_0)
+
+/* GPSR3 */
+#define GPSR3_16 FM(CANFD7_RX)
+#define GPSR3_15 FM(CANFD7_TX)
+#define GPSR3_14 FM(CANFD6_RX)
+#define GPSR3_13 F_(CANFD6_TX, IP1SR3_23_20)
+#define GPSR3_12 F_(CANFD5_RX, IP1SR3_19_16)
+#define GPSR3_11 F_(CANFD5_TX, IP1SR3_15_12)
+#define GPSR3_10 F_(CANFD4_RX, IP1SR3_11_8)
+#define GPSR3_9 F_(CANFD4_TX, IP1SR3_7_4)
+#define GPSR3_8 F_(CANFD3_RX, IP1SR3_3_0)
+#define GPSR3_7 F_(CANFD3_TX, IP0SR3_31_28)
+#define GPSR3_6 F_(CANFD2_RX, IP0SR3_27_24)
+#define GPSR3_5 F_(CANFD2_TX, IP0SR3_23_20)
+#define GPSR3_4 FM(CANFD1_RX)
+#define GPSR3_3 FM(CANFD1_TX)
+#define GPSR3_2 F_(CANFD0_RX, IP0SR3_11_8)
+#define GPSR3_1 F_(CANFD0_TX, IP0SR3_7_4)
+#define GPSR3_0 FM(CAN_CLK)
+
+/* GPSR4 */
+#define GPSR4_26 FM(AVS1)
+#define GPSR4_25 FM(AVS0)
+#define GPSR4_24 FM(PCIE3_CLKREQ_N)
+#define GPSR4_23 FM(PCIE2_CLKREQ_N)
+#define GPSR4_22 FM(PCIE1_CLKREQ_N)
+#define GPSR4_21 FM(PCIE0_CLKREQ_N)
+#define GPSR4_20 F_(AVB0_AVTP_PPS, IP2SR4_19_16)
+#define GPSR4_19 F_(AVB0_AVTP_CAPTURE, IP2SR4_15_12)
+#define GPSR4_18 F_(AVB0_AVTP_MATCH, IP2SR4_11_8)
+#define GPSR4_17 F_(AVB0_LINK, IP2SR4_7_4)
+#define GPSR4_16 FM(AVB0_PHY_INT)
+#define GPSR4_15 F_(AVB0_MAGIC, IP1SR4_31_28)
+#define GPSR4_14 F_(AVB0_MDC, IP1SR4_27_24)
+#define GPSR4_13 F_(AVB0_MDIO, IP1SR4_23_20)
+#define GPSR4_12 F_(AVB0_TXCREFCLK, IP1SR4_19_16)
+#define GPSR4_11 F_(AVB0_TD3, IP1SR4_15_12)
+#define GPSR4_10 F_(AVB0_TD2, IP1SR4_11_8)
+#define GPSR4_9 F_(AVB0_TD1, IP1SR4_7_4)
+#define GPSR4_8 F_(AVB0_TD0, IP1SR4_3_0)
+#define GPSR4_7 F_(AVB0_TXC, IP0SR4_31_28)
+#define GPSR4_6 F_(AVB0_TX_CTL, IP0SR4_27_24)
+#define GPSR4_5 F_(AVB0_RD3, IP0SR4_23_20)
+#define GPSR4_4 F_(AVB0_RD2, IP0SR4_19_16)
+#define GPSR4_3 F_(AVB0_RD1, IP0SR4_15_12)
+#define GPSR4_2 F_(AVB0_RD0, IP0SR4_11_8)
+#define GPSR4_1 F_(AVB0_RXC, IP0SR4_7_4)
+#define GPSR4_0 F_(AVB0_RX_CTL, IP0SR4_3_0)
+
+/* GPSR5 */
+#define GPSR5_20 F_(AVB1_AVTP_PPS, IP2SR5_19_16)
+#define GPSR5_19 F_(AVB1_AVTP_CAPTURE, IP2SR5_15_12)
+#define GPSR5_18 F_(AVB1_AVTP_MATCH, IP2SR5_11_8)
+#define GPSR5_17 F_(AVB1_LINK, IP2SR5_7_4)
+#define GPSR5_16 FM(AVB1_PHY_INT)
+#define GPSR5_15 F_(AVB1_MAGIC, IP1SR5_31_28)
+#define GPSR5_14 F_(AVB1_MDC, IP1SR5_27_24)
+#define GPSR5_13 F_(AVB1_MDIO, IP1SR5_23_20)
+#define GPSR5_12 F_(AVB1_TXCREFCLK, IP1SR5_19_16)
+#define GPSR5_11 F_(AVB1_TD3, IP1SR5_15_12)
+#define GPSR5_10 F_(AVB1_TD2, IP1SR5_11_8)
+#define GPSR5_9 F_(AVB1_TD1, IP1SR5_7_4)
+#define GPSR5_8 F_(AVB1_TD0, IP1SR5_3_0)
+#define GPSR5_7 F_(AVB1_TXC, IP0SR5_31_28)
+#define GPSR5_6 F_(AVB1_TX_CTL, IP0SR5_27_24)
+#define GPSR5_5 F_(AVB1_RD3, IP0SR5_23_20)
+#define GPSR5_4 F_(AVB1_RD2, IP0SR5_19_16)
+#define GPSR5_3 F_(AVB1_RD1, IP0SR5_15_12)
+#define GPSR5_2 F_(AVB1_RD0, IP0SR5_11_8)
+#define GPSR5_1 F_(AVB1_RXC, IP0SR5_7_4)
+#define GPSR5_0 F_(AVB1_RX_CTL, IP0SR5_3_0)
+
+/* GPSR6 */
+#define GPSR6_20 FM(AVB2_AVTP_PPS)
+#define GPSR6_19 FM(AVB2_AVTP_CAPTURE)
+#define GPSR6_18 FM(AVB2_AVTP_MATCH)
+#define GPSR6_17 FM(AVB2_LINK)
+#define GPSR6_16 FM(AVB2_PHY_INT)
+#define GPSR6_15 FM(AVB2_MAGIC)
+#define GPSR6_14 FM(AVB2_MDC)
+#define GPSR6_13 FM(AVB2_MDIO)
+#define GPSR6_12 FM(AVB2_TXCREFCLK)
+#define GPSR6_11 FM(AVB2_TD3)
+#define GPSR6_10 FM(AVB2_TD2)
+#define GPSR6_9 FM(AVB2_TD1)
+#define GPSR6_8 FM(AVB2_TD0)
+#define GPSR6_7 FM(AVB2_TXC)
+#define GPSR6_6 FM(AVB2_TX_CTL)
+#define GPSR6_5 FM(AVB2_RD3)
+#define GPSR6_4 FM(AVB2_RD2)
+#define GPSR6_3 FM(AVB2_RD1)
+#define GPSR6_2 FM(AVB2_RD0)
+#define GPSR6_1 FM(AVB2_RXC)
+#define GPSR6_0 FM(AVB2_RX_CTL)
+
+/* GPSR7 */
+#define GPSR7_20 FM(AVB3_AVTP_PPS)
+#define GPSR7_19 FM(AVB3_AVTP_CAPTURE)
+#define GPSR7_18 FM(AVB3_AVTP_MATCH)
+#define GPSR7_17 FM(AVB3_LINK)
+#define GPSR7_16 FM(AVB3_PHY_INT)
+#define GPSR7_15 FM(AVB3_MAGIC)
+#define GPSR7_14 FM(AVB3_MDC)
+#define GPSR7_13 FM(AVB3_MDIO)
+#define GPSR7_12 FM(AVB3_TXCREFCLK)
+#define GPSR7_11 FM(AVB3_TD3)
+#define GPSR7_10 FM(AVB3_TD2)
+#define GPSR7_9 FM(AVB3_TD1)
+#define GPSR7_8 FM(AVB3_TD0)
+#define GPSR7_7 FM(AVB3_TXC)
+#define GPSR7_6 FM(AVB3_TX_CTL)
+#define GPSR7_5 FM(AVB3_RD3)
+#define GPSR7_4 FM(AVB3_RD2)
+#define GPSR7_3 FM(AVB3_RD1)
+#define GPSR7_2 FM(AVB3_RD0)
+#define GPSR7_1 FM(AVB3_RXC)
+#define GPSR7_0 FM(AVB3_RX_CTL)
+
+/* GPSR8 */
+#define GPSR8_20 FM(AVB4_AVTP_PPS)
+#define GPSR8_19 FM(AVB4_AVTP_CAPTURE)
+#define GPSR8_18 FM(AVB4_AVTP_MATCH)
+#define GPSR8_17 FM(AVB4_LINK)
+#define GPSR8_16 FM(AVB4_PHY_INT)
+#define GPSR8_15 FM(AVB4_MAGIC)
+#define GPSR8_14 FM(AVB4_MDC)
+#define GPSR8_13 FM(AVB4_MDIO)
+#define GPSR8_12 FM(AVB4_TXCREFCLK)
+#define GPSR8_11 FM(AVB4_TD3)
+#define GPSR8_10 FM(AVB4_TD2)
+#define GPSR8_9 FM(AVB4_TD1)
+#define GPSR8_8 FM(AVB4_TD0)
+#define GPSR8_7 FM(AVB4_TXC)
+#define GPSR8_6 FM(AVB4_TX_CTL)
+#define GPSR8_5 FM(AVB4_RD3)
+#define GPSR8_4 FM(AVB4_RD2)
+#define GPSR8_3 FM(AVB4_RD1)
+#define GPSR8_2 FM(AVB4_RD0)
+#define GPSR8_1 FM(AVB4_RXC)
+#define GPSR8_0 FM(AVB4_RX_CTL)
+
+/* GPSR9 */
+#define GPSR9_20 FM(AVB5_AVTP_PPS)
+#define GPSR9_19 FM(AVB5_AVTP_CAPTURE)
+#define GPSR9_18 FM(AVB5_AVTP_MATCH)
+#define GPSR9_17 FM(AVB5_LINK)
+#define GPSR9_16 FM(AVB5_PHY_INT)
+#define GPSR9_15 FM(AVB5_MAGIC)
+#define GPSR9_14 FM(AVB5_MDC)
+#define GPSR9_13 FM(AVB5_MDIO)
+#define GPSR9_12 FM(AVB5_TXCREFCLK)
+#define GPSR9_11 FM(AVB5_TD3)
+#define GPSR9_10 FM(AVB5_TD2)
+#define GPSR9_9 FM(AVB5_TD1)
+#define GPSR9_8 FM(AVB5_TD0)
+#define GPSR9_7 FM(AVB5_TXC)
+#define GPSR9_6 FM(AVB5_TX_CTL)
+#define GPSR9_5 FM(AVB5_RD3)
+#define GPSR9_4 FM(AVB5_RD2)
+#define GPSR9_3 FM(AVB5_RD1)
+#define GPSR9_2 FM(AVB5_RD0)
+#define GPSR9_1 FM(AVB5_RXC)
+#define GPSR9_0 FM(AVB5_RX_CTL)
+
+/* IP0SR1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */
+#define IP0SR1_3_0 FM(SCIF_CLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(A0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR1_7_4 FM(HRX0) FM(RX0) F_(0, 0) F_(0, 0) F_(0, 0) FM(A1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR1_11_8 FM(HSCK0) FM(SCK0) F_(0, 0) F_(0, 0) F_(0, 0) FM(A2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR1_15_12 FM(HRTS0_N) FM(RTS0_N) F_(0, 0) F_(0, 0) F_(0, 0) FM(A3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR1_19_16 FM(HCTS0_N) FM(CTS0_N) F_(0, 0) F_(0, 0) F_(0, 0) FM(A4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR1_23_20 FM(HTX0) FM(TX0) F_(0, 0) F_(0, 0) F_(0, 0) FM(A5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR1_27_24 FM(MSIOF0_RXD) F_(0, 0) F_(0, 0) F_(0, 0) FM(DU_DR2) FM(A6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR1_31_28 FM(MSIOF0_TXD) F_(0, 0) F_(0, 0) F_(0, 0) FM(DU_DR3) FM(A7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+/* IP1SR1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */
+#define IP1SR1_3_0 FM(MSIOF0_SCK) F_(0, 0) F_(0, 0) F_(0, 0) FM(DU_DR4) FM(A8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR1_7_4 FM(MSIOF0_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) FM(DU_DR5) FM(A9) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR1_11_8 FM(MSIOF0_SS1) F_(0, 0) F_(0, 0) F_(0, 0) FM(DU_DR6) FM(A10) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR1_15_12 FM(MSIOF0_SS2) F_(0, 0) F_(0, 0) F_(0, 0) FM(DU_DR7) FM(A11) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR1_19_16 FM(MSIOF1_RXD) F_(0, 0) F_(0, 0) F_(0, 0) FM(DU_DG2) FM(A12) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR1_23_20 FM(MSIOF1_TXD) FM(HRX3) FM(SCK3) F_(0, 0) FM(DU_DG3) FM(A13) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR1_27_24 FM(MSIOF1_SCK) FM(HSCK3) FM(CTS3_N) F_(0, 0) FM(DU_DG4) FM(A14) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR1_31_28 FM(MSIOF1_SYNC) FM(HRTS3_N) FM(RTS3_N) F_(0, 0) FM(DU_DG5) FM(A15) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+/* IP2SR1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */
+#define IP2SR1_3_0 FM(MSIOF1_SS1) FM(HCTS3_N) FM(RX3) F_(0, 0) FM(DU_DG6) FM(A16) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2SR1_7_4 FM(MSIOF1_SS2) FM(HTX3) FM(TX3) F_(0, 0) FM(DU_DG7) FM(A17) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2SR1_11_8 FM(MSIOF2_RXD) FM(HSCK1) FM(SCK1) F_(0, 0) FM(DU_DB2) FM(A18) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2SR1_15_12 FM(MSIOF2_TXD) FM(HCTS1_N) FM(CTS1_N) F_(0, 0) FM(DU_DB3) FM(A19) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2SR1_19_16 FM(MSIOF2_SCK) FM(HRTS1_N) FM(RTS1_N) F_(0, 0) FM(DU_DB4) FM(A20) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2SR1_23_20 FM(MSIOF2_SYNC) FM(HRX1) FM(RX1_A) F_(0, 0) FM(DU_DB5) FM(A21) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2SR1_27_24 FM(MSIOF2_SS1) FM(HTX1) FM(TX1_A) F_(0, 0) FM(DU_DB6) FM(A22) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2SR1_31_28 FM(MSIOF2_SS2) FM(TCLK1_B) F_(0, 0) F_(0, 0) FM(DU_DB7) FM(A23) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+
+/* IP3SR1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */
+#define IP3SR1_3_0 FM(IRQ0) F_(0, 0) F_(0, 0) F_(0, 0) FM(DU_DOTCLKOUT) FM(A24) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP3SR1_7_4 FM(IRQ1) F_(0, 0) F_(0, 0) F_(0, 0) FM(DU_HSYNC) FM(A25) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP3SR1_11_8 FM(IRQ2) F_(0, 0) F_(0, 0) F_(0, 0) FM(DU_VSYNC) FM(CS1_N_A26) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP3SR1_15_12 FM(IRQ3) F_(0, 0) F_(0, 0) F_(0, 0) FM(DU_ODDF_DISP_CDE) FM(CS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP3SR1_19_16 FM(GP1_28) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(D0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP3SR1_23_20 FM(GP1_29) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(D1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP3SR1_27_24 FM(GP1_30) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(D2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP3SR1_31_28 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+
+/* IP0SR2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */
+#define IP0SR2_3_0 FM(IPC_CLKIN) FM(IPC_CLKEN_IN) F_(0, 0) F_(0, 0) FM(DU_DOTCLKIN) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR2_7_4 FM(IPC_CLKOUT) FM(IPC_CLKEN_OUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR2_11_8 FM(GP2_02) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(D3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR2_15_12 FM(GP2_03) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(D4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR2_19_16 FM(GP2_04) F_(0, 0) FM(MSIOF4_RXD) F_(0, 0) F_(0, 0) FM(D5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR2_23_20 FM(GP2_05) FM(HSCK2) FM(MSIOF4_TXD) FM(SCK4) F_(0, 0) FM(D6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR2_27_24 FM(GP2_06) FM(HCTS2_N) FM(MSIOF4_SCK) FM(CTS4_N) F_(0, 0) FM(D7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR2_31_28 FM(GP2_07) FM(HRTS2_N) FM(MSIOF4_SYNC) FM(RTS4_N) F_(0, 0) FM(D8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+/* IP1SR2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */
+#define IP1SR2_3_0 FM(GP2_08) FM(HRX2) FM(MSIOF4_SS1) FM(RX4) F_(0, 0) FM(D9) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR2_7_4 FM(GP2_09) FM(HTX2) FM(MSIOF4_SS2) FM(TX4) F_(0, 0) FM(D10) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR2_11_8 FM(GP2_10) FM(TCLK2_B) FM(MSIOF5_RXD) F_(0, 0) F_(0, 0) FM(D11) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR2_15_12 FM(GP2_11) FM(TCLK3) FM(MSIOF5_TXD) F_(0, 0) F_(0, 0) FM(D12) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR2_19_16 FM(GP2_12) FM(TCLK4) FM(MSIOF5_SCK) F_(0, 0) F_(0, 0) FM(D13) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR2_23_20 FM(GP2_13) F_(0, 0) FM(MSIOF5_SYNC) F_(0, 0) F_(0, 0) FM(D14) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR2_27_24 FM(GP2_14) FM(IRQ4) FM(MSIOF5_SS1) F_(0, 0) F_(0, 0) FM(D15) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR2_31_28 FM(GP2_15) FM(IRQ5) FM(MSIOF5_SS2) FM(CPG_CPCKOUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+/* IP2SR2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */
+#define IP2SR2_3_0 FM(FXR_TXDA_A) FM(MSIOF3_SS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2SR2_7_4 FM(RXDA_EXTFXR_A) FM(MSIOF3_SS2) F_(0, 0) F_(0, 0) F_(0, 0) FM(BS_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2SR2_11_8 FM(FXR_TXDB) FM(MSIOF3_RXD) F_(0, 0) F_(0, 0) F_(0, 0) FM(RD_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2SR2_15_12 FM(RXDB_EXTFXR) FM(MSIOF3_TXD) F_(0, 0) F_(0, 0) F_(0, 0) FM(WE0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2SR2_19_16 FM(CLK_EXTFXR) FM(MSIOF3_SCK) F_(0, 0) F_(0, 0) F_(0, 0) FM(WE1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2SR2_23_20 FM(TPU0TO0) FM(MSIOF3_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) FM(RD_WR_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2SR2_27_24 FM(TPU0TO1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(CLKOUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2SR2_31_28 FM(TCLK1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(EX_WAIT0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+
+/* IP0SR3 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */
+#define IP0SR3_3_0 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR3_7_4 FM(CANFD0_TX) FM(FXR_TXDA_B) FM(TX1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR3_11_8 FM(CANFD0_RX) FM(RXDA_EXTFXR_B) FM(RX1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR3_15_12 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR3_19_16 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR3_23_20 FM(CANFD2_TX) FM(TPU0TO2) FM(PWM0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR3_27_24 FM(CANFD2_RX) FM(TPU0TO3) FM(PWM1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR3_31_28 FM(CANFD3_TX) F_(0, 0) FM(PWM2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+/* IP1SR3 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */
+#define IP1SR3_3_0 FM(CANFD3_RX) F_(0, 0) FM(PWM3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR3_7_4 FM(CANFD4_TX) F_(0, 0) FM(PWM4) FM(FXR_CLKOUT1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR3_11_8 FM(CANFD4_RX) F_(0, 0) F_(0, 0) FM(FXR_CLKOUT2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR3_15_12 FM(CANFD5_TX) F_(0, 0) F_(0, 0) FM(FXR_TXENA_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR3_19_16 FM(CANFD5_RX) F_(0, 0) F_(0, 0) FM(FXR_TXENB_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR3_23_20 FM(CANFD6_TX) F_(0, 0) F_(0, 0) FM(STPWT_EXTFXR) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR3_27_24 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR3_31_28 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+
+/* IP0SR4 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */
+#define IP0SR4_3_0 FM(AVB0_RX_CTL) FM(AVB0_MII_RX_DV) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR4_7_4 FM(AVB0_RXC) FM(AVB0_MII_RXC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR4_11_8 FM(AVB0_RD0) FM(AVB0_MII_RD0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR4_15_12 FM(AVB0_RD1) FM(AVB0_MII_RD1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR4_19_16 FM(AVB0_RD2) FM(AVB0_MII_RD2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR4_23_20 FM(AVB0_RD3) FM(AVB0_MII_RD3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR4_27_24 FM(AVB0_TX_CTL) FM(AVB0_MII_TX_EN) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR4_31_28 FM(AVB0_TXC) FM(AVB0_MII_TXC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+/* IP1SR4 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */
+#define IP1SR4_3_0 FM(AVB0_TD0) FM(AVB0_MII_TD0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR4_7_4 FM(AVB0_TD1) FM(AVB0_MII_TD1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR4_11_8 FM(AVB0_TD2) FM(AVB0_MII_TD2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR4_15_12 FM(AVB0_TD3) FM(AVB0_MII_TD3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR4_19_16 FM(AVB0_TXCREFCLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR4_23_20 FM(AVB0_MDIO) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR4_27_24 FM(AVB0_MDC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR4_31_28 FM(AVB0_MAGIC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+/* IP2SR4 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */
+#define IP2SR4_3_0 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2SR4_7_4 FM(AVB0_LINK) FM(AVB0_MII_TX_ER) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2SR4_11_8 FM(AVB0_AVTP_MATCH) FM(AVB0_MII_RX_ER) FM(CC5_OSCOUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2SR4_15_12 FM(AVB0_AVTP_CAPTURE) FM(AVB0_MII_CRS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2SR4_19_16 FM(AVB0_AVTP_PPS) FM(AVB0_MII_COL) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2SR4_23_20 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2SR4_27_24 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2SR4_31_28 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+
+/* IP0SR5 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */
+#define IP0SR5_3_0 FM(AVB1_RX_CTL) FM(AVB1_MII_RX_DV) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR5_7_4 FM(AVB1_RXC) FM(AVB1_MII_RXC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR5_11_8 FM(AVB1_RD0) FM(AVB1_MII_RD0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR5_15_12 FM(AVB1_RD1) FM(AVB1_MII_RD1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR5_19_16 FM(AVB1_RD2) FM(AVB1_MII_RD2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR5_23_20 FM(AVB1_RD3) FM(AVB1_MII_RD3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR5_27_24 FM(AVB1_TX_CTL) FM(AVB1_MII_TX_EN) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR5_31_28 FM(AVB1_TXC) FM(AVB1_MII_TXC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+/* IP1SR5 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */
+#define IP1SR5_3_0 FM(AVB1_TD0) FM(AVB1_MII_TD0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR5_7_4 FM(AVB1_TD1) FM(AVB1_MII_TD1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR5_11_8 FM(AVB1_TD2) FM(AVB1_MII_TD2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR5_15_12 FM(AVB1_TD3) FM(AVB1_MII_TD3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR5_19_16 FM(AVB1_TXCREFCLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR5_23_20 FM(AVB1_MDIO) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR5_27_24 FM(AVB1_MDC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR5_31_28 FM(AVB1_MAGIC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+/* IP2SR5 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */
+#define IP2SR5_3_0 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2SR5_7_4 FM(AVB1_LINK) FM(AVB1_MII_TX_ER) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2SR5_11_8 FM(AVB1_AVTP_MATCH) FM(AVB1_MII_RX_ER) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2SR5_15_12 FM(AVB1_AVTP_CAPTURE) FM(AVB1_MII_CRS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2SR5_19_16 FM(AVB1_AVTP_PPS) FM(AVB1_MII_COL) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2SR5_23_20 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2SR5_27_24 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2SR5_31_28 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+
+#define PINMUX_GPSR \
+ \
+ GPSR1_30 \
+ GPSR1_29 \
+ GPSR1_28 \
+GPSR0_27 GPSR1_27 \
+GPSR0_26 GPSR1_26 GPSR4_26 \
+GPSR0_25 GPSR1_25 GPSR4_25 \
+GPSR0_24 GPSR1_24 GPSR2_24 GPSR4_24 \
+GPSR0_23 GPSR1_23 GPSR2_23 GPSR4_23 \
+GPSR0_22 GPSR1_22 GPSR2_22 GPSR4_22 \
+GPSR0_21 GPSR1_21 GPSR2_21 GPSR4_21 \
+GPSR0_20 GPSR1_20 GPSR2_20 GPSR4_20 GPSR5_20 GPSR6_20 GPSR7_20 GPSR8_20 GPSR9_20 \
+GPSR0_19 GPSR1_19 GPSR2_19 GPSR4_19 GPSR5_19 GPSR6_19 GPSR7_19 GPSR8_19 GPSR9_19 \
+GPSR0_18 GPSR1_18 GPSR2_18 GPSR4_18 GPSR5_18 GPSR6_18 GPSR7_18 GPSR8_18 GPSR9_18 \
+GPSR0_17 GPSR1_17 GPSR2_17 GPSR4_17 GPSR5_17 GPSR6_17 GPSR7_17 GPSR8_17 GPSR9_17 \
+GPSR0_16 GPSR1_16 GPSR2_16 GPSR3_16 GPSR4_16 GPSR5_16 GPSR6_16 GPSR7_16 GPSR8_16 GPSR9_16 \
+GPSR0_15 GPSR1_15 GPSR2_15 GPSR3_15 GPSR4_15 GPSR5_15 GPSR6_15 GPSR7_15 GPSR8_15 GPSR9_15 \
+GPSR0_14 GPSR1_14 GPSR2_14 GPSR3_14 GPSR4_14 GPSR5_14 GPSR6_14 GPSR7_14 GPSR8_14 GPSR9_14 \
+GPSR0_13 GPSR1_13 GPSR2_13 GPSR3_13 GPSR4_13 GPSR5_13 GPSR6_13 GPSR7_13 GPSR8_13 GPSR9_13 \
+GPSR0_12 GPSR1_12 GPSR2_12 GPSR3_12 GPSR4_12 GPSR5_12 GPSR6_12 GPSR7_12 GPSR8_12 GPSR9_12 \
+GPSR0_11 GPSR1_11 GPSR2_11 GPSR3_11 GPSR4_11 GPSR5_11 GPSR6_11 GPSR7_11 GPSR8_11 GPSR9_11 \
+GPSR0_10 GPSR1_10 GPSR2_10 GPSR3_10 GPSR4_10 GPSR5_10 GPSR6_10 GPSR7_10 GPSR8_10 GPSR9_10 \
+GPSR0_9 GPSR1_9 GPSR2_9 GPSR3_9 GPSR4_9 GPSR5_9 GPSR6_9 GPSR7_9 GPSR8_9 GPSR9_9 \
+GPSR0_8 GPSR1_8 GPSR2_8 GPSR3_8 GPSR4_8 GPSR5_8 GPSR6_8 GPSR7_8 GPSR8_8 GPSR9_8 \
+GPSR0_7 GPSR1_7 GPSR2_7 GPSR3_7 GPSR4_7 GPSR5_7 GPSR6_7 GPSR7_7 GPSR8_7 GPSR9_7 \
+GPSR0_6 GPSR1_6 GPSR2_6 GPSR3_6 GPSR4_6 GPSR5_6 GPSR6_6 GPSR7_6 GPSR8_6 GPSR9_6 \
+GPSR0_5 GPSR1_5 GPSR2_5 GPSR3_5 GPSR4_5 GPSR5_5 GPSR6_5 GPSR7_5 GPSR8_5 GPSR9_5 \
+GPSR0_4 GPSR1_4 GPSR2_4 GPSR3_4 GPSR4_4 GPSR5_4 GPSR6_4 GPSR7_4 GPSR8_4 GPSR9_4 \
+GPSR0_3 GPSR1_3 GPSR2_3 GPSR3_3 GPSR4_3 GPSR5_3 GPSR6_3 GPSR7_3 GPSR8_3 GPSR9_3 \
+GPSR0_2 GPSR1_2 GPSR2_2 GPSR3_2 GPSR4_2 GPSR5_2 GPSR6_2 GPSR7_2 GPSR8_2 GPSR9_2 \
+GPSR0_1 GPSR1_1 GPSR2_1 GPSR3_1 GPSR4_1 GPSR5_1 GPSR6_1 GPSR7_1 GPSR8_1 GPSR9_1 \
+GPSR0_0 GPSR1_0 GPSR2_0 GPSR3_0 GPSR4_0 GPSR5_0 GPSR6_0 GPSR7_0 GPSR8_0 GPSR9_0
+
+#define PINMUX_IPSR \
+\
+FM(IP0SR1_3_0) IP0SR1_3_0 FM(IP1SR1_3_0) IP1SR1_3_0 FM(IP2SR1_3_0) IP2SR1_3_0 FM(IP3SR1_3_0) IP3SR1_3_0 \
+FM(IP0SR1_7_4) IP0SR1_7_4 FM(IP1SR1_7_4) IP1SR1_7_4 FM(IP2SR1_7_4) IP2SR1_7_4 FM(IP3SR1_7_4) IP3SR1_7_4 \
+FM(IP0SR1_11_8) IP0SR1_11_8 FM(IP1SR1_11_8) IP1SR1_11_8 FM(IP2SR1_11_8) IP2SR1_11_8 FM(IP3SR1_11_8) IP3SR1_11_8 \
+FM(IP0SR1_15_12) IP0SR1_15_12 FM(IP1SR1_15_12) IP1SR1_15_12 FM(IP2SR1_15_12) IP2SR1_15_12 FM(IP3SR1_15_12) IP3SR1_15_12 \
+FM(IP0SR1_19_16) IP0SR1_19_16 FM(IP1SR1_19_16) IP1SR1_19_16 FM(IP2SR1_19_16) IP2SR1_19_16 FM(IP3SR1_19_16) IP3SR1_19_16 \
+FM(IP0SR1_23_20) IP0SR1_23_20 FM(IP1SR1_23_20) IP1SR1_23_20 FM(IP2SR1_23_20) IP2SR1_23_20 FM(IP3SR1_23_20) IP3SR1_23_20 \
+FM(IP0SR1_27_24) IP0SR1_27_24 FM(IP1SR1_27_24) IP1SR1_27_24 FM(IP2SR1_27_24) IP2SR1_27_24 FM(IP3SR1_27_24) IP3SR1_27_24 \
+FM(IP0SR1_31_28) IP0SR1_31_28 FM(IP1SR1_31_28) IP1SR1_31_28 FM(IP2SR1_31_28) IP2SR1_31_28 FM(IP3SR1_31_28) IP3SR1_31_28 \
+\
+FM(IP0SR2_3_0) IP0SR2_3_0 FM(IP1SR2_3_0) IP1SR2_3_0 FM(IP2SR2_3_0) IP2SR2_3_0 \
+FM(IP0SR2_7_4) IP0SR2_7_4 FM(IP1SR2_7_4) IP1SR2_7_4 FM(IP2SR2_7_4) IP2SR2_7_4 \
+FM(IP0SR2_11_8) IP0SR2_11_8 FM(IP1SR2_11_8) IP1SR2_11_8 FM(IP2SR2_11_8) IP2SR2_11_8 \
+FM(IP0SR2_15_12) IP0SR2_15_12 FM(IP1SR2_15_12) IP1SR2_15_12 FM(IP2SR2_15_12) IP2SR2_15_12 \
+FM(IP0SR2_19_16) IP0SR2_19_16 FM(IP1SR2_19_16) IP1SR2_19_16 FM(IP2SR2_19_16) IP2SR2_19_16 \
+FM(IP0SR2_23_20) IP0SR2_23_20 FM(IP1SR2_23_20) IP1SR2_23_20 FM(IP2SR2_23_20) IP2SR2_23_20 \
+FM(IP0SR2_27_24) IP0SR2_27_24 FM(IP1SR2_27_24) IP1SR2_27_24 FM(IP2SR2_27_24) IP2SR2_27_24 \
+FM(IP0SR2_31_28) IP0SR2_31_28 FM(IP1SR2_31_28) IP1SR2_31_28 FM(IP2SR2_31_28) IP2SR2_31_28 \
+\
+FM(IP0SR3_3_0) IP0SR3_3_0 FM(IP1SR3_3_0) IP1SR3_3_0 \
+FM(IP0SR3_7_4) IP0SR3_7_4 FM(IP1SR3_7_4) IP1SR3_7_4 \
+FM(IP0SR3_11_8) IP0SR3_11_8 FM(IP1SR3_11_8) IP1SR3_11_8 \
+FM(IP0SR3_15_12) IP0SR3_15_12 FM(IP1SR3_15_12) IP1SR3_15_12 \
+FM(IP0SR3_19_16) IP0SR3_19_16 FM(IP1SR3_19_16) IP1SR3_19_16 \
+FM(IP0SR3_23_20) IP0SR3_23_20 FM(IP1SR3_23_20) IP1SR3_23_20 \
+FM(IP0SR3_27_24) IP0SR3_27_24 FM(IP1SR3_27_24) IP1SR3_27_24 \
+FM(IP0SR3_31_28) IP0SR3_31_28 FM(IP1SR3_31_28) IP1SR3_31_28 \
+\
+FM(IP0SR4_3_0) IP0SR4_3_0 FM(IP1SR4_3_0) IP1SR4_3_0 FM(IP2SR4_3_0) IP2SR4_3_0 \
+FM(IP0SR4_7_4) IP0SR4_7_4 FM(IP1SR4_7_4) IP1SR4_7_4 FM(IP2SR4_7_4) IP2SR4_7_4 \
+FM(IP0SR4_11_8) IP0SR4_11_8 FM(IP1SR4_11_8) IP1SR4_11_8 FM(IP2SR4_11_8) IP2SR4_11_8 \
+FM(IP0SR4_15_12) IP0SR4_15_12 FM(IP1SR4_15_12) IP1SR4_15_12 FM(IP2SR4_15_12) IP2SR4_15_12 \
+FM(IP0SR4_19_16) IP0SR4_19_16 FM(IP1SR4_19_16) IP1SR4_19_16 FM(IP2SR4_19_16) IP2SR4_19_16 \
+FM(IP0SR4_23_20) IP0SR4_23_20 FM(IP1SR4_23_20) IP1SR4_23_20 FM(IP2SR4_23_20) IP2SR4_23_20 \
+FM(IP0SR4_27_24) IP0SR4_27_24 FM(IP1SR4_27_24) IP1SR4_27_24 FM(IP2SR4_27_24) IP2SR4_27_24 \
+FM(IP0SR4_31_28) IP0SR4_31_28 FM(IP1SR4_31_28) IP1SR4_31_28 FM(IP2SR4_31_28) IP2SR4_31_28 \
+\
+FM(IP0SR5_3_0) IP0SR5_3_0 FM(IP1SR5_3_0) IP1SR5_3_0 FM(IP2SR5_3_0) IP2SR5_3_0 \
+FM(IP0SR5_7_4) IP0SR5_7_4 FM(IP1SR5_7_4) IP1SR5_7_4 FM(IP2SR5_7_4) IP2SR5_7_4 \
+FM(IP0SR5_11_8) IP0SR5_11_8 FM(IP1SR5_11_8) IP1SR5_11_8 FM(IP2SR5_11_8) IP2SR5_11_8 \
+FM(IP0SR5_15_12) IP0SR5_15_12 FM(IP1SR5_15_12) IP1SR5_15_12 FM(IP2SR5_15_12) IP2SR5_15_12 \
+FM(IP0SR5_19_16) IP0SR5_19_16 FM(IP1SR5_19_16) IP1SR5_19_16 FM(IP2SR5_19_16) IP2SR5_19_16 \
+FM(IP0SR5_23_20) IP0SR5_23_20 FM(IP1SR5_23_20) IP1SR5_23_20 FM(IP2SR5_23_20) IP2SR5_23_20 \
+FM(IP0SR5_27_24) IP0SR5_27_24 FM(IP1SR5_27_24) IP1SR5_27_24 FM(IP2SR5_27_24) IP2SR5_27_24 \
+FM(IP0SR5_31_28) IP0SR5_31_28 FM(IP1SR5_31_28) IP1SR5_31_28 FM(IP2SR5_31_28) IP2SR5_31_28
+
+/* MOD_SEL2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */
+#define MOD_SEL2_14_15 FM(SEL_I2C6_0) F_(0, 0) F_(0, 0) FM(SEL_I2C6_3)
+#define MOD_SEL2_12_13 FM(SEL_I2C5_0) F_(0, 0) F_(0, 0) FM(SEL_I2C5_3)
+#define MOD_SEL2_10_11 FM(SEL_I2C4_0) F_(0, 0) F_(0, 0) FM(SEL_I2C4_3)
+#define MOD_SEL2_8_9 FM(SEL_I2C3_0) F_(0, 0) F_(0, 0) FM(SEL_I2C3_3)
+#define MOD_SEL2_6_7 FM(SEL_I2C2_0) F_(0, 0) F_(0, 0) FM(SEL_I2C2_3)
+#define MOD_SEL2_4_5 FM(SEL_I2C1_0) F_(0, 0) F_(0, 0) FM(SEL_I2C1_3)
+#define MOD_SEL2_2_3 FM(SEL_I2C0_0) F_(0, 0) F_(0, 0) FM(SEL_I2C0_3)
+
+#define PINMUX_MOD_SELS \
+\
+MOD_SEL2_14_15 \
+MOD_SEL2_12_13 \
+MOD_SEL2_10_11 \
+MOD_SEL2_8_9 \
+MOD_SEL2_6_7 \
+MOD_SEL2_4_5 \
+MOD_SEL2_2_3
+
+#define PINMUX_PHYS \
+ FM(SCL0) FM(SDA0) FM(SCL1) FM(SDA1) FM(SCL2) FM(SDA2) FM(SCL3) FM(SDA3) \
+ FM(SCL4) FM(SDA4) FM(SCL5) FM(SDA5) FM(SCL6) FM(SDA6)
+
+enum {
+ PINMUX_RESERVED = 0,
+
+ PINMUX_DATA_BEGIN,
+ GP_ALL(DATA),
+ PINMUX_DATA_END,
+
+#define F_(x, y)
+#define FM(x) FN_##x,
+ PINMUX_FUNCTION_BEGIN,
+ GP_ALL(FN),
+ PINMUX_GPSR
+ PINMUX_IPSR
+ PINMUX_MOD_SELS
+ PINMUX_FUNCTION_END,
+#undef F_
+#undef FM
+
+#define F_(x, y)
+#define FM(x) x##_MARK,
+ PINMUX_MARK_BEGIN,
+ PINMUX_GPSR
+ PINMUX_IPSR
+ PINMUX_MOD_SELS
+ PINMUX_PHYS
+ PINMUX_MARK_END,
+#undef F_
+#undef FM
+};
+
+static const u16 pinmux_data[] = {
+ PINMUX_DATA_GP_ALL(),
+
+ PINMUX_SINGLE(MMC_D7),
+ PINMUX_SINGLE(MMC_D6),
+ PINMUX_SINGLE(MMC_D5),
+ PINMUX_SINGLE(MMC_D4),
+ PINMUX_SINGLE(MMC_SD_CLK),
+ PINMUX_SINGLE(MMC_SD_D3),
+ PINMUX_SINGLE(MMC_SD_D2),
+ PINMUX_SINGLE(MMC_SD_D1),
+ PINMUX_SINGLE(MMC_SD_D0),
+ PINMUX_SINGLE(MMC_SD_CMD),
+ PINMUX_SINGLE(MMC_DS),
+
+ PINMUX_SINGLE(SD_CD),
+ PINMUX_SINGLE(SD_WP),
+
+ PINMUX_SINGLE(RPC_INT_N),
+ PINMUX_SINGLE(RPC_WP_N),
+ PINMUX_SINGLE(RPC_RESET_N),
+
+ PINMUX_SINGLE(QSPI1_SSL),
+ PINMUX_SINGLE(QSPI1_IO3),
+ PINMUX_SINGLE(QSPI1_IO2),
+ PINMUX_SINGLE(QSPI1_MISO_IO1),
+ PINMUX_SINGLE(QSPI1_MOSI_IO0),
+ PINMUX_SINGLE(QSPI1_SPCLK),
+ PINMUX_SINGLE(QSPI0_SSL),
+ PINMUX_SINGLE(QSPI0_IO3),
+ PINMUX_SINGLE(QSPI0_IO2),
+ PINMUX_SINGLE(QSPI0_MISO_IO1),
+ PINMUX_SINGLE(QSPI0_MOSI_IO0),
+ PINMUX_SINGLE(QSPI0_SPCLK),
+
+ PINMUX_SINGLE(TCLK2_A),
+
+ PINMUX_SINGLE(CANFD7_RX),
+ PINMUX_SINGLE(CANFD7_TX),
+ PINMUX_SINGLE(CANFD6_RX),
+ PINMUX_SINGLE(CANFD1_RX),
+ PINMUX_SINGLE(CANFD1_TX),
+ PINMUX_SINGLE(CAN_CLK),
+
+ PINMUX_SINGLE(AVS1),
+ PINMUX_SINGLE(AVS0),
+
+ PINMUX_SINGLE(PCIE3_CLKREQ_N),
+ PINMUX_SINGLE(PCIE2_CLKREQ_N),
+ PINMUX_SINGLE(PCIE1_CLKREQ_N),
+ PINMUX_SINGLE(PCIE0_CLKREQ_N),
+
+ PINMUX_SINGLE(AVB0_PHY_INT),
+ PINMUX_SINGLE(AVB0_MAGIC),
+ PINMUX_SINGLE(AVB0_MDC),
+ PINMUX_SINGLE(AVB0_MDIO),
+ PINMUX_SINGLE(AVB0_TXCREFCLK),
+
+ PINMUX_SINGLE(AVB1_PHY_INT),
+ PINMUX_SINGLE(AVB1_MAGIC),
+ PINMUX_SINGLE(AVB1_MDC),
+ PINMUX_SINGLE(AVB1_MDIO),
+ PINMUX_SINGLE(AVB1_TXCREFCLK),
+
+ PINMUX_SINGLE(AVB2_AVTP_PPS),
+ PINMUX_SINGLE(AVB2_AVTP_CAPTURE),
+ PINMUX_SINGLE(AVB2_AVTP_MATCH),
+ PINMUX_SINGLE(AVB2_LINK),
+ PINMUX_SINGLE(AVB2_PHY_INT),
+ PINMUX_SINGLE(AVB2_MAGIC),
+ PINMUX_SINGLE(AVB2_MDC),
+ PINMUX_SINGLE(AVB2_MDIO),
+ PINMUX_SINGLE(AVB2_TXCREFCLK),
+ PINMUX_SINGLE(AVB2_TD3),
+ PINMUX_SINGLE(AVB2_TD2),
+ PINMUX_SINGLE(AVB2_TD1),
+ PINMUX_SINGLE(AVB2_TD0),
+ PINMUX_SINGLE(AVB2_TXC),
+ PINMUX_SINGLE(AVB2_TX_CTL),
+ PINMUX_SINGLE(AVB2_RD3),
+ PINMUX_SINGLE(AVB2_RD2),
+ PINMUX_SINGLE(AVB2_RD1),
+ PINMUX_SINGLE(AVB2_RD0),
+ PINMUX_SINGLE(AVB2_RXC),
+ PINMUX_SINGLE(AVB2_RX_CTL),
+
+ PINMUX_SINGLE(AVB3_AVTP_PPS),
+ PINMUX_SINGLE(AVB3_AVTP_CAPTURE),
+ PINMUX_SINGLE(AVB3_AVTP_MATCH),
+ PINMUX_SINGLE(AVB3_LINK),
+ PINMUX_SINGLE(AVB3_PHY_INT),
+ PINMUX_SINGLE(AVB3_MAGIC),
+ PINMUX_SINGLE(AVB3_MDC),
+ PINMUX_SINGLE(AVB3_MDIO),
+ PINMUX_SINGLE(AVB3_TXCREFCLK),
+ PINMUX_SINGLE(AVB3_TD3),
+ PINMUX_SINGLE(AVB3_TD2),
+ PINMUX_SINGLE(AVB3_TD1),
+ PINMUX_SINGLE(AVB3_TD0),
+ PINMUX_SINGLE(AVB3_TXC),
+ PINMUX_SINGLE(AVB3_TX_CTL),
+ PINMUX_SINGLE(AVB3_RD3),
+ PINMUX_SINGLE(AVB3_RD2),
+ PINMUX_SINGLE(AVB3_RD1),
+ PINMUX_SINGLE(AVB3_RD0),
+ PINMUX_SINGLE(AVB3_RXC),
+ PINMUX_SINGLE(AVB3_RX_CTL),
+
+ PINMUX_SINGLE(AVB4_AVTP_PPS),
+ PINMUX_SINGLE(AVB4_AVTP_CAPTURE),
+ PINMUX_SINGLE(AVB4_AVTP_MATCH),
+ PINMUX_SINGLE(AVB4_LINK),
+ PINMUX_SINGLE(AVB4_PHY_INT),
+ PINMUX_SINGLE(AVB4_MAGIC),
+ PINMUX_SINGLE(AVB4_MDC),
+ PINMUX_SINGLE(AVB4_MDIO),
+ PINMUX_SINGLE(AVB4_TXCREFCLK),
+ PINMUX_SINGLE(AVB4_TD3),
+ PINMUX_SINGLE(AVB4_TD2),
+ PINMUX_SINGLE(AVB4_TD1),
+ PINMUX_SINGLE(AVB4_TD0),
+ PINMUX_SINGLE(AVB4_TXC),
+ PINMUX_SINGLE(AVB4_TX_CTL),
+ PINMUX_SINGLE(AVB4_RD3),
+ PINMUX_SINGLE(AVB4_RD2),
+ PINMUX_SINGLE(AVB4_RD1),
+ PINMUX_SINGLE(AVB4_RD0),
+ PINMUX_SINGLE(AVB4_RXC),
+ PINMUX_SINGLE(AVB4_RX_CTL),
+
+ PINMUX_SINGLE(AVB5_AVTP_PPS),
+ PINMUX_SINGLE(AVB5_AVTP_CAPTURE),
+ PINMUX_SINGLE(AVB5_AVTP_MATCH),
+ PINMUX_SINGLE(AVB5_LINK),
+ PINMUX_SINGLE(AVB5_PHY_INT),
+ PINMUX_SINGLE(AVB5_MAGIC),
+ PINMUX_SINGLE(AVB5_MDC),
+ PINMUX_SINGLE(AVB5_MDIO),
+ PINMUX_SINGLE(AVB5_TXCREFCLK),
+ PINMUX_SINGLE(AVB5_TD3),
+ PINMUX_SINGLE(AVB5_TD2),
+ PINMUX_SINGLE(AVB5_TD1),
+ PINMUX_SINGLE(AVB5_TD0),
+ PINMUX_SINGLE(AVB5_TXC),
+ PINMUX_SINGLE(AVB5_TX_CTL),
+ PINMUX_SINGLE(AVB5_RD3),
+ PINMUX_SINGLE(AVB5_RD2),
+ PINMUX_SINGLE(AVB5_RD1),
+ PINMUX_SINGLE(AVB5_RD0),
+ PINMUX_SINGLE(AVB5_RXC),
+ PINMUX_SINGLE(AVB5_RX_CTL),
+
+ /* IP0SR1 */
+ PINMUX_IPSR_GPSR(IP0SR1_3_0, SCIF_CLK),
+ PINMUX_IPSR_GPSR(IP0SR1_3_0, A0),
+
+ PINMUX_IPSR_GPSR(IP0SR1_7_4, HRX0),
+ PINMUX_IPSR_GPSR(IP0SR1_7_4, RX0),
+ PINMUX_IPSR_GPSR(IP0SR1_7_4, A1),
+
+ PINMUX_IPSR_GPSR(IP0SR1_11_8, HSCK0),
+ PINMUX_IPSR_GPSR(IP0SR1_11_8, SCK0),
+ PINMUX_IPSR_GPSR(IP0SR1_11_8, A2),
+
+ PINMUX_IPSR_GPSR(IP0SR1_15_12, HRTS0_N),
+ PINMUX_IPSR_GPSR(IP0SR1_15_12, RTS0_N),
+ PINMUX_IPSR_GPSR(IP0SR1_15_12, A3),
+
+ PINMUX_IPSR_GPSR(IP0SR1_19_16, HCTS0_N),
+ PINMUX_IPSR_GPSR(IP0SR1_19_16, CTS0_N),
+ PINMUX_IPSR_GPSR(IP0SR1_19_16, A4),
+
+ PINMUX_IPSR_GPSR(IP0SR1_23_20, HTX0),
+ PINMUX_IPSR_GPSR(IP0SR1_23_20, TX0),
+ PINMUX_IPSR_GPSR(IP0SR1_23_20, A5),
+
+ PINMUX_IPSR_GPSR(IP0SR1_27_24, MSIOF0_RXD),
+ PINMUX_IPSR_GPSR(IP0SR1_27_24, DU_DR2),
+ PINMUX_IPSR_GPSR(IP0SR1_27_24, A6),
+
+ PINMUX_IPSR_GPSR(IP0SR1_31_28, MSIOF0_TXD),
+ PINMUX_IPSR_GPSR(IP0SR1_31_28, DU_DR3),
+ PINMUX_IPSR_GPSR(IP0SR1_31_28, A7),
+
+ /* IP1SR1 */
+ PINMUX_IPSR_GPSR(IP1SR1_3_0, MSIOF0_SCK),
+ PINMUX_IPSR_GPSR(IP1SR1_3_0, DU_DR4),
+ PINMUX_IPSR_GPSR(IP1SR1_3_0, A8),
+
+ PINMUX_IPSR_GPSR(IP1SR1_7_4, MSIOF0_SYNC),
+ PINMUX_IPSR_GPSR(IP1SR1_7_4, DU_DR5),
+ PINMUX_IPSR_GPSR(IP1SR1_7_4, A9),
+
+ PINMUX_IPSR_GPSR(IP1SR1_11_8, MSIOF0_SS1),
+ PINMUX_IPSR_GPSR(IP1SR1_11_8, DU_DR6),
+ PINMUX_IPSR_GPSR(IP1SR1_11_8, A10),
+
+ PINMUX_IPSR_GPSR(IP1SR1_15_12, MSIOF0_SS2),
+ PINMUX_IPSR_GPSR(IP1SR1_15_12, DU_DR7),
+ PINMUX_IPSR_GPSR(IP1SR1_15_12, A11),
+
+ PINMUX_IPSR_GPSR(IP1SR1_19_16, MSIOF1_RXD),
+ PINMUX_IPSR_GPSR(IP1SR1_19_16, DU_DG2),
+ PINMUX_IPSR_GPSR(IP1SR1_19_16, A12),
+
+ PINMUX_IPSR_GPSR(IP1SR1_23_20, MSIOF1_TXD),
+ PINMUX_IPSR_GPSR(IP1SR1_23_20, HRX3),
+ PINMUX_IPSR_GPSR(IP1SR1_23_20, SCK3),
+ PINMUX_IPSR_GPSR(IP1SR1_23_20, DU_DG3),
+ PINMUX_IPSR_GPSR(IP1SR1_23_20, A13),
+
+ PINMUX_IPSR_GPSR(IP1SR1_27_24, MSIOF1_SCK),
+ PINMUX_IPSR_GPSR(IP1SR1_27_24, HSCK3),
+ PINMUX_IPSR_GPSR(IP1SR1_27_24, CTS3_N),
+ PINMUX_IPSR_GPSR(IP1SR1_27_24, DU_DG4),
+ PINMUX_IPSR_GPSR(IP1SR1_27_24, A14),
+
+ PINMUX_IPSR_GPSR(IP1SR1_31_28, MSIOF1_SYNC),
+ PINMUX_IPSR_GPSR(IP1SR1_31_28, HRTS3_N),
+ PINMUX_IPSR_GPSR(IP1SR1_31_28, RTS3_N),
+ PINMUX_IPSR_GPSR(IP1SR1_31_28, DU_DG5),
+ PINMUX_IPSR_GPSR(IP1SR1_31_28, A15),
+
+ /* IP2SR1 */
+ PINMUX_IPSR_GPSR(IP2SR1_3_0, MSIOF1_SS1),
+ PINMUX_IPSR_GPSR(IP2SR1_3_0, HCTS3_N),
+ PINMUX_IPSR_GPSR(IP2SR1_3_0, RX3),
+ PINMUX_IPSR_GPSR(IP2SR1_3_0, DU_DG6),
+ PINMUX_IPSR_GPSR(IP2SR1_3_0, A16),
+
+ PINMUX_IPSR_GPSR(IP2SR1_7_4, MSIOF1_SS2),
+ PINMUX_IPSR_GPSR(IP2SR1_7_4, HTX3),
+ PINMUX_IPSR_GPSR(IP2SR1_7_4, TX3),
+ PINMUX_IPSR_GPSR(IP2SR1_7_4, DU_DG7),
+ PINMUX_IPSR_GPSR(IP2SR1_7_4, A17),
+
+ PINMUX_IPSR_GPSR(IP2SR1_11_8, MSIOF2_RXD),
+ PINMUX_IPSR_GPSR(IP2SR1_11_8, HSCK1),
+ PINMUX_IPSR_GPSR(IP2SR1_11_8, SCK1),
+ PINMUX_IPSR_GPSR(IP2SR1_11_8, DU_DB2),
+ PINMUX_IPSR_GPSR(IP2SR1_11_8, A18),
+
+ PINMUX_IPSR_GPSR(IP2SR1_15_12, MSIOF2_TXD),
+ PINMUX_IPSR_GPSR(IP2SR1_15_12, HCTS1_N),
+ PINMUX_IPSR_GPSR(IP2SR1_15_12, CTS1_N),
+ PINMUX_IPSR_GPSR(IP2SR1_15_12, DU_DB3),
+ PINMUX_IPSR_GPSR(IP2SR1_15_12, A19),
+
+ PINMUX_IPSR_GPSR(IP2SR1_19_16, MSIOF2_SCK),
+ PINMUX_IPSR_GPSR(IP2SR1_19_16, HRTS1_N),
+ PINMUX_IPSR_GPSR(IP2SR1_19_16, RTS1_N),
+ PINMUX_IPSR_GPSR(IP2SR1_19_16, DU_DB4),
+ PINMUX_IPSR_GPSR(IP2SR1_19_16, A20),
+
+ PINMUX_IPSR_GPSR(IP2SR1_23_20, MSIOF2_SYNC),
+ PINMUX_IPSR_GPSR(IP2SR1_23_20, HRX1),
+ PINMUX_IPSR_GPSR(IP2SR1_23_20, RX1_A),
+ PINMUX_IPSR_GPSR(IP2SR1_23_20, DU_DB5),
+ PINMUX_IPSR_GPSR(IP2SR1_23_20, A21),
+
+ PINMUX_IPSR_GPSR(IP2SR1_27_24, MSIOF2_SS1),
+ PINMUX_IPSR_GPSR(IP2SR1_27_24, HTX1),
+ PINMUX_IPSR_GPSR(IP2SR1_27_24, TX1_A),
+ PINMUX_IPSR_GPSR(IP2SR1_27_24, DU_DB6),
+ PINMUX_IPSR_GPSR(IP2SR1_27_24, A22),
+
+ PINMUX_IPSR_GPSR(IP2SR1_31_28, MSIOF2_SS2),
+ PINMUX_IPSR_GPSR(IP2SR1_31_28, TCLK1_B),
+ PINMUX_IPSR_GPSR(IP2SR1_31_28, DU_DB7),
+ PINMUX_IPSR_GPSR(IP2SR1_31_28, A23),
+
+ /* IP3SR1 */
+ PINMUX_IPSR_GPSR(IP3SR1_3_0, IRQ0),
+ PINMUX_IPSR_GPSR(IP3SR1_3_0, DU_DOTCLKOUT),
+ PINMUX_IPSR_GPSR(IP3SR1_3_0, A24),
+
+ PINMUX_IPSR_GPSR(IP3SR1_7_4, IRQ1),
+ PINMUX_IPSR_GPSR(IP3SR1_7_4, DU_HSYNC),
+ PINMUX_IPSR_GPSR(IP3SR1_7_4, A25),
+
+ PINMUX_IPSR_GPSR(IP3SR1_11_8, IRQ2),
+ PINMUX_IPSR_GPSR(IP3SR1_11_8, DU_VSYNC),
+ PINMUX_IPSR_GPSR(IP3SR1_11_8, CS1_N_A26),
+
+ PINMUX_IPSR_GPSR(IP3SR1_15_12, IRQ3),
+ PINMUX_IPSR_GPSR(IP3SR1_15_12, DU_ODDF_DISP_CDE),
+ PINMUX_IPSR_GPSR(IP3SR1_15_12, CS0_N),
+
+ PINMUX_IPSR_GPSR(IP3SR1_19_16, GP1_28),
+ PINMUX_IPSR_GPSR(IP3SR1_19_16, D0),
+
+ PINMUX_IPSR_GPSR(IP3SR1_23_20, GP1_29),
+ PINMUX_IPSR_GPSR(IP3SR1_23_20, D1),
+
+ PINMUX_IPSR_GPSR(IP3SR1_27_24, GP1_30),
+ PINMUX_IPSR_GPSR(IP3SR1_27_24, D2),
+
+ /* IP0SR2 */
+ PINMUX_IPSR_GPSR(IP0SR2_3_0, IPC_CLKIN),
+ PINMUX_IPSR_GPSR(IP0SR2_3_0, IPC_CLKEN_IN),
+ PINMUX_IPSR_GPSR(IP0SR2_3_0, DU_DOTCLKIN),
+
+ PINMUX_IPSR_GPSR(IP0SR2_7_4, IPC_CLKOUT),
+ PINMUX_IPSR_GPSR(IP0SR2_7_4, IPC_CLKEN_OUT),
+
+ /* GP2_02 = SCL0 */
+ PINMUX_IPSR_MSEL(IP0SR2_11_8, GP2_02, SEL_I2C0_0),
+ PINMUX_IPSR_MSEL(IP0SR2_11_8, D3, SEL_I2C0_0),
+ PINMUX_IPSR_PHYS(IP0SR2_11_8, SCL0, SEL_I2C0_3),
+
+ /* GP2_03 = SDA0 */
+ PINMUX_IPSR_MSEL(IP0SR2_15_12, GP2_03, SEL_I2C0_0),
+ PINMUX_IPSR_MSEL(IP0SR2_15_12, D4, SEL_I2C0_0),
+ PINMUX_IPSR_PHYS(IP0SR2_15_12, SDA0, SEL_I2C0_3),
+
+ /* GP2_04 = SCL1 */
+ PINMUX_IPSR_MSEL(IP0SR2_19_16, GP2_04, SEL_I2C1_0),
+ PINMUX_IPSR_MSEL(IP0SR2_19_16, MSIOF4_RXD, SEL_I2C1_0),
+ PINMUX_IPSR_MSEL(IP0SR2_19_16, D5, SEL_I2C1_0),
+ PINMUX_IPSR_PHYS(IP0SR2_19_16, SCL1, SEL_I2C1_3),
+
+ /* GP2_05 = SDA1 */
+ PINMUX_IPSR_MSEL(IP0SR2_23_20, GP2_05, SEL_I2C1_0),
+ PINMUX_IPSR_MSEL(IP0SR2_23_20, HSCK2, SEL_I2C1_0),
+ PINMUX_IPSR_MSEL(IP0SR2_23_20, MSIOF4_TXD, SEL_I2C1_0),
+ PINMUX_IPSR_MSEL(IP0SR2_23_20, SCK4, SEL_I2C1_0),
+ PINMUX_IPSR_MSEL(IP0SR2_23_20, D6, SEL_I2C1_0),
+ PINMUX_IPSR_PHYS(IP0SR2_23_20, SDA1, SEL_I2C1_3),
+
+ /* GP2_06 = SCL2 */
+ PINMUX_IPSR_MSEL(IP0SR2_27_24, GP2_06, SEL_I2C2_0),
+ PINMUX_IPSR_MSEL(IP0SR2_27_24, HCTS2_N, SEL_I2C2_0),
+ PINMUX_IPSR_MSEL(IP0SR2_27_24, MSIOF4_SCK, SEL_I2C2_0),
+ PINMUX_IPSR_MSEL(IP0SR2_27_24, CTS4_N, SEL_I2C2_0),
+ PINMUX_IPSR_MSEL(IP0SR2_27_24, D7, SEL_I2C2_0),
+ PINMUX_IPSR_PHYS(IP0SR2_27_24, SCL2, SEL_I2C2_3),
+
+ /* GP2_07 = SDA2 */
+ PINMUX_IPSR_MSEL(IP0SR2_31_28, GP2_07, SEL_I2C2_0),
+ PINMUX_IPSR_MSEL(IP0SR2_31_28, HRTS2_N, SEL_I2C2_0),
+ PINMUX_IPSR_MSEL(IP0SR2_31_28, MSIOF4_SYNC, SEL_I2C2_0),
+ PINMUX_IPSR_MSEL(IP0SR2_31_28, RTS4_N, SEL_I2C2_0),
+ PINMUX_IPSR_MSEL(IP0SR2_31_28, D8, SEL_I2C2_0),
+ PINMUX_IPSR_PHYS(IP0SR2_31_28, SDA2, SEL_I2C2_3),
+
+ /* GP2_08 = SCL3 */
+ PINMUX_IPSR_MSEL(IP1SR2_3_0, GP2_08, SEL_I2C3_0),
+ PINMUX_IPSR_MSEL(IP1SR2_3_0, HRX2, SEL_I2C3_0),
+ PINMUX_IPSR_MSEL(IP1SR2_3_0, MSIOF4_SS1, SEL_I2C3_0),
+ PINMUX_IPSR_MSEL(IP1SR2_3_0, RX4, SEL_I2C3_0),
+ PINMUX_IPSR_MSEL(IP1SR2_3_0, D9, SEL_I2C3_0),
+ PINMUX_IPSR_PHYS(IP1SR2_3_0, SCL3, SEL_I2C3_3),
+
+ /* GP2_09 = SDA3 */
+ PINMUX_IPSR_MSEL(IP1SR2_7_4, GP2_09, SEL_I2C3_0),
+ PINMUX_IPSR_MSEL(IP1SR2_7_4, HTX2, SEL_I2C3_0),
+ PINMUX_IPSR_MSEL(IP1SR2_7_4, MSIOF4_SS2, SEL_I2C3_0),
+ PINMUX_IPSR_MSEL(IP1SR2_7_4, TX4, SEL_I2C3_0),
+ PINMUX_IPSR_MSEL(IP1SR2_7_4, D10, SEL_I2C3_0),
+ PINMUX_IPSR_PHYS(IP1SR2_7_4, SDA3, SEL_I2C3_3),
+
+ /* GP2_10 = SCL4 */
+ PINMUX_IPSR_MSEL(IP1SR2_11_8, GP2_10, SEL_I2C4_0),
+ PINMUX_IPSR_MSEL(IP1SR2_11_8, TCLK2_B, SEL_I2C4_0),
+ PINMUX_IPSR_MSEL(IP1SR2_11_8, MSIOF5_RXD, SEL_I2C4_0),
+ PINMUX_IPSR_MSEL(IP1SR2_11_8, D11, SEL_I2C4_0),
+ PINMUX_IPSR_PHYS(IP1SR2_11_8, SCL4, SEL_I2C4_3),
+
+ /* GP2_11 = SDA4 */
+ PINMUX_IPSR_MSEL(IP1SR2_15_12, GP2_11, SEL_I2C4_0),
+ PINMUX_IPSR_MSEL(IP1SR2_15_12, TCLK3, SEL_I2C4_0),
+ PINMUX_IPSR_MSEL(IP1SR2_15_12, MSIOF5_TXD, SEL_I2C4_0),
+ PINMUX_IPSR_MSEL(IP1SR2_15_12, D12, SEL_I2C4_0),
+ PINMUX_IPSR_PHYS(IP1SR2_15_12, SDA4, SEL_I2C4_3),
+
+ /* GP2_12 = SCL5 */
+ PINMUX_IPSR_MSEL(IP1SR2_19_16, GP2_12, SEL_I2C5_0),
+ PINMUX_IPSR_MSEL(IP1SR2_19_16, TCLK4, SEL_I2C5_0),
+ PINMUX_IPSR_MSEL(IP1SR2_19_16, MSIOF5_SCK, SEL_I2C5_0),
+ PINMUX_IPSR_MSEL(IP1SR2_19_16, D13, SEL_I2C5_0),
+ PINMUX_IPSR_PHYS(IP1SR2_19_16, SCL5, SEL_I2C5_3),
+
+ /* GP2_13 = SDA5 */
+ PINMUX_IPSR_MSEL(IP1SR2_23_20, GP2_13, SEL_I2C5_0),
+ PINMUX_IPSR_MSEL(IP1SR2_23_20, MSIOF5_SYNC, SEL_I2C5_0),
+ PINMUX_IPSR_MSEL(IP1SR2_23_20, D14, SEL_I2C5_0),
+ PINMUX_IPSR_PHYS(IP1SR2_23_20, SDA5, SEL_I2C5_3),
+
+ /* GP2_14 = SCL6 */
+ PINMUX_IPSR_MSEL(IP1SR2_27_24, GP2_14, SEL_I2C6_0),
+ PINMUX_IPSR_MSEL(IP1SR2_27_24, IRQ4, SEL_I2C6_0),
+ PINMUX_IPSR_MSEL(IP1SR2_27_24, MSIOF5_SS1, SEL_I2C6_0),
+ PINMUX_IPSR_MSEL(IP1SR2_27_24, D15, SEL_I2C6_0),
+ PINMUX_IPSR_PHYS(IP1SR2_27_24, SCL6, SEL_I2C6_3),
+
+ /* GP2_15 = SDA6 */
+ PINMUX_IPSR_MSEL(IP1SR2_31_28, GP2_15, SEL_I2C6_0),
+ PINMUX_IPSR_MSEL(IP1SR2_31_28, IRQ5, SEL_I2C6_0),
+ PINMUX_IPSR_MSEL(IP1SR2_31_28, MSIOF5_SS2, SEL_I2C6_0),
+ PINMUX_IPSR_MSEL(IP1SR2_31_28, CPG_CPCKOUT, SEL_I2C6_0),
+ PINMUX_IPSR_PHYS(IP1SR2_31_28, SDA6, SEL_I2C6_3),
+
+ /* IP2SR2 */
+ PINMUX_IPSR_GPSR(IP2SR2_3_0, FXR_TXDA_A),
+ PINMUX_IPSR_GPSR(IP2SR2_3_0, MSIOF3_SS1),
+
+ PINMUX_IPSR_GPSR(IP2SR2_7_4, RXDA_EXTFXR_A),
+ PINMUX_IPSR_GPSR(IP2SR2_7_4, MSIOF3_SS2),
+ PINMUX_IPSR_GPSR(IP2SR2_7_4, BS_N),
+
+ PINMUX_IPSR_GPSR(IP2SR2_11_8, FXR_TXDB),
+ PINMUX_IPSR_GPSR(IP2SR2_11_8, MSIOF3_RXD),
+ PINMUX_IPSR_GPSR(IP2SR2_11_8, RD_N),
+
+ PINMUX_IPSR_GPSR(IP2SR2_15_12, RXDB_EXTFXR),
+ PINMUX_IPSR_GPSR(IP2SR2_15_12, MSIOF3_TXD),
+ PINMUX_IPSR_GPSR(IP2SR2_15_12, WE0_N),
+
+ PINMUX_IPSR_GPSR(IP2SR2_19_16, CLK_EXTFXR),
+ PINMUX_IPSR_GPSR(IP2SR2_19_16, MSIOF3_SCK),
+ PINMUX_IPSR_GPSR(IP2SR2_19_16, WE1_N),
+
+ PINMUX_IPSR_GPSR(IP2SR2_23_20, TPU0TO0),
+ PINMUX_IPSR_GPSR(IP2SR2_23_20, MSIOF3_SYNC),
+ PINMUX_IPSR_GPSR(IP2SR2_23_20, RD_WR_N),
+
+ PINMUX_IPSR_GPSR(IP2SR2_27_24, TPU0TO1),
+ PINMUX_IPSR_GPSR(IP2SR2_27_24, CLKOUT),
+
+ PINMUX_IPSR_GPSR(IP2SR2_31_28, TCLK1_A),
+ PINMUX_IPSR_GPSR(IP2SR2_31_28, EX_WAIT0),
+
+ /* IP0SR3 */
+ PINMUX_IPSR_GPSR(IP0SR3_7_4, CANFD0_TX),
+ PINMUX_IPSR_GPSR(IP0SR3_7_4, FXR_TXDA_B),
+ PINMUX_IPSR_GPSR(IP0SR3_7_4, TX1_B),
+
+ PINMUX_IPSR_GPSR(IP0SR3_11_8, CANFD0_RX),
+ PINMUX_IPSR_GPSR(IP0SR3_11_8, RXDA_EXTFXR_B),
+ PINMUX_IPSR_GPSR(IP0SR3_11_8, RX1_B),
+
+ PINMUX_IPSR_GPSR(IP0SR3_23_20, CANFD2_TX),
+ PINMUX_IPSR_GPSR(IP0SR3_23_20, TPU0TO2),
+ PINMUX_IPSR_GPSR(IP0SR3_23_20, PWM0),
+
+ PINMUX_IPSR_GPSR(IP0SR3_27_24, CANFD2_RX),
+ PINMUX_IPSR_GPSR(IP0SR3_27_24, TPU0TO3),
+ PINMUX_IPSR_GPSR(IP0SR3_27_24, PWM1),
+
+ PINMUX_IPSR_GPSR(IP0SR3_31_28, CANFD3_TX),
+ PINMUX_IPSR_GPSR(IP0SR3_31_28, PWM2),
+
+ /* IP1SR3 */
+ PINMUX_IPSR_GPSR(IP1SR3_3_0, CANFD3_RX),
+ PINMUX_IPSR_GPSR(IP1SR3_3_0, PWM3),
+
+ PINMUX_IPSR_GPSR(IP1SR3_7_4, CANFD4_TX),
+ PINMUX_IPSR_GPSR(IP1SR3_7_4, PWM4),
+ PINMUX_IPSR_GPSR(IP1SR3_7_4, FXR_CLKOUT1),
+
+ PINMUX_IPSR_GPSR(IP1SR3_11_8, CANFD4_RX),
+ PINMUX_IPSR_GPSR(IP1SR3_11_8, FXR_CLKOUT2),
+
+ PINMUX_IPSR_GPSR(IP1SR3_15_12, CANFD5_TX),
+ PINMUX_IPSR_GPSR(IP1SR3_15_12, FXR_TXENA_N),
+
+ PINMUX_IPSR_GPSR(IP1SR3_19_16, CANFD5_RX),
+ PINMUX_IPSR_GPSR(IP1SR3_19_16, FXR_TXENB_N),
+
+ PINMUX_IPSR_GPSR(IP1SR3_23_20, CANFD6_TX),
+ PINMUX_IPSR_GPSR(IP1SR3_23_20, STPWT_EXTFXR),
+
+ /* IP0SR4 */
+ PINMUX_IPSR_GPSR(IP0SR4_3_0, AVB0_RX_CTL),
+ PINMUX_IPSR_GPSR(IP0SR4_3_0, AVB0_MII_RX_DV),
+
+ PINMUX_IPSR_GPSR(IP0SR4_7_4, AVB0_RXC),
+ PINMUX_IPSR_GPSR(IP0SR4_7_4, AVB0_MII_RXC),
+
+ PINMUX_IPSR_GPSR(IP0SR4_11_8, AVB0_RD0),
+ PINMUX_IPSR_GPSR(IP0SR4_11_8, AVB0_MII_RD0),
+
+ PINMUX_IPSR_GPSR(IP0SR4_15_12, AVB0_RD1),
+ PINMUX_IPSR_GPSR(IP0SR4_15_12, AVB0_MII_RD1),
+
+ PINMUX_IPSR_GPSR(IP0SR4_19_16, AVB0_RD2),
+ PINMUX_IPSR_GPSR(IP0SR4_19_16, AVB0_MII_RD2),
+
+ PINMUX_IPSR_GPSR(IP0SR4_23_20, AVB0_RD3),
+ PINMUX_IPSR_GPSR(IP0SR4_23_20, AVB0_MII_RD3),
+
+ PINMUX_IPSR_GPSR(IP0SR4_27_24, AVB0_TX_CTL),
+ PINMUX_IPSR_GPSR(IP0SR4_27_24, AVB0_MII_TX_EN),
+
+ PINMUX_IPSR_GPSR(IP0SR4_31_28, AVB0_TXC),
+ PINMUX_IPSR_GPSR(IP0SR4_31_28, AVB0_MII_TXC),
+
+ /* IP1SR4 */
+ PINMUX_IPSR_GPSR(IP1SR4_3_0, AVB0_TD0),
+ PINMUX_IPSR_GPSR(IP1SR4_3_0, AVB0_MII_TD0),
+
+ PINMUX_IPSR_GPSR(IP1SR4_7_4, AVB0_TD1),
+ PINMUX_IPSR_GPSR(IP1SR4_7_4, AVB0_MII_TD1),
+
+ PINMUX_IPSR_GPSR(IP1SR4_11_8, AVB0_TD2),
+ PINMUX_IPSR_GPSR(IP1SR4_11_8, AVB0_MII_TD2),
+
+ PINMUX_IPSR_GPSR(IP1SR4_15_12, AVB0_TD3),
+ PINMUX_IPSR_GPSR(IP1SR4_15_12, AVB0_MII_TD3),
+
+ PINMUX_IPSR_GPSR(IP1SR4_19_16, AVB0_TXCREFCLK),
+
+ PINMUX_IPSR_GPSR(IP1SR4_23_20, AVB0_MDIO),
+
+ PINMUX_IPSR_GPSR(IP1SR4_27_24, AVB0_MDC),
+
+ PINMUX_IPSR_GPSR(IP1SR4_31_28, AVB0_MAGIC),
+
+ /* IP2SR4 */
+ PINMUX_IPSR_GPSR(IP2SR4_7_4, AVB0_LINK),
+ PINMUX_IPSR_GPSR(IP2SR4_7_4, AVB0_MII_TX_ER),
+
+ PINMUX_IPSR_GPSR(IP2SR4_11_8, AVB0_AVTP_MATCH),
+ PINMUX_IPSR_GPSR(IP2SR4_11_8, AVB0_MII_RX_ER),
+ PINMUX_IPSR_GPSR(IP2SR4_11_8, CC5_OSCOUT),
+
+ PINMUX_IPSR_GPSR(IP2SR4_15_12, AVB0_AVTP_CAPTURE),
+ PINMUX_IPSR_GPSR(IP2SR4_15_12, AVB0_MII_CRS),
+
+ PINMUX_IPSR_GPSR(IP2SR4_19_16, AVB0_AVTP_PPS),
+ PINMUX_IPSR_GPSR(IP2SR4_19_16, AVB0_MII_COL),
+
+ /* IP0SR5 */
+ PINMUX_IPSR_GPSR(IP0SR5_3_0, AVB1_RX_CTL),
+ PINMUX_IPSR_GPSR(IP0SR5_3_0, AVB1_MII_RX_DV),
+
+ PINMUX_IPSR_GPSR(IP0SR5_7_4, AVB1_RXC),
+ PINMUX_IPSR_GPSR(IP0SR5_7_4, AVB1_MII_RXC),
+
+ PINMUX_IPSR_GPSR(IP0SR5_11_8, AVB1_RD0),
+ PINMUX_IPSR_GPSR(IP0SR5_11_8, AVB1_MII_RD0),
+
+ PINMUX_IPSR_GPSR(IP0SR5_15_12, AVB1_RD1),
+ PINMUX_IPSR_GPSR(IP0SR5_15_12, AVB1_MII_RD1),
+
+ PINMUX_IPSR_GPSR(IP0SR5_19_16, AVB1_RD2),
+ PINMUX_IPSR_GPSR(IP0SR5_19_16, AVB1_MII_RD2),
+
+ PINMUX_IPSR_GPSR(IP0SR5_23_20, AVB1_RD3),
+ PINMUX_IPSR_GPSR(IP0SR5_23_20, AVB1_MII_RD3),
+
+ PINMUX_IPSR_GPSR(IP0SR5_27_24, AVB1_TX_CTL),
+ PINMUX_IPSR_GPSR(IP0SR5_27_24, AVB1_MII_TX_EN),
+
+ PINMUX_IPSR_GPSR(IP0SR5_31_28, AVB1_TXC),
+ PINMUX_IPSR_GPSR(IP0SR5_31_28, AVB1_MII_TXC),
+
+ /* IP1SR5 */
+ PINMUX_IPSR_GPSR(IP1SR5_3_0, AVB1_TD0),
+ PINMUX_IPSR_GPSR(IP1SR5_3_0, AVB1_MII_TD0),
+
+ PINMUX_IPSR_GPSR(IP1SR5_7_4, AVB1_TD1),
+ PINMUX_IPSR_GPSR(IP1SR5_7_4, AVB1_MII_TD1),
+
+ PINMUX_IPSR_GPSR(IP1SR5_11_8, AVB1_TD2),
+ PINMUX_IPSR_GPSR(IP1SR5_11_8, AVB1_MII_TD2),
+
+ PINMUX_IPSR_GPSR(IP1SR5_15_12, AVB1_TD3),
+ PINMUX_IPSR_GPSR(IP1SR5_15_12, AVB1_MII_TD3),
+
+ PINMUX_IPSR_GPSR(IP1SR5_19_16, AVB1_TXCREFCLK),
+
+ PINMUX_IPSR_GPSR(IP1SR5_23_20, AVB1_MDIO),
+
+ PINMUX_IPSR_GPSR(IP1SR5_27_24, AVB1_MDC),
+
+ PINMUX_IPSR_GPSR(IP1SR5_31_28, AVB1_MAGIC),
+
+ /* IP2SR5 */
+ PINMUX_IPSR_GPSR(IP2SR5_7_4, AVB1_LINK),
+ PINMUX_IPSR_GPSR(IP2SR5_7_4, AVB1_MII_TX_ER),
+
+ PINMUX_IPSR_GPSR(IP2SR5_11_8, AVB1_AVTP_MATCH),
+ PINMUX_IPSR_GPSR(IP2SR5_11_8, AVB1_MII_RX_ER),
+
+ PINMUX_IPSR_GPSR(IP2SR5_15_12, AVB1_AVTP_CAPTURE),
+ PINMUX_IPSR_GPSR(IP2SR5_15_12, AVB1_MII_CRS),
+
+ PINMUX_IPSR_GPSR(IP2SR5_19_16, AVB1_AVTP_PPS),
+ PINMUX_IPSR_GPSR(IP2SR5_19_16, AVB1_MII_COL),
+};
+
+/*
+ * Pins not associated with a GPIO port.
+ */
+enum {
+ GP_ASSIGN_LAST(),
+ NOGP_ALL(),
+};
+
+static const struct sh_pfc_pin pinmux_pins[] = {
+ PINMUX_GPIO_GP_ALL(),
+};
+
+/* - AVB0 ------------------------------------------------ */
+static const unsigned int avb0_link_pins[] = {
+ /* AVB0_LINK */
+ RCAR_GP_PIN(4, 17),
+};
+static const unsigned int avb0_link_mux[] = {
+ AVB0_LINK_MARK,
+};
+static const unsigned int avb0_magic_pins[] = {
+ /* AVB0_MAGIC */
+ RCAR_GP_PIN(4, 15),
+};
+static const unsigned int avb0_magic_mux[] = {
+ AVB0_MAGIC_MARK,
+};
+static const unsigned int avb0_phy_int_pins[] = {
+ /* AVB0_PHY_INT */
+ RCAR_GP_PIN(4, 16),
+};
+static const unsigned int avb0_phy_int_mux[] = {
+ AVB0_PHY_INT_MARK,
+};
+static const unsigned int avb0_mdio_pins[] = {
+ /* AVB0_MDC, AVB0_MDIO */
+ RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 13),
+};
+static const unsigned int avb0_mdio_mux[] = {
+ AVB0_MDC_MARK, AVB0_MDIO_MARK,
+};
+static const unsigned int avb0_rgmii_pins[] = {
+ /*
+ * AVB0_TX_CTL, AVB0_TXC, AVB0_TD0, AVB0_TD1, AVB0_TD2, AVB0_TD3,
+ * AVB0_RX_CTL, AVB0_RXC, AVB0_RD0, AVB0_RD1, AVB0_RD2, AVB0_RD3,
+ */
+ RCAR_GP_PIN(4, 6), RCAR_GP_PIN(4, 7),
+ RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9),
+ RCAR_GP_PIN(4, 10), RCAR_GP_PIN(4, 11),
+ RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
+ RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
+ RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
+};
+static const unsigned int avb0_rgmii_mux[] = {
+ AVB0_TX_CTL_MARK, AVB0_TXC_MARK,
+ AVB0_TD0_MARK, AVB0_TD1_MARK, AVB0_TD2_MARK, AVB0_TD3_MARK,
+ AVB0_RX_CTL_MARK, AVB0_RXC_MARK,
+ AVB0_RD0_MARK, AVB0_RD1_MARK, AVB0_RD2_MARK, AVB0_RD3_MARK,
+};
+static const unsigned int avb0_txcrefclk_pins[] = {
+ /* AVB0_TXCREFCLK */
+ RCAR_GP_PIN(4, 12),
+};
+static const unsigned int avb0_txcrefclk_mux[] = {
+ AVB0_TXCREFCLK_MARK,
+};
+static const unsigned int avb0_avtp_pps_pins[] = {
+ /* AVB0_AVTP_PPS */
+ RCAR_GP_PIN(4, 20),
+};
+static const unsigned int avb0_avtp_pps_mux[] = {
+ AVB0_AVTP_PPS_MARK,
+};
+static const unsigned int avb0_avtp_capture_pins[] = {
+ /* AVB0_AVTP_CAPTURE */
+ RCAR_GP_PIN(4, 19),
+};
+static const unsigned int avb0_avtp_capture_mux[] = {
+ AVB0_AVTP_CAPTURE_MARK,
+};
+static const unsigned int avb0_avtp_match_pins[] = {
+ /* AVB0_AVTP_MATCH */
+ RCAR_GP_PIN(4, 18),
+};
+static const unsigned int avb0_avtp_match_mux[] = {
+ AVB0_AVTP_MATCH_MARK,
+};
+
+/* - AVB1 ------------------------------------------------ */
+static const unsigned int avb1_link_pins[] = {
+ /* AVB1_LINK */
+ RCAR_GP_PIN(5, 17),
+};
+static const unsigned int avb1_link_mux[] = {
+ AVB1_LINK_MARK,
+};
+static const unsigned int avb1_magic_pins[] = {
+ /* AVB1_MAGIC */
+ RCAR_GP_PIN(5, 15),
+};
+static const unsigned int avb1_magic_mux[] = {
+ AVB1_MAGIC_MARK,
+};
+static const unsigned int avb1_phy_int_pins[] = {
+ /* AVB1_PHY_INT */
+ RCAR_GP_PIN(5, 16),
+};
+static const unsigned int avb1_phy_int_mux[] = {
+ AVB1_PHY_INT_MARK,
+};
+static const unsigned int avb1_mdio_pins[] = {
+ /* AVB1_MDC, AVB1_MDIO */
+ RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 13),
+};
+static const unsigned int avb1_mdio_mux[] = {
+ AVB1_MDC_MARK, AVB1_MDIO_MARK,
+};
+static const unsigned int avb1_rgmii_pins[] = {
+ /*
+ * AVB1_TX_CTL, AVB1_TXC, AVB1_TD0, AVB1_TD1, AVB1_TD2, AVB1_TD3,
+ * AVB1_RX_CTL, AVB1_RXC, AVB1_RD0, AVB1_RD1, AVB1_RD2, AVB1_RD3,
+ */
+ RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 7),
+ RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 9),
+ RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 11),
+ RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 1),
+ RCAR_GP_PIN(5, 2), RCAR_GP_PIN(5, 3),
+ RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 5),
+};
+static const unsigned int avb1_rgmii_mux[] = {
+ AVB1_TX_CTL_MARK, AVB1_TXC_MARK,
+ AVB1_TD0_MARK, AVB1_TD1_MARK, AVB1_TD2_MARK, AVB1_TD3_MARK,
+ AVB1_RX_CTL_MARK, AVB1_RXC_MARK,
+ AVB1_RD0_MARK, AVB1_RD1_MARK, AVB1_RD2_MARK, AVB1_RD3_MARK,
+};
+static const unsigned int avb1_txcrefclk_pins[] = {
+ /* AVB1_TXCREFCLK */
+ RCAR_GP_PIN(5, 12),
+};
+static const unsigned int avb1_txcrefclk_mux[] = {
+ AVB1_TXCREFCLK_MARK,
+};
+static const unsigned int avb1_avtp_pps_pins[] = {
+ /* AVB1_AVTP_PPS */
+ RCAR_GP_PIN(5, 20),
+};
+static const unsigned int avb1_avtp_pps_mux[] = {
+ AVB1_AVTP_PPS_MARK,
+};
+static const unsigned int avb1_avtp_capture_pins[] = {
+ /* AVB1_AVTP_CAPTURE */
+ RCAR_GP_PIN(5, 19),
+};
+static const unsigned int avb1_avtp_capture_mux[] = {
+ AVB1_AVTP_CAPTURE_MARK,
+};
+static const unsigned int avb1_avtp_match_pins[] = {
+ /* AVB1_AVTP_MATCH */
+ RCAR_GP_PIN(5, 18),
+};
+static const unsigned int avb1_avtp_match_mux[] = {
+ AVB1_AVTP_MATCH_MARK,
+};
+
+/* - AVB2 ------------------------------------------------ */
+static const unsigned int avb2_link_pins[] = {
+ /* AVB2_LINK */
+ RCAR_GP_PIN(6, 17),
+};
+static const unsigned int avb2_link_mux[] = {
+ AVB2_LINK_MARK,
+};
+static const unsigned int avb2_magic_pins[] = {
+ /* AVB2_MAGIC */
+ RCAR_GP_PIN(6, 15),
+};
+static const unsigned int avb2_magic_mux[] = {
+ AVB2_MAGIC_MARK,
+};
+static const unsigned int avb2_phy_int_pins[] = {
+ /* AVB2_PHY_INT */
+ RCAR_GP_PIN(6, 16),
+};
+static const unsigned int avb2_phy_int_mux[] = {
+ AVB2_PHY_INT_MARK,
+};
+static const unsigned int avb2_mdio_pins[] = {
+ /* AVB2_MDC, AVB2_MDIO */
+ RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 13),
+};
+static const unsigned int avb2_mdio_mux[] = {
+ AVB2_MDC_MARK, AVB2_MDIO_MARK,
+};
+static const unsigned int avb2_rgmii_pins[] = {
+ /*
+ * AVB2_TX_CTL, AVB2_TXC, AVB2_TD0, AVB2_TD1, AVB2_TD2, AVB2_TD3,
+ * AVB2_RX_CTL, AVB2_RXC, AVB2_RD0, AVB2_RD1, AVB2_RD2, AVB2_RD3,
+ */
+ RCAR_GP_PIN(6, 6), RCAR_GP_PIN(6, 7),
+ RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
+ RCAR_GP_PIN(6, 10), RCAR_GP_PIN(6, 11),
+ RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1),
+ RCAR_GP_PIN(6, 2), RCAR_GP_PIN(6, 3),
+ RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 5),
+};
+static const unsigned int avb2_rgmii_mux[] = {
+ AVB2_TX_CTL_MARK, AVB2_TXC_MARK,
+ AVB2_TD0_MARK, AVB2_TD1_MARK, AVB2_TD2_MARK, AVB2_TD3_MARK,
+ AVB2_RX_CTL_MARK, AVB2_RXC_MARK,
+ AVB2_RD0_MARK, AVB2_RD1_MARK, AVB2_RD2_MARK, AVB2_RD3_MARK,
+};
+static const unsigned int avb2_txcrefclk_pins[] = {
+ /* AVB2_TXCREFCLK */
+ RCAR_GP_PIN(6, 12),
+};
+static const unsigned int avb2_txcrefclk_mux[] = {
+ AVB2_TXCREFCLK_MARK,
+};
+static const unsigned int avb2_avtp_pps_pins[] = {
+ /* AVB2_AVTP_PPS */
+ RCAR_GP_PIN(6, 20),
+};
+static const unsigned int avb2_avtp_pps_mux[] = {
+ AVB2_AVTP_PPS_MARK,
+};
+static const unsigned int avb2_avtp_capture_pins[] = {
+ /* AVB2_AVTP_CAPTURE */
+ RCAR_GP_PIN(6, 19),
+};
+static const unsigned int avb2_avtp_capture_mux[] = {
+ AVB2_AVTP_CAPTURE_MARK,
+};
+static const unsigned int avb2_avtp_match_pins[] = {
+ /* AVB2_AVTP_MATCH */
+ RCAR_GP_PIN(6, 18),
+};
+static const unsigned int avb2_avtp_match_mux[] = {
+ AVB2_AVTP_MATCH_MARK,
+};
+
+/* - AVB3 ------------------------------------------------ */
+static const unsigned int avb3_link_pins[] = {
+ /* AVB3_LINK */
+ RCAR_GP_PIN(7, 17),
+};
+static const unsigned int avb3_link_mux[] = {
+ AVB3_LINK_MARK,
+};
+static const unsigned int avb3_magic_pins[] = {
+ /* AVB3_MAGIC */
+ RCAR_GP_PIN(7, 15),
+};
+static const unsigned int avb3_magic_mux[] = {
+ AVB3_MAGIC_MARK,
+};
+static const unsigned int avb3_phy_int_pins[] = {
+ /* AVB3_PHY_INT */
+ RCAR_GP_PIN(7, 16),
+};
+static const unsigned int avb3_phy_int_mux[] = {
+ AVB3_PHY_INT_MARK,
+};
+static const unsigned int avb3_mdio_pins[] = {
+ /* AVB3_MDC, AVB3_MDIO */
+ RCAR_GP_PIN(7, 14), RCAR_GP_PIN(7, 13),
+};
+static const unsigned int avb3_mdio_mux[] = {
+ AVB3_MDC_MARK, AVB3_MDIO_MARK,
+};
+static const unsigned int avb3_rgmii_pins[] = {
+ /*
+ * AVB3_TX_CTL, AVB3_TXC, AVB3_TD0, AVB3_TD1, AVB3_TD2, AVB3_TD3,
+ * AVB3_RX_CTL, AVB3_RXC, AVB3_RD0, AVB3_RD1, AVB3_RD2, AVB3_RD3,
+ */
+ RCAR_GP_PIN(7, 6), RCAR_GP_PIN(7, 7),
+ RCAR_GP_PIN(7, 8), RCAR_GP_PIN(7, 9),
+ RCAR_GP_PIN(7, 10), RCAR_GP_PIN(7, 11),
+ RCAR_GP_PIN(7, 0), RCAR_GP_PIN(7, 1),
+ RCAR_GP_PIN(7, 2), RCAR_GP_PIN(7, 3),
+ RCAR_GP_PIN(7, 4), RCAR_GP_PIN(7, 5),
+};
+static const unsigned int avb3_rgmii_mux[] = {
+ AVB3_TX_CTL_MARK, AVB3_TXC_MARK,
+ AVB3_TD0_MARK, AVB3_TD1_MARK, AVB3_TD2_MARK, AVB3_TD3_MARK,
+ AVB3_RX_CTL_MARK, AVB3_RXC_MARK,
+ AVB3_RD0_MARK, AVB3_RD1_MARK, AVB3_RD2_MARK, AVB3_RD3_MARK,
+};
+static const unsigned int avb3_txcrefclk_pins[] = {
+ /* AVB3_TXCREFCLK */
+ RCAR_GP_PIN(7, 12),
+};
+static const unsigned int avb3_txcrefclk_mux[] = {
+ AVB3_TXCREFCLK_MARK,
+};
+static const unsigned int avb3_avtp_pps_pins[] = {
+ /* AVB3_AVTP_PPS */
+ RCAR_GP_PIN(7, 20),
+};
+static const unsigned int avb3_avtp_pps_mux[] = {
+ AVB3_AVTP_PPS_MARK,
+};
+static const unsigned int avb3_avtp_capture_pins[] = {
+ /* AVB3_AVTP_CAPTURE */
+ RCAR_GP_PIN(7, 19),
+};
+static const unsigned int avb3_avtp_capture_mux[] = {
+ AVB3_AVTP_CAPTURE_MARK,
+};
+static const unsigned int avb3_avtp_match_pins[] = {
+ /* AVB3_AVTP_MATCH */
+ RCAR_GP_PIN(7, 18),
+};
+static const unsigned int avb3_avtp_match_mux[] = {
+ AVB3_AVTP_MATCH_MARK,
+};
+
+/* - AVB4 ------------------------------------------------ */
+static const unsigned int avb4_link_pins[] = {
+ /* AVB4_LINK */
+ RCAR_GP_PIN(8, 17),
+};
+static const unsigned int avb4_link_mux[] = {
+ AVB4_LINK_MARK,
+};
+static const unsigned int avb4_magic_pins[] = {
+ /* AVB4_MAGIC */
+ RCAR_GP_PIN(8, 15),
+};
+static const unsigned int avb4_magic_mux[] = {
+ AVB4_MAGIC_MARK,
+};
+static const unsigned int avb4_phy_int_pins[] = {
+ /* AVB4_PHY_INT */
+ RCAR_GP_PIN(8, 16),
+};
+static const unsigned int avb4_phy_int_mux[] = {
+ AVB4_PHY_INT_MARK,
+};
+static const unsigned int avb4_mdio_pins[] = {
+ /* AVB4_MDC, AVB4_MDIO */
+ RCAR_GP_PIN(8, 14), RCAR_GP_PIN(8, 13),
+};
+static const unsigned int avb4_mdio_mux[] = {
+ AVB4_MDC_MARK, AVB4_MDIO_MARK,
+};
+static const unsigned int avb4_rgmii_pins[] = {
+ /*
+ * AVB4_TX_CTL, AVB4_TXC, AVB4_TD0, AVB4_TD1, AVB4_TD2, AVB4_TD3,
+ * AVB4_RX_CTL, AVB4_RXC, AVB4_RD0, AVB4_RD1, AVB4_RD2, AVB4_RD3,
+ */
+ RCAR_GP_PIN(8, 6), RCAR_GP_PIN(8, 7),
+ RCAR_GP_PIN(8, 8), RCAR_GP_PIN(8, 9),
+ RCAR_GP_PIN(8, 10), RCAR_GP_PIN(8, 11),
+ RCAR_GP_PIN(8, 0), RCAR_GP_PIN(8, 1),
+ RCAR_GP_PIN(8, 2), RCAR_GP_PIN(8, 3),
+ RCAR_GP_PIN(8, 4), RCAR_GP_PIN(8, 5),
+};
+static const unsigned int avb4_rgmii_mux[] = {
+ AVB4_TX_CTL_MARK, AVB4_TXC_MARK,
+ AVB4_TD0_MARK, AVB4_TD1_MARK, AVB4_TD2_MARK, AVB4_TD3_MARK,
+ AVB4_RX_CTL_MARK, AVB4_RXC_MARK,
+ AVB4_RD0_MARK, AVB4_RD1_MARK, AVB4_RD2_MARK, AVB4_RD3_MARK,
+};
+static const unsigned int avb4_txcrefclk_pins[] = {
+ /* AVB4_TXCREFCLK */
+ RCAR_GP_PIN(8, 12),
+};
+static const unsigned int avb4_txcrefclk_mux[] = {
+ AVB4_TXCREFCLK_MARK,
+};
+static const unsigned int avb4_avtp_pps_pins[] = {
+ /* AVB4_AVTP_PPS */
+ RCAR_GP_PIN(8, 20),
+};
+static const unsigned int avb4_avtp_pps_mux[] = {
+ AVB4_AVTP_PPS_MARK,
+};
+static const unsigned int avb4_avtp_capture_pins[] = {
+ /* AVB4_AVTP_CAPTURE */
+ RCAR_GP_PIN(8, 19),
+};
+static const unsigned int avb4_avtp_capture_mux[] = {
+ AVB4_AVTP_CAPTURE_MARK,
+};
+static const unsigned int avb4_avtp_match_pins[] = {
+ /* AVB4_AVTP_MATCH */
+ RCAR_GP_PIN(8, 18),
+};
+static const unsigned int avb4_avtp_match_mux[] = {
+ AVB4_AVTP_MATCH_MARK,
+};
+
+/* - AVB5 ------------------------------------------------ */
+static const unsigned int avb5_link_pins[] = {
+ /* AVB5_LINK */
+ RCAR_GP_PIN(9, 17),
+};
+static const unsigned int avb5_link_mux[] = {
+ AVB5_LINK_MARK,
+};
+static const unsigned int avb5_magic_pins[] = {
+ /* AVB5_MAGIC */
+ RCAR_GP_PIN(9, 15),
+};
+static const unsigned int avb5_magic_mux[] = {
+ AVB5_MAGIC_MARK,
+};
+static const unsigned int avb5_phy_int_pins[] = {
+ /* AVB5_PHY_INT */
+ RCAR_GP_PIN(9, 16),
+};
+static const unsigned int avb5_phy_int_mux[] = {
+ AVB5_PHY_INT_MARK,
+};
+static const unsigned int avb5_mdio_pins[] = {
+ /* AVB5_MDC, AVB5_MDIO */
+ RCAR_GP_PIN(9, 14), RCAR_GP_PIN(9, 13),
+};
+static const unsigned int avb5_mdio_mux[] = {
+ AVB5_MDC_MARK, AVB5_MDIO_MARK,
+};
+static const unsigned int avb5_rgmii_pins[] = {
+ /*
+ * AVB5_TX_CTL, AVB5_TXC, AVB5_TD0, AVB5_TD1, AVB5_TD2, AVB5_TD3,
+ * AVB5_RX_CTL, AVB5_RXC, AVB5_RD0, AVB5_RD1, AVB5_RD2, AVB5_RD3,
+ */
+ RCAR_GP_PIN(9, 6), RCAR_GP_PIN(9, 7),
+ RCAR_GP_PIN(9, 8), RCAR_GP_PIN(9, 9),
+ RCAR_GP_PIN(9, 10), RCAR_GP_PIN(9, 11),
+ RCAR_GP_PIN(9, 0), RCAR_GP_PIN(9, 1),
+ RCAR_GP_PIN(9, 2), RCAR_GP_PIN(9, 3),
+ RCAR_GP_PIN(9, 4), RCAR_GP_PIN(9, 5),
+};
+static const unsigned int avb5_rgmii_mux[] = {
+ AVB5_TX_CTL_MARK, AVB5_TXC_MARK,
+ AVB5_TD0_MARK, AVB5_TD1_MARK, AVB5_TD2_MARK, AVB5_TD3_MARK,
+ AVB5_RX_CTL_MARK, AVB5_RXC_MARK,
+ AVB5_RD0_MARK, AVB5_RD1_MARK, AVB5_RD2_MARK, AVB5_RD3_MARK,
+};
+static const unsigned int avb5_txcrefclk_pins[] = {
+ /* AVB5_TXCREFCLK */
+ RCAR_GP_PIN(9, 12),
+};
+static const unsigned int avb5_txcrefclk_mux[] = {
+ AVB5_TXCREFCLK_MARK,
+};
+static const unsigned int avb5_avtp_pps_pins[] = {
+ /* AVB5_AVTP_PPS */
+ RCAR_GP_PIN(9, 20),
+};
+static const unsigned int avb5_avtp_pps_mux[] = {
+ AVB5_AVTP_PPS_MARK,
+};
+static const unsigned int avb5_avtp_capture_pins[] = {
+ /* AVB5_AVTP_CAPTURE */
+ RCAR_GP_PIN(9, 19),
+};
+static const unsigned int avb5_avtp_capture_mux[] = {
+ AVB5_AVTP_CAPTURE_MARK,
+};
+static const unsigned int avb5_avtp_match_pins[] = {
+ /* AVB5_AVTP_MATCH */
+ RCAR_GP_PIN(9, 18),
+};
+static const unsigned int avb5_avtp_match_mux[] = {
+ AVB5_AVTP_MATCH_MARK,
+};
+
+/* - CANFD0 ----------------------------------------------------------------- */
+static const unsigned int canfd0_data_pins[] = {
+ /* CANFD0_TX, CANFD0_RX */
+ RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 2),
+};
+static const unsigned int canfd0_data_mux[] = {
+ CANFD0_TX_MARK, CANFD0_RX_MARK,
+};
+
+/* - CANFD1 ----------------------------------------------------------------- */
+static const unsigned int canfd1_data_pins[] = {
+ /* CANFD1_TX, CANFD1_RX */
+ RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 4),
+};
+static const unsigned int canfd1_data_mux[] = {
+ CANFD1_TX_MARK, CANFD1_RX_MARK,
+};
+
+/* - CANFD2 ----------------------------------------------------------------- */
+static const unsigned int canfd2_data_pins[] = {
+ /* CANFD2_TX, CANFD2_RX */
+ RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 6),
+};
+static const unsigned int canfd2_data_mux[] = {
+ CANFD2_TX_MARK, CANFD2_RX_MARK,
+};
+
+/* - CANFD3 ----------------------------------------------------------------- */
+static const unsigned int canfd3_data_pins[] = {
+ /* CANFD3_TX, CANFD3_RX */
+ RCAR_GP_PIN(3, 7), RCAR_GP_PIN(3, 8),
+};
+static const unsigned int canfd3_data_mux[] = {
+ CANFD3_TX_MARK, CANFD3_RX_MARK,
+};
+
+/* - CANFD4 ----------------------------------------------------------------- */
+static const unsigned int canfd4_data_pins[] = {
+ /* CANFD4_TX, CANFD4_RX */
+ RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 10),
+};
+static const unsigned int canfd4_data_mux[] = {
+ CANFD4_TX_MARK, CANFD4_RX_MARK,
+};
+
+/* - CANFD5 ----------------------------------------------------------------- */
+static const unsigned int canfd5_data_pins[] = {
+ /* CANFD5_TX, CANFD5_RX */
+ RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 12),
+};
+static const unsigned int canfd5_data_mux[] = {
+ CANFD5_TX_MARK, CANFD5_RX_MARK,
+};
+
+/* - CANFD6 ----------------------------------------------------------------- */
+static const unsigned int canfd6_data_pins[] = {
+ /* CANFD6_TX, CANFD6_RX */
+ RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14),
+};
+static const unsigned int canfd6_data_mux[] = {
+ CANFD6_TX_MARK, CANFD6_RX_MARK,
+};
+
+/* - CANFD7 ----------------------------------------------------------------- */
+static const unsigned int canfd7_data_pins[] = {
+ /* CANFD7_TX, CANFD7_RX */
+ RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16),
+};
+static const unsigned int canfd7_data_mux[] = {
+ CANFD7_TX_MARK, CANFD7_RX_MARK,
+};
+
+/* - CANFD Clock ------------------------------------------------------------ */
+static const unsigned int can_clk_pins[] = {
+ /* CAN_CLK */
+ RCAR_GP_PIN(3, 0),
+};
+static const unsigned int can_clk_mux[] = {
+ CAN_CLK_MARK,
+};
+
+/* - DU --------------------------------------------------------------------- */
+static const unsigned int du_rgb888_pins[] = {
+ /* DU_DR[7:2], DU_DG[7:2], DU_DB[7:2] */
+ RCAR_GP_PIN(1, 11), RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9),
+ RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6),
+ RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 15),
+ RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 12),
+ RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 21),
+ RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
+};
+static const unsigned int du_rgb888_mux[] = {
+ DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK,
+ DU_DR4_MARK, DU_DR3_MARK, DU_DR2_MARK,
+ DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK,
+ DU_DG4_MARK, DU_DG3_MARK, DU_DG2_MARK,
+ DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK,
+ DU_DB4_MARK, DU_DB3_MARK, DU_DB2_MARK,
+};
+static const unsigned int du_clk_out_pins[] = {
+ /* DU_DOTCLKOUT */
+ RCAR_GP_PIN(1, 24),
+};
+static const unsigned int du_clk_out_mux[] = {
+ DU_DOTCLKOUT_MARK,
+};
+static const unsigned int du_sync_pins[] = {
+ /* DU_HSYNC, DU_VSYNC */
+ RCAR_GP_PIN(1, 25), RCAR_GP_PIN(1, 26),
+};
+static const unsigned int du_sync_mux[] = {
+ DU_HSYNC_MARK, DU_VSYNC_MARK,
+};
+static const unsigned int du_oddf_pins[] = {
+ /* DU_EXODDF/DU_ODDF/DISP/CDE */
+ RCAR_GP_PIN(1, 27),
+};
+static const unsigned int du_oddf_mux[] = {
+ DU_ODDF_DISP_CDE_MARK,
+};
+
+/* - HSCIF0 ----------------------------------------------------------------- */
+static const unsigned int hscif0_data_pins[] = {
+ /* HRX0, HTX0 */
+ RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 5),
+};
+static const unsigned int hscif0_data_mux[] = {
+ HRX0_MARK, HTX0_MARK,
+};
+static const unsigned int hscif0_clk_pins[] = {
+ /* HSCK0 */
+ RCAR_GP_PIN(1, 2),
+};
+static const unsigned int hscif0_clk_mux[] = {
+ HSCK0_MARK,
+};
+static const unsigned int hscif0_ctrl_pins[] = {
+ /* HRTS0#, HCTS0# */
+ RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 4),
+};
+static const unsigned int hscif0_ctrl_mux[] = {
+ HRTS0_N_MARK, HCTS0_N_MARK,
+};
+
+/* - HSCIF1 ----------------------------------------------------------------- */
+static const unsigned int hscif1_data_pins[] = {
+ /* HRX1, HTX1 */
+ RCAR_GP_PIN(1, 21), RCAR_GP_PIN(1, 22),
+};
+static const unsigned int hscif1_data_mux[] = {
+ HRX1_MARK, HTX1_MARK,
+};
+static const unsigned int hscif1_clk_pins[] = {
+ /* HSCK1 */
+ RCAR_GP_PIN(1, 18),
+};
+static const unsigned int hscif1_clk_mux[] = {
+ HSCK1_MARK,
+};
+static const unsigned int hscif1_ctrl_pins[] = {
+ /* HRTS1#, HCTS1# */
+ RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 19),
+};
+static const unsigned int hscif1_ctrl_mux[] = {
+ HRTS1_N_MARK, HCTS1_N_MARK,
+};
+
+/* - HSCIF2 ----------------------------------------------------------------- */
+static const unsigned int hscif2_data_pins[] = {
+ /* HRX2, HTX2 */
+ RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
+};
+static const unsigned int hscif2_data_mux[] = {
+ HRX2_MARK, HTX2_MARK,
+};
+static const unsigned int hscif2_clk_pins[] = {
+ /* HSCK2 */
+ RCAR_GP_PIN(2, 5),
+};
+static const unsigned int hscif2_clk_mux[] = {
+ HSCK2_MARK,
+};
+static const unsigned int hscif2_ctrl_pins[] = {
+ /* HRTS2#, HCTS2# */
+ RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 6),
+};
+static const unsigned int hscif2_ctrl_mux[] = {
+ HRTS2_N_MARK, HCTS2_N_MARK,
+};
+
+/* - HSCIF3 ----------------------------------------------------------------- */
+static const unsigned int hscif3_data_pins[] = {
+ /* HRX3, HTX3 */
+ RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 17),
+};
+static const unsigned int hscif3_data_mux[] = {
+ HRX3_MARK, HTX3_MARK,
+};
+static const unsigned int hscif3_clk_pins[] = {
+ /* HSCK3 */
+ RCAR_GP_PIN(1, 14),
+};
+static const unsigned int hscif3_clk_mux[] = {
+ HSCK3_MARK,
+};
+static const unsigned int hscif3_ctrl_pins[] = {
+ /* HRTS3#, HCTS3# */
+ RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 16),
+};
+static const unsigned int hscif3_ctrl_mux[] = {
+ HRTS3_N_MARK, HCTS3_N_MARK,
+};
+
+/* - I2C0 ------------------------------------------------------------------- */
+static const unsigned int i2c0_pins[] = {
+ /* SDA0, SCL0 */
+ RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 2),
+};
+static const unsigned int i2c0_mux[] = {
+ SDA0_MARK, SCL0_MARK,
+};
+
+/* - I2C1 ------------------------------------------------------------------- */
+static const unsigned int i2c1_pins[] = {
+ /* SDA1, SCL1 */
+ RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 4),
+};
+static const unsigned int i2c1_mux[] = {
+ SDA1_MARK, SCL1_MARK,
+};
+
+/* - I2C2 ------------------------------------------------------------------- */
+static const unsigned int i2c2_pins[] = {
+ /* SDA2, SCL2 */
+ RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 6),
+};
+static const unsigned int i2c2_mux[] = {
+ SDA2_MARK, SCL2_MARK,
+};
+
+/* - I2C3 ------------------------------------------------------------------- */
+static const unsigned int i2c3_pins[] = {
+ /* SDA3, SCL3 */
+ RCAR_GP_PIN(2, 9), RCAR_GP_PIN(2, 8),
+};
+static const unsigned int i2c3_mux[] = {
+ SDA3_MARK, SCL3_MARK,
+};
+
+/* - I2C4 ------------------------------------------------------------------- */
+static const unsigned int i2c4_pins[] = {
+ /* SDA4, SCL4 */
+ RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 10),
+};
+static const unsigned int i2c4_mux[] = {
+ SDA4_MARK, SCL4_MARK,
+};
+
+/* - I2C5 ------------------------------------------------------------------- */
+static const unsigned int i2c5_pins[] = {
+ /* SDA5, SCL5 */
+ RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 12),
+};
+static const unsigned int i2c5_mux[] = {
+ SDA5_MARK, SCL5_MARK,
+};
+
+/* - I2C6 ------------------------------------------------------------------- */
+static const unsigned int i2c6_pins[] = {
+ /* SDA6, SCL6 */
+ RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 14),
+};
+static const unsigned int i2c6_mux[] = {
+ SDA6_MARK, SCL6_MARK,
+};
+
+/* - INTC-EX ---------------------------------------------------------------- */
+static const unsigned int intc_ex_irq0_pins[] = {
+ /* IRQ0 */
+ RCAR_GP_PIN(1, 24),
+};
+static const unsigned int intc_ex_irq0_mux[] = {
+ IRQ0_MARK,
+};
+static const unsigned int intc_ex_irq1_pins[] = {
+ /* IRQ1 */
+ RCAR_GP_PIN(1, 25),
+};
+static const unsigned int intc_ex_irq1_mux[] = {
+ IRQ1_MARK,
+};
+static const unsigned int intc_ex_irq2_pins[] = {
+ /* IRQ2 */
+ RCAR_GP_PIN(1, 26),
+};
+static const unsigned int intc_ex_irq2_mux[] = {
+ IRQ2_MARK,
+};
+static const unsigned int intc_ex_irq3_pins[] = {
+ /* IRQ3 */
+ RCAR_GP_PIN(1, 27),
+};
+static const unsigned int intc_ex_irq3_mux[] = {
+ IRQ3_MARK,
+};
+static const unsigned int intc_ex_irq4_pins[] = {
+ /* IRQ4 */
+ RCAR_GP_PIN(2, 14),
+};
+static const unsigned int intc_ex_irq4_mux[] = {
+ IRQ4_MARK,
+};
+static const unsigned int intc_ex_irq5_pins[] = {
+ /* IRQ5 */
+ RCAR_GP_PIN(2, 15),
+};
+static const unsigned int intc_ex_irq5_mux[] = {
+ IRQ5_MARK,
+};
+
+/* - MMC -------------------------------------------------------------------- */
+static const unsigned int mmc_data1_pins[] = {
+ /* MMC_SD_D0 */
+ RCAR_GP_PIN(0, 19),
+};
+static const unsigned int mmc_data1_mux[] = {
+ MMC_SD_D0_MARK,
+};
+static const unsigned int mmc_data4_pins[] = {
+ /* MMC_SD_D[0:3] */
+ RCAR_GP_PIN(0, 19), RCAR_GP_PIN(0, 20),
+ RCAR_GP_PIN(0, 21), RCAR_GP_PIN(0, 22),
+};
+static const unsigned int mmc_data4_mux[] = {
+ MMC_SD_D0_MARK, MMC_SD_D1_MARK,
+ MMC_SD_D2_MARK, MMC_SD_D3_MARK,
+};
+static const unsigned int mmc_data8_pins[] = {
+ /* MMC_SD_D[0:3], MMC_D[4:7] */
+ RCAR_GP_PIN(0, 19), RCAR_GP_PIN(0, 20),
+ RCAR_GP_PIN(0, 21), RCAR_GP_PIN(0, 22),
+ RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25),
+ RCAR_GP_PIN(0, 26), RCAR_GP_PIN(0, 27),
+};
+static const unsigned int mmc_data8_mux[] = {
+ MMC_SD_D0_MARK, MMC_SD_D1_MARK,
+ MMC_SD_D2_MARK, MMC_SD_D3_MARK,
+ MMC_D4_MARK, MMC_D5_MARK,
+ MMC_D6_MARK, MMC_D7_MARK,
+};
+static const unsigned int mmc_ctrl_pins[] = {
+ /* MMC_SD_CLK, MMC_SD_CMD */
+ RCAR_GP_PIN(0, 23), RCAR_GP_PIN(0, 18),
+};
+static const unsigned int mmc_ctrl_mux[] = {
+ MMC_SD_CLK_MARK, MMC_SD_CMD_MARK,
+};
+static const unsigned int mmc_cd_pins[] = {
+ /* SD_CD */
+ RCAR_GP_PIN(0, 16),
+};
+static const unsigned int mmc_cd_mux[] = {
+ SD_CD_MARK,
+};
+static const unsigned int mmc_wp_pins[] = {
+ /* SD_WP */
+ RCAR_GP_PIN(0, 15),
+};
+static const unsigned int mmc_wp_mux[] = {
+ SD_WP_MARK,
+};
+static const unsigned int mmc_ds_pins[] = {
+ /* MMC_DS */
+ RCAR_GP_PIN(0, 17),
+};
+static const unsigned int mmc_ds_mux[] = {
+ MMC_DS_MARK,
+};
+
+/* - MSIOF0 ----------------------------------------------------------------- */
+static const unsigned int msiof0_clk_pins[] = {
+ /* MSIOF0_SCK */
+ RCAR_GP_PIN(1, 8),
+};
+static const unsigned int msiof0_clk_mux[] = {
+ MSIOF0_SCK_MARK,
+};
+static const unsigned int msiof0_sync_pins[] = {
+ /* MSIOF0_SYNC */
+ RCAR_GP_PIN(1, 9),
+};
+static const unsigned int msiof0_sync_mux[] = {
+ MSIOF0_SYNC_MARK,
+};
+static const unsigned int msiof0_ss1_pins[] = {
+ /* MSIOF0_SS1 */
+ RCAR_GP_PIN(1, 10),
+};
+static const unsigned int msiof0_ss1_mux[] = {
+ MSIOF0_SS1_MARK,
+};
+static const unsigned int msiof0_ss2_pins[] = {
+ /* MSIOF0_SS2 */
+ RCAR_GP_PIN(1, 11),
+};
+static const unsigned int msiof0_ss2_mux[] = {
+ MSIOF0_SS2_MARK,
+};
+static const unsigned int msiof0_txd_pins[] = {
+ /* MSIOF0_TXD */
+ RCAR_GP_PIN(1, 7),
+};
+static const unsigned int msiof0_txd_mux[] = {
+ MSIOF0_TXD_MARK,
+};
+static const unsigned int msiof0_rxd_pins[] = {
+ /* MSIOF0_RXD */
+ RCAR_GP_PIN(1, 6),
+};
+static const unsigned int msiof0_rxd_mux[] = {
+ MSIOF0_RXD_MARK,
+};
+
+/* - MSIOF1 ----------------------------------------------------------------- */
+static const unsigned int msiof1_clk_pins[] = {
+ /* MSIOF1_SCK */
+ RCAR_GP_PIN(1, 14),
+};
+static const unsigned int msiof1_clk_mux[] = {
+ MSIOF1_SCK_MARK,
+};
+static const unsigned int msiof1_sync_pins[] = {
+ /* MSIOF1_SYNC */
+ RCAR_GP_PIN(1, 15),
+};
+static const unsigned int msiof1_sync_mux[] = {
+ MSIOF1_SYNC_MARK,
+};
+static const unsigned int msiof1_ss1_pins[] = {
+ /* MSIOF1_SS1 */
+ RCAR_GP_PIN(1, 16),
+};
+static const unsigned int msiof1_ss1_mux[] = {
+ MSIOF1_SS1_MARK,
+};
+static const unsigned int msiof1_ss2_pins[] = {
+ /* MSIOF1_SS2 */
+ RCAR_GP_PIN(1, 17),
+};
+static const unsigned int msiof1_ss2_mux[] = {
+ MSIOF1_SS2_MARK,
+};
+static const unsigned int msiof1_txd_pins[] = {
+ /* MSIOF1_TXD */
+ RCAR_GP_PIN(1, 13),
+};
+static const unsigned int msiof1_txd_mux[] = {
+ MSIOF1_TXD_MARK,
+};
+static const unsigned int msiof1_rxd_pins[] = {
+ /* MSIOF1_RXD */
+ RCAR_GP_PIN(1, 12),
+};
+static const unsigned int msiof1_rxd_mux[] = {
+ MSIOF1_RXD_MARK,
+};
+
+/* - MSIOF2 ----------------------------------------------------------------- */
+static const unsigned int msiof2_clk_pins[] = {
+ /* MSIOF2_SCK */
+ RCAR_GP_PIN(1, 20),
+};
+static const unsigned int msiof2_clk_mux[] = {
+ MSIOF2_SCK_MARK,
+};
+static const unsigned int msiof2_sync_pins[] = {
+ /* MSIOF2_SYNC */
+ RCAR_GP_PIN(1, 21),
+};
+static const unsigned int msiof2_sync_mux[] = {
+ MSIOF2_SYNC_MARK,
+};
+static const unsigned int msiof2_ss1_pins[] = {
+ /* MSIOF2_SS1 */
+ RCAR_GP_PIN(1, 22),
+};
+static const unsigned int msiof2_ss1_mux[] = {
+ MSIOF2_SS1_MARK,
+};
+static const unsigned int msiof2_ss2_pins[] = {
+ /* MSIOF2_SS2 */
+ RCAR_GP_PIN(1, 23),
+};
+static const unsigned int msiof2_ss2_mux[] = {
+ MSIOF2_SS2_MARK,
+};
+static const unsigned int msiof2_txd_pins[] = {
+ /* MSIOF2_TXD */
+ RCAR_GP_PIN(1, 19),
+};
+static const unsigned int msiof2_txd_mux[] = {
+ MSIOF2_TXD_MARK,
+};
+static const unsigned int msiof2_rxd_pins[] = {
+ /* MSIOF2_RXD */
+ RCAR_GP_PIN(1, 18),
+};
+static const unsigned int msiof2_rxd_mux[] = {
+ MSIOF2_RXD_MARK,
+};
+
+/* - MSIOF3 ----------------------------------------------------------------- */
+static const unsigned int msiof3_clk_pins[] = {
+ /* MSIOF3_SCK */
+ RCAR_GP_PIN(2, 20),
+};
+static const unsigned int msiof3_clk_mux[] = {
+ MSIOF3_SCK_MARK,
+};
+static const unsigned int msiof3_sync_pins[] = {
+ /* MSIOF3_SYNC */
+ RCAR_GP_PIN(2, 21),
+};
+static const unsigned int msiof3_sync_mux[] = {
+ MSIOF3_SYNC_MARK,
+};
+static const unsigned int msiof3_ss1_pins[] = {
+ /* MSIOF3_SS1 */
+ RCAR_GP_PIN(2, 16),
+};
+static const unsigned int msiof3_ss1_mux[] = {
+ MSIOF3_SS1_MARK,
+};
+static const unsigned int msiof3_ss2_pins[] = {
+ /* MSIOF3_SS2 */
+ RCAR_GP_PIN(2, 17),
+};
+static const unsigned int msiof3_ss2_mux[] = {
+ MSIOF3_SS2_MARK,
+};
+static const unsigned int msiof3_txd_pins[] = {
+ /* MSIOF3_TXD */
+ RCAR_GP_PIN(2, 19),
+};
+static const unsigned int msiof3_txd_mux[] = {
+ MSIOF3_TXD_MARK,
+};
+static const unsigned int msiof3_rxd_pins[] = {
+ /* MSIOF3_RXD */
+ RCAR_GP_PIN(2, 18),
+};
+static const unsigned int msiof3_rxd_mux[] = {
+ MSIOF3_RXD_MARK,
+};
+
+/* - MSIOF4 ----------------------------------------------------------------- */
+static const unsigned int msiof4_clk_pins[] = {
+ /* MSIOF4_SCK */
+ RCAR_GP_PIN(2, 6),
+};
+static const unsigned int msiof4_clk_mux[] = {
+ MSIOF4_SCK_MARK,
+};
+static const unsigned int msiof4_sync_pins[] = {
+ /* MSIOF4_SYNC */
+ RCAR_GP_PIN(2, 7),
+};
+static const unsigned int msiof4_sync_mux[] = {
+ MSIOF4_SYNC_MARK,
+};
+static const unsigned int msiof4_ss1_pins[] = {
+ /* MSIOF4_SS1 */
+ RCAR_GP_PIN(2, 8),
+};
+static const unsigned int msiof4_ss1_mux[] = {
+ MSIOF4_SS1_MARK,
+};
+static const unsigned int msiof4_ss2_pins[] = {
+ /* MSIOF4_SS2 */
+ RCAR_GP_PIN(2, 9),
+};
+static const unsigned int msiof4_ss2_mux[] = {
+ MSIOF4_SS2_MARK,
+};
+static const unsigned int msiof4_txd_pins[] = {
+ /* MSIOF4_TXD */
+ RCAR_GP_PIN(2, 5),
+};
+static const unsigned int msiof4_txd_mux[] = {
+ MSIOF4_TXD_MARK,
+};
+static const unsigned int msiof4_rxd_pins[] = {
+ /* MSIOF4_RXD */
+ RCAR_GP_PIN(2, 4),
+};
+static const unsigned int msiof4_rxd_mux[] = {
+ MSIOF4_RXD_MARK,
+};
+
+/* - MSIOF5 ----------------------------------------------------------------- */
+static const unsigned int msiof5_clk_pins[] = {
+ /* MSIOF5_SCK */
+ RCAR_GP_PIN(2, 12),
+};
+static const unsigned int msiof5_clk_mux[] = {
+ MSIOF5_SCK_MARK,
+};
+static const unsigned int msiof5_sync_pins[] = {
+ /* MSIOF5_SYNC */
+ RCAR_GP_PIN(2, 13),
+};
+static const unsigned int msiof5_sync_mux[] = {
+ MSIOF5_SYNC_MARK,
+};
+static const unsigned int msiof5_ss1_pins[] = {
+ /* MSIOF5_SS1 */
+ RCAR_GP_PIN(2, 14),
+};
+static const unsigned int msiof5_ss1_mux[] = {
+ MSIOF5_SS1_MARK,
+};
+static const unsigned int msiof5_ss2_pins[] = {
+ /* MSIOF5_SS2 */
+ RCAR_GP_PIN(2, 15),
+};
+static const unsigned int msiof5_ss2_mux[] = {
+ MSIOF5_SS2_MARK,
+};
+static const unsigned int msiof5_txd_pins[] = {
+ /* MSIOF5_TXD */
+ RCAR_GP_PIN(2, 11),
+};
+static const unsigned int msiof5_txd_mux[] = {
+ MSIOF5_TXD_MARK,
+};
+static const unsigned int msiof5_rxd_pins[] = {
+ /* MSIOF5_RXD */
+ RCAR_GP_PIN(2, 10),
+};
+static const unsigned int msiof5_rxd_mux[] = {
+ MSIOF5_RXD_MARK,
+};
+
+/* - PWM0 ------------------------------------------------------------------- */
+static const unsigned int pwm0_pins[] = {
+ /* PWM0 */
+ RCAR_GP_PIN(3, 5),
+};
+static const unsigned int pwm0_mux[] = {
+ PWM0_MARK,
+};
+
+/* - PWM1 ------------------------------------------------------------------- */
+static const unsigned int pwm1_pins[] = {
+ /* PWM1 */
+ RCAR_GP_PIN(3, 6),
+};
+static const unsigned int pwm1_mux[] = {
+ PWM1_MARK,
+};
+
+/* - PWM2 ------------------------------------------------------------------- */
+static const unsigned int pwm2_pins[] = {
+ /* PWM2 */
+ RCAR_GP_PIN(3, 7),
+};
+static const unsigned int pwm2_mux[] = {
+ PWM2_MARK,
+};
+
+/* - PWM3 ------------------------------------------------------------------- */
+static const unsigned int pwm3_pins[] = {
+ /* PWM3 */
+ RCAR_GP_PIN(3, 8),
+};
+static const unsigned int pwm3_mux[] = {
+ PWM3_MARK,
+};
+
+/* - PWM4 ------------------------------------------------------------------- */
+static const unsigned int pwm4_pins[] = {
+ /* PWM4 */
+ RCAR_GP_PIN(3, 9),
+};
+static const unsigned int pwm4_mux[] = {
+ PWM4_MARK,
+};
+
+/* - QSPI0 ------------------------------------------------------------------ */
+static const unsigned int qspi0_ctrl_pins[] = {
+ /* SPCLK, SSL */
+ RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 5),
+};
+static const unsigned int qspi0_ctrl_mux[] = {
+ QSPI0_SPCLK_MARK, QSPI0_SSL_MARK,
+};
+static const unsigned int qspi0_data2_pins[] = {
+ /* MOSI_IO0, MISO_IO1 */
+ RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 2),
+};
+static const unsigned int qspi0_data2_mux[] = {
+ QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
+};
+static const unsigned int qspi0_data4_pins[] = {
+ /* MOSI_IO0, MISO_IO1, IO2, IO3 */
+ RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 2),
+ RCAR_GP_PIN(0, 3), RCAR_GP_PIN(0, 4),
+};
+static const unsigned int qspi0_data4_mux[] = {
+ QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
+ QSPI0_IO2_MARK, QSPI0_IO3_MARK
+};
+
+/* - QSPI1 ------------------------------------------------------------------ */
+static const unsigned int qspi1_ctrl_pins[] = {
+ /* SPCLK, SSL */
+ RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 11),
+};
+static const unsigned int qspi1_ctrl_mux[] = {
+ QSPI1_SPCLK_MARK, QSPI1_SSL_MARK,
+};
+static const unsigned int qspi1_data2_pins[] = {
+ /* MOSI_IO0, MISO_IO1 */
+ RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 8),
+};
+static const unsigned int qspi1_data2_mux[] = {
+ QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
+};
+static const unsigned int qspi1_data4_pins[] = {
+ /* MOSI_IO0, MISO_IO1, IO2, IO3 */
+ RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 8),
+ RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10),
+};
+static const unsigned int qspi1_data4_mux[] = {
+ QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
+ QSPI1_IO2_MARK, QSPI1_IO3_MARK
+};
+
+/* - SCIF0 ------------------------------------------------------------------ */
+static const unsigned int scif0_data_pins[] = {
+ /* RX0, TX0 */
+ RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 5),
+};
+static const unsigned int scif0_data_mux[] = {
+ RX0_MARK, TX0_MARK,
+};
+static const unsigned int scif0_clk_pins[] = {
+ /* SCK0 */
+ RCAR_GP_PIN(1, 2),
+};
+static const unsigned int scif0_clk_mux[] = {
+ SCK0_MARK,
+};
+static const unsigned int scif0_ctrl_pins[] = {
+ /* RTS0#, CTS0# */
+ RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 4),
+};
+static const unsigned int scif0_ctrl_mux[] = {
+ RTS0_N_MARK, CTS0_N_MARK,
+};
+
+/* - SCIF1 ------------------------------------------------------------------ */
+static const unsigned int scif1_data_a_pins[] = {
+ /* RX, TX */
+ RCAR_GP_PIN(1, 21), RCAR_GP_PIN(1, 22),
+};
+static const unsigned int scif1_data_a_mux[] = {
+ RX1_A_MARK, TX1_A_MARK,
+};
+static const unsigned int scif1_data_b_pins[] = {
+ /* RX, TX */
+ RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 1),
+};
+static const unsigned int scif1_data_b_mux[] = {
+ RX1_B_MARK, TX1_B_MARK,
+};
+static const unsigned int scif1_clk_pins[] = {
+ /* SCK1 */
+ RCAR_GP_PIN(1, 18),
+};
+static const unsigned int scif1_clk_mux[] = {
+ SCK1_MARK,
+};
+static const unsigned int scif1_ctrl_pins[] = {
+ /* RTS1#, CTS1# */
+ RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 19),
+};
+static const unsigned int scif1_ctrl_mux[] = {
+ RTS1_N_MARK, CTS1_N_MARK,
+};
+
+/* - SCIF3 ------------------------------------------------------------------ */
+static const unsigned int scif3_data_pins[] = {
+ /* RX3, TX3 */
+ RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 17),
+};
+static const unsigned int scif3_data_mux[] = {
+ RX3_MARK, TX3_MARK,
+};
+static const unsigned int scif3_clk_pins[] = {
+ /* SCK3 */
+ RCAR_GP_PIN(1, 13),
+};
+static const unsigned int scif3_clk_mux[] = {
+ SCK3_MARK,
+};
+static const unsigned int scif3_ctrl_pins[] = {
+ /* RTS3#, CTS3# */
+ RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14),
+};
+static const unsigned int scif3_ctrl_mux[] = {
+ RTS3_N_MARK, CTS3_N_MARK,
+};
+
+/* - SCIF4 ------------------------------------------------------------------ */
+static const unsigned int scif4_data_pins[] = {
+ /* RX4, TX4 */
+ RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
+};
+static const unsigned int scif4_data_mux[] = {
+ RX4_MARK, TX4_MARK,
+};
+static const unsigned int scif4_clk_pins[] = {
+ /* SCK4 */
+ RCAR_GP_PIN(2, 5),
+};
+static const unsigned int scif4_clk_mux[] = {
+ SCK4_MARK,
+};
+static const unsigned int scif4_ctrl_pins[] = {
+ /* RTS4#, CTS4# */
+ RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 6),
+};
+static const unsigned int scif4_ctrl_mux[] = {
+ RTS4_N_MARK, CTS4_N_MARK,
+};
+
+/* - SCIF Clock ------------------------------------------------------------- */
+static const unsigned int scif_clk_pins[] = {
+ /* SCIF_CLK */
+ RCAR_GP_PIN(1, 0),
+};
+static const unsigned int scif_clk_mux[] = {
+ SCIF_CLK_MARK,
+};
+
+/* - TMU -------------------------------------------------------------------- */
+static const unsigned int tmu_tclk1_a_pins[] = {
+ /* TCLK1 */
+ RCAR_GP_PIN(2, 23),
+};
+static const unsigned int tmu_tclk1_a_mux[] = {
+ TCLK1_A_MARK,
+};
+static const unsigned int tmu_tclk1_b_pins[] = {
+ /* TCLK1 */
+ RCAR_GP_PIN(1, 23),
+};
+static const unsigned int tmu_tclk1_b_mux[] = {
+ TCLK1_B_MARK,
+};
+
+static const unsigned int tmu_tclk2_a_pins[] = {
+ /* TCLK2 */
+ RCAR_GP_PIN(2, 24),
+};
+static const unsigned int tmu_tclk2_a_mux[] = {
+ TCLK2_A_MARK,
+};
+static const unsigned int tmu_tclk2_b_pins[] = {
+ /* TCLK2 */
+ RCAR_GP_PIN(2, 10),
+};
+static const unsigned int tmu_tclk2_b_mux[] = {
+ TCLK2_B_MARK,
+};
+
+static const unsigned int tmu_tclk3_pins[] = {
+ /* TCLK3 */
+ RCAR_GP_PIN(2, 11),
+};
+static const unsigned int tmu_tclk3_mux[] = {
+ TCLK3_MARK,
+};
+
+static const unsigned int tmu_tclk4_pins[] = {
+ /* TCLK4 */
+ RCAR_GP_PIN(2, 12),
+};
+static const unsigned int tmu_tclk4_mux[] = {
+ TCLK4_MARK,
+};
+
+/* - TPU ------------------------------------------------------------------- */
+static const unsigned int tpu_to0_pins[] = {
+ /* TPU0TO0 */
+ RCAR_GP_PIN(2, 21),
+};
+static const unsigned int tpu_to0_mux[] = {
+ TPU0TO0_MARK,
+};
+static const unsigned int tpu_to1_pins[] = {
+ /* TPU0TO1 */
+ RCAR_GP_PIN(2, 22),
+};
+static const unsigned int tpu_to1_mux[] = {
+ TPU0TO1_MARK,
+};
+static const unsigned int tpu_to2_pins[] = {
+ /* TPU0TO2 */
+ RCAR_GP_PIN(3, 5),
+};
+static const unsigned int tpu_to2_mux[] = {
+ TPU0TO2_MARK,
+};
+static const unsigned int tpu_to3_pins[] = {
+ /* TPU0TO3 */
+ RCAR_GP_PIN(3, 6),
+};
+static const unsigned int tpu_to3_mux[] = {
+ TPU0TO3_MARK,
+};
+
+static const struct sh_pfc_pin_group pinmux_groups[] = {
+ SH_PFC_PIN_GROUP(avb0_link),
+ SH_PFC_PIN_GROUP(avb0_magic),
+ SH_PFC_PIN_GROUP(avb0_phy_int),
+ SH_PFC_PIN_GROUP(avb0_mdio),
+ SH_PFC_PIN_GROUP(avb0_rgmii),
+ SH_PFC_PIN_GROUP(avb0_txcrefclk),
+ SH_PFC_PIN_GROUP(avb0_avtp_pps),
+ SH_PFC_PIN_GROUP(avb0_avtp_capture),
+ SH_PFC_PIN_GROUP(avb0_avtp_match),
+
+ SH_PFC_PIN_GROUP(avb1_link),
+ SH_PFC_PIN_GROUP(avb1_magic),
+ SH_PFC_PIN_GROUP(avb1_phy_int),
+ SH_PFC_PIN_GROUP(avb1_mdio),
+ SH_PFC_PIN_GROUP(avb1_rgmii),
+ SH_PFC_PIN_GROUP(avb1_txcrefclk),
+ SH_PFC_PIN_GROUP(avb1_avtp_pps),
+ SH_PFC_PIN_GROUP(avb1_avtp_capture),
+ SH_PFC_PIN_GROUP(avb1_avtp_match),
+
+ SH_PFC_PIN_GROUP(avb2_link),
+ SH_PFC_PIN_GROUP(avb2_magic),
+ SH_PFC_PIN_GROUP(avb2_phy_int),
+ SH_PFC_PIN_GROUP(avb2_mdio),
+ SH_PFC_PIN_GROUP(avb2_rgmii),
+ SH_PFC_PIN_GROUP(avb2_txcrefclk),
+ SH_PFC_PIN_GROUP(avb2_avtp_pps),
+ SH_PFC_PIN_GROUP(avb2_avtp_capture),
+ SH_PFC_PIN_GROUP(avb2_avtp_match),
+
+ SH_PFC_PIN_GROUP(avb3_link),
+ SH_PFC_PIN_GROUP(avb3_magic),
+ SH_PFC_PIN_GROUP(avb3_phy_int),
+ SH_PFC_PIN_GROUP(avb3_mdio),
+ SH_PFC_PIN_GROUP(avb3_rgmii),
+ SH_PFC_PIN_GROUP(avb3_txcrefclk),
+ SH_PFC_PIN_GROUP(avb3_avtp_pps),
+ SH_PFC_PIN_GROUP(avb3_avtp_capture),
+ SH_PFC_PIN_GROUP(avb3_avtp_match),
+
+ SH_PFC_PIN_GROUP(avb4_link),
+ SH_PFC_PIN_GROUP(avb4_magic),
+ SH_PFC_PIN_GROUP(avb4_phy_int),
+ SH_PFC_PIN_GROUP(avb4_mdio),
+ SH_PFC_PIN_GROUP(avb4_rgmii),
+ SH_PFC_PIN_GROUP(avb4_txcrefclk),
+ SH_PFC_PIN_GROUP(avb4_avtp_pps),
+ SH_PFC_PIN_GROUP(avb4_avtp_capture),
+ SH_PFC_PIN_GROUP(avb4_avtp_match),
+
+ SH_PFC_PIN_GROUP(avb5_link),
+ SH_PFC_PIN_GROUP(avb5_magic),
+ SH_PFC_PIN_GROUP(avb5_phy_int),
+ SH_PFC_PIN_GROUP(avb5_mdio),
+ SH_PFC_PIN_GROUP(avb5_rgmii),
+ SH_PFC_PIN_GROUP(avb5_txcrefclk),
+ SH_PFC_PIN_GROUP(avb5_avtp_pps),
+ SH_PFC_PIN_GROUP(avb5_avtp_capture),
+ SH_PFC_PIN_GROUP(avb5_avtp_match),
+
+ SH_PFC_PIN_GROUP(canfd0_data),
+ SH_PFC_PIN_GROUP(canfd1_data),
+ SH_PFC_PIN_GROUP(canfd2_data),
+ SH_PFC_PIN_GROUP(canfd3_data),
+ SH_PFC_PIN_GROUP(canfd4_data),
+ SH_PFC_PIN_GROUP(canfd5_data),
+ SH_PFC_PIN_GROUP(canfd6_data),
+ SH_PFC_PIN_GROUP(canfd7_data),
+ SH_PFC_PIN_GROUP(can_clk),
+
+ SH_PFC_PIN_GROUP(du_rgb888),
+ SH_PFC_PIN_GROUP(du_clk_out),
+ SH_PFC_PIN_GROUP(du_sync),
+ SH_PFC_PIN_GROUP(du_oddf),
+
+ SH_PFC_PIN_GROUP(hscif0_data),
+ SH_PFC_PIN_GROUP(hscif0_clk),
+ SH_PFC_PIN_GROUP(hscif0_ctrl),
+ SH_PFC_PIN_GROUP(hscif1_data),
+ SH_PFC_PIN_GROUP(hscif1_clk),
+ SH_PFC_PIN_GROUP(hscif1_ctrl),
+ SH_PFC_PIN_GROUP(hscif2_data),
+ SH_PFC_PIN_GROUP(hscif2_clk),
+ SH_PFC_PIN_GROUP(hscif2_ctrl),
+ SH_PFC_PIN_GROUP(hscif3_data),
+ SH_PFC_PIN_GROUP(hscif3_clk),
+ SH_PFC_PIN_GROUP(hscif3_ctrl),
+
+ SH_PFC_PIN_GROUP(i2c0),
+ SH_PFC_PIN_GROUP(i2c1),
+ SH_PFC_PIN_GROUP(i2c2),
+ SH_PFC_PIN_GROUP(i2c3),
+ SH_PFC_PIN_GROUP(i2c4),
+ SH_PFC_PIN_GROUP(i2c5),
+ SH_PFC_PIN_GROUP(i2c6),
+
+ SH_PFC_PIN_GROUP(intc_ex_irq0),
+ SH_PFC_PIN_GROUP(intc_ex_irq1),
+ SH_PFC_PIN_GROUP(intc_ex_irq2),
+ SH_PFC_PIN_GROUP(intc_ex_irq3),
+ SH_PFC_PIN_GROUP(intc_ex_irq4),
+ SH_PFC_PIN_GROUP(intc_ex_irq5),
+
+ SH_PFC_PIN_GROUP(mmc_data1),
+ SH_PFC_PIN_GROUP(mmc_data4),
+ SH_PFC_PIN_GROUP(mmc_data8),
+ SH_PFC_PIN_GROUP(mmc_ctrl),
+ SH_PFC_PIN_GROUP(mmc_cd),
+ SH_PFC_PIN_GROUP(mmc_wp),
+ SH_PFC_PIN_GROUP(mmc_ds),
+
+ SH_PFC_PIN_GROUP(msiof0_clk),
+ SH_PFC_PIN_GROUP(msiof0_sync),
+ SH_PFC_PIN_GROUP(msiof0_ss1),
+ SH_PFC_PIN_GROUP(msiof0_ss2),
+ SH_PFC_PIN_GROUP(msiof0_txd),
+ SH_PFC_PIN_GROUP(msiof0_rxd),
+ SH_PFC_PIN_GROUP(msiof1_clk),
+ SH_PFC_PIN_GROUP(msiof1_sync),
+ SH_PFC_PIN_GROUP(msiof1_ss1),
+ SH_PFC_PIN_GROUP(msiof1_ss2),
+ SH_PFC_PIN_GROUP(msiof1_txd),
+ SH_PFC_PIN_GROUP(msiof1_rxd),
+ SH_PFC_PIN_GROUP(msiof2_clk),
+ SH_PFC_PIN_GROUP(msiof2_sync),
+ SH_PFC_PIN_GROUP(msiof2_ss1),
+ SH_PFC_PIN_GROUP(msiof2_ss2),
+ SH_PFC_PIN_GROUP(msiof2_txd),
+ SH_PFC_PIN_GROUP(msiof2_rxd),
+ SH_PFC_PIN_GROUP(msiof3_clk),
+ SH_PFC_PIN_GROUP(msiof3_sync),
+ SH_PFC_PIN_GROUP(msiof3_ss1),
+ SH_PFC_PIN_GROUP(msiof3_ss2),
+ SH_PFC_PIN_GROUP(msiof3_txd),
+ SH_PFC_PIN_GROUP(msiof3_rxd),
+ SH_PFC_PIN_GROUP(msiof4_clk),
+ SH_PFC_PIN_GROUP(msiof4_sync),
+ SH_PFC_PIN_GROUP(msiof4_ss1),
+ SH_PFC_PIN_GROUP(msiof4_ss2),
+ SH_PFC_PIN_GROUP(msiof4_txd),
+ SH_PFC_PIN_GROUP(msiof4_rxd),
+ SH_PFC_PIN_GROUP(msiof5_clk),
+ SH_PFC_PIN_GROUP(msiof5_sync),
+ SH_PFC_PIN_GROUP(msiof5_ss1),
+ SH_PFC_PIN_GROUP(msiof5_ss2),
+ SH_PFC_PIN_GROUP(msiof5_txd),
+ SH_PFC_PIN_GROUP(msiof5_rxd),
+
+ SH_PFC_PIN_GROUP(pwm0),
+ SH_PFC_PIN_GROUP(pwm1),
+ SH_PFC_PIN_GROUP(pwm2),
+ SH_PFC_PIN_GROUP(pwm3),
+ SH_PFC_PIN_GROUP(pwm4),
+
+ SH_PFC_PIN_GROUP(qspi0_ctrl),
+ SH_PFC_PIN_GROUP(qspi0_data2),
+ SH_PFC_PIN_GROUP(qspi0_data4),
+ SH_PFC_PIN_GROUP(qspi1_ctrl),
+ SH_PFC_PIN_GROUP(qspi1_data2),
+ SH_PFC_PIN_GROUP(qspi1_data4),
+
+ SH_PFC_PIN_GROUP(scif0_data),
+ SH_PFC_PIN_GROUP(scif0_clk),
+ SH_PFC_PIN_GROUP(scif0_ctrl),
+ SH_PFC_PIN_GROUP(scif1_data_a),
+ SH_PFC_PIN_GROUP(scif1_data_b),
+ SH_PFC_PIN_GROUP(scif1_clk),
+ SH_PFC_PIN_GROUP(scif1_ctrl),
+ SH_PFC_PIN_GROUP(scif3_data),
+ SH_PFC_PIN_GROUP(scif3_clk),
+ SH_PFC_PIN_GROUP(scif3_ctrl),
+ SH_PFC_PIN_GROUP(scif4_data),
+ SH_PFC_PIN_GROUP(scif4_clk),
+ SH_PFC_PIN_GROUP(scif4_ctrl),
+ SH_PFC_PIN_GROUP(scif_clk),
+
+ SH_PFC_PIN_GROUP(tmu_tclk1_a),
+ SH_PFC_PIN_GROUP(tmu_tclk1_b),
+ SH_PFC_PIN_GROUP(tmu_tclk2_a),
+ SH_PFC_PIN_GROUP(tmu_tclk2_b),
+ SH_PFC_PIN_GROUP(tmu_tclk3),
+ SH_PFC_PIN_GROUP(tmu_tclk4),
+
+ SH_PFC_PIN_GROUP(tpu_to0),
+ SH_PFC_PIN_GROUP(tpu_to1),
+ SH_PFC_PIN_GROUP(tpu_to2),
+ SH_PFC_PIN_GROUP(tpu_to3),
+};
+
+static const char * const avb0_groups[] = {
+ "avb0_link",
+ "avb0_magic",
+ "avb0_phy_int",
+ "avb0_mdio",
+ "avb0_rgmii",
+ "avb0_txcrefclk",
+ "avb0_avtp_pps",
+ "avb0_avtp_capture",
+ "avb0_avtp_match",
+};
+
+static const char * const avb1_groups[] = {
+ "avb1_link",
+ "avb1_magic",
+ "avb1_phy_int",
+ "avb1_mdio",
+ "avb1_rgmii",
+ "avb1_txcrefclk",
+ "avb1_avtp_pps",
+ "avb1_avtp_capture",
+ "avb1_avtp_match",
+};
+
+static const char * const avb2_groups[] = {
+ "avb2_link",
+ "avb2_magic",
+ "avb2_phy_int",
+ "avb2_mdio",
+ "avb2_rgmii",
+ "avb2_txcrefclk",
+ "avb2_avtp_pps",
+ "avb2_avtp_capture",
+ "avb2_avtp_match",
+};
+
+static const char * const avb3_groups[] = {
+ "avb3_link",
+ "avb3_magic",
+ "avb3_phy_int",
+ "avb3_mdio",
+ "avb3_rgmii",
+ "avb3_txcrefclk",
+ "avb3_avtp_pps",
+ "avb3_avtp_capture",
+ "avb3_avtp_match",
+};
+
+static const char * const avb4_groups[] = {
+ "avb4_link",
+ "avb4_magic",
+ "avb4_phy_int",
+ "avb4_mdio",
+ "avb4_rgmii",
+ "avb4_txcrefclk",
+ "avb4_avtp_pps",
+ "avb4_avtp_capture",
+ "avb4_avtp_match",
+};
+
+static const char * const avb5_groups[] = {
+ "avb5_link",
+ "avb5_magic",
+ "avb5_phy_int",
+ "avb5_mdio",
+ "avb5_rgmii",
+ "avb5_txcrefclk",
+ "avb5_avtp_pps",
+ "avb5_avtp_capture",
+ "avb5_avtp_match",
+};
+
+static const char * const canfd0_groups[] = {
+ "canfd0_data",
+};
+
+static const char * const canfd1_groups[] = {
+ "canfd1_data",
+};
+
+static const char * const canfd2_groups[] = {
+ "canfd2_data",
+};
+
+static const char * const canfd3_groups[] = {
+ "canfd3_data",
+};
+
+static const char * const canfd4_groups[] = {
+ "canfd4_data",
+};
+
+static const char * const canfd5_groups[] = {
+ "canfd5_data",
+};
+
+static const char * const canfd6_groups[] = {
+ "canfd6_data",
+};
+
+static const char * const canfd7_groups[] = {
+ "canfd7_data",
+};
+
+static const char * const can_clk_groups[] = {
+ "can_clk",
+};
+
+static const char * const du_groups[] = {
+ "du_rgb888",
+ "du_clk_out",
+ "du_sync",
+ "du_oddf",
+};
+
+static const char * const hscif0_groups[] = {
+ "hscif0_data",
+ "hscif0_clk",
+ "hscif0_ctrl",
+};
+
+static const char * const hscif1_groups[] = {
+ "hscif1_data",
+ "hscif1_clk",
+ "hscif1_ctrl",
+};
+
+static const char * const hscif2_groups[] = {
+ "hscif2_data",
+ "hscif2_clk",
+ "hscif2_ctrl",
+};
+
+static const char * const hscif3_groups[] = {
+ "hscif3_data",
+ "hscif3_clk",
+ "hscif3_ctrl",
+};
+
+static const char * const i2c0_groups[] = {
+ "i2c0",
+};
+
+static const char * const i2c1_groups[] = {
+ "i2c1",
+};
+
+static const char * const i2c2_groups[] = {
+ "i2c2",
+};
+
+static const char * const i2c3_groups[] = {
+ "i2c3",
+};
+
+static const char * const i2c4_groups[] = {
+ "i2c4",
+};
+
+static const char * const i2c5_groups[] = {
+ "i2c5",
+};
+
+static const char * const i2c6_groups[] = {
+ "i2c6",
+};
+
+static const char * const intc_ex_groups[] = {
+ "intc_ex_irq0",
+ "intc_ex_irq1",
+ "intc_ex_irq2",
+ "intc_ex_irq3",
+ "intc_ex_irq4",
+ "intc_ex_irq5",
+};
+
+static const char * const mmc_groups[] = {
+ "mmc_data1",
+ "mmc_data4",
+ "mmc_data8",
+ "mmc_ctrl",
+ "mmc_cd",
+ "mmc_wp",
+ "mmc_ds",
+};
+
+static const char * const msiof0_groups[] = {
+ "msiof0_clk",
+ "msiof0_sync",
+ "msiof0_ss1",
+ "msiof0_ss2",
+ "msiof0_txd",
+ "msiof0_rxd",
+};
+
+static const char * const msiof1_groups[] = {
+ "msiof1_clk",
+ "msiof1_sync",
+ "msiof1_ss1",
+ "msiof1_ss2",
+ "msiof1_txd",
+ "msiof1_rxd",
+};
+
+static const char * const msiof2_groups[] = {
+ "msiof2_clk",
+ "msiof2_sync",
+ "msiof2_ss1",
+ "msiof2_ss2",
+ "msiof2_txd",
+ "msiof2_rxd",
+};
+
+static const char * const msiof3_groups[] = {
+ "msiof3_clk",
+ "msiof3_sync",
+ "msiof3_ss1",
+ "msiof3_ss2",
+ "msiof3_txd",
+ "msiof3_rxd",
+};
+
+static const char * const msiof4_groups[] = {
+ "msiof4_clk",
+ "msiof4_sync",
+ "msiof4_ss1",
+ "msiof4_ss2",
+ "msiof4_txd",
+ "msiof4_rxd",
+};
+
+static const char * const msiof5_groups[] = {
+ "msiof5_clk",
+ "msiof5_sync",
+ "msiof5_ss1",
+ "msiof5_ss2",
+ "msiof5_txd",
+ "msiof5_rxd",
+};
+
+static const char * const pwm0_groups[] = {
+ "pwm0",
+};
+
+static const char * const pwm1_groups[] = {
+ "pwm1",
+};
+
+static const char * const pwm2_groups[] = {
+ "pwm2",
+};
+
+static const char * const pwm3_groups[] = {
+ "pwm3",
+};
+
+static const char * const pwm4_groups[] = {
+ "pwm4",
+};
+
+static const char * const qspi0_groups[] = {
+ "qspi0_ctrl",
+ "qspi0_data2",
+ "qspi0_data4",
+};
+
+static const char * const qspi1_groups[] = {
+ "qspi1_ctrl",
+ "qspi1_data2",
+ "qspi1_data4",
+};
+
+static const char * const scif0_groups[] = {
+ "scif0_data",
+ "scif0_clk",
+ "scif0_ctrl",
+};
+
+static const char * const scif1_groups[] = {
+ "scif1_data_a",
+ "scif1_data_b",
+ "scif1_clk",
+ "scif1_ctrl",
+};
+
+static const char * const scif3_groups[] = {
+ "scif3_data",
+ "scif3_clk",
+ "scif3_ctrl",
+};
+
+static const char * const scif4_groups[] = {
+ "scif4_data",
+ "scif4_clk",
+ "scif4_ctrl",
+};
+
+static const char * const scif_clk_groups[] = {
+ "scif_clk",
+};
+
+static const char * const tmu_groups[] = {
+ "tmu_tclk1_a",
+ "tmu_tclk1_b",
+ "tmu_tclk2_a",
+ "tmu_tclk2_b",
+ "tmu_tclk3",
+ "tmu_tclk4",
+};
+
+static const char * const tpu_groups[] = {
+ "tpu_to0",
+ "tpu_to1",
+ "tpu_to2",
+ "tpu_to3",
+};
+
+static const struct sh_pfc_function pinmux_functions[] = {
+ SH_PFC_FUNCTION(avb0),
+ SH_PFC_FUNCTION(avb1),
+ SH_PFC_FUNCTION(avb2),
+ SH_PFC_FUNCTION(avb3),
+ SH_PFC_FUNCTION(avb4),
+ SH_PFC_FUNCTION(avb5),
+
+ SH_PFC_FUNCTION(canfd0),
+ SH_PFC_FUNCTION(canfd1),
+ SH_PFC_FUNCTION(canfd2),
+ SH_PFC_FUNCTION(canfd3),
+ SH_PFC_FUNCTION(canfd4),
+ SH_PFC_FUNCTION(canfd5),
+ SH_PFC_FUNCTION(canfd6),
+ SH_PFC_FUNCTION(canfd7),
+ SH_PFC_FUNCTION(can_clk),
+
+ SH_PFC_FUNCTION(du),
+
+ SH_PFC_FUNCTION(hscif0),
+ SH_PFC_FUNCTION(hscif1),
+ SH_PFC_FUNCTION(hscif2),
+ SH_PFC_FUNCTION(hscif3),
+
+ SH_PFC_FUNCTION(i2c0),
+ SH_PFC_FUNCTION(i2c1),
+ SH_PFC_FUNCTION(i2c2),
+ SH_PFC_FUNCTION(i2c3),
+ SH_PFC_FUNCTION(i2c4),
+ SH_PFC_FUNCTION(i2c5),
+ SH_PFC_FUNCTION(i2c6),
+
+ SH_PFC_FUNCTION(intc_ex),
+
+ SH_PFC_FUNCTION(mmc),
+
+ SH_PFC_FUNCTION(msiof0),
+ SH_PFC_FUNCTION(msiof1),
+ SH_PFC_FUNCTION(msiof2),
+ SH_PFC_FUNCTION(msiof3),
+ SH_PFC_FUNCTION(msiof4),
+ SH_PFC_FUNCTION(msiof5),
+
+ SH_PFC_FUNCTION(pwm0),
+ SH_PFC_FUNCTION(pwm1),
+ SH_PFC_FUNCTION(pwm2),
+ SH_PFC_FUNCTION(pwm3),
+ SH_PFC_FUNCTION(pwm4),
+
+ SH_PFC_FUNCTION(qspi0),
+ SH_PFC_FUNCTION(qspi1),
+
+ SH_PFC_FUNCTION(scif0),
+ SH_PFC_FUNCTION(scif1),
+ SH_PFC_FUNCTION(scif3),
+ SH_PFC_FUNCTION(scif4),
+ SH_PFC_FUNCTION(scif_clk),
+
+ SH_PFC_FUNCTION(tmu),
+
+ SH_PFC_FUNCTION(tpu),
+};
+
+static const struct pinmux_cfg_reg pinmux_config_regs[] = {
+#define F_(x, y) FN_##y
+#define FM(x) FN_##x
+ { PINMUX_CFG_REG("GPSR0", 0xe6058040, 32, 1, GROUP(
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ GP_0_27_FN, GPSR0_27,
+ GP_0_26_FN, GPSR0_26,
+ GP_0_25_FN, GPSR0_25,
+ GP_0_24_FN, GPSR0_24,
+ GP_0_23_FN, GPSR0_23,
+ GP_0_22_FN, GPSR0_22,
+ GP_0_21_FN, GPSR0_21,
+ GP_0_20_FN, GPSR0_20,
+ GP_0_19_FN, GPSR0_19,
+ GP_0_18_FN, GPSR0_18,
+ GP_0_17_FN, GPSR0_17,
+ GP_0_16_FN, GPSR0_16,
+ GP_0_15_FN, GPSR0_15,
+ GP_0_14_FN, GPSR0_14,
+ GP_0_13_FN, GPSR0_13,
+ GP_0_12_FN, GPSR0_12,
+ GP_0_11_FN, GPSR0_11,
+ GP_0_10_FN, GPSR0_10,
+ GP_0_9_FN, GPSR0_9,
+ GP_0_8_FN, GPSR0_8,
+ GP_0_7_FN, GPSR0_7,
+ GP_0_6_FN, GPSR0_6,
+ GP_0_5_FN, GPSR0_5,
+ GP_0_4_FN, GPSR0_4,
+ GP_0_3_FN, GPSR0_3,
+ GP_0_2_FN, GPSR0_2,
+ GP_0_1_FN, GPSR0_1,
+ GP_0_0_FN, GPSR0_0, ))
+ },
+ { PINMUX_CFG_REG("GPSR1", 0xe6050040, 32, 1, GROUP(
+ 0, 0,
+ GP_1_30_FN, GPSR1_30,
+ GP_1_29_FN, GPSR1_29,
+ GP_1_28_FN, GPSR1_28,
+ GP_1_27_FN, GPSR1_27,
+ GP_1_26_FN, GPSR1_26,
+ GP_1_25_FN, GPSR1_25,
+ GP_1_24_FN, GPSR1_24,
+ GP_1_23_FN, GPSR1_23,
+ GP_1_22_FN, GPSR1_22,
+ GP_1_21_FN, GPSR1_21,
+ GP_1_20_FN, GPSR1_20,
+ GP_1_19_FN, GPSR1_19,
+ GP_1_18_FN, GPSR1_18,
+ GP_1_17_FN, GPSR1_17,
+ GP_1_16_FN, GPSR1_16,
+ GP_1_15_FN, GPSR1_15,
+ GP_1_14_FN, GPSR1_14,
+ GP_1_13_FN, GPSR1_13,
+ GP_1_12_FN, GPSR1_12,
+ GP_1_11_FN, GPSR1_11,
+ GP_1_10_FN, GPSR1_10,
+ GP_1_9_FN, GPSR1_9,
+ GP_1_8_FN, GPSR1_8,
+ GP_1_7_FN, GPSR1_7,
+ GP_1_6_FN, GPSR1_6,
+ GP_1_5_FN, GPSR1_5,
+ GP_1_4_FN, GPSR1_4,
+ GP_1_3_FN, GPSR1_3,
+ GP_1_2_FN, GPSR1_2,
+ GP_1_1_FN, GPSR1_1,
+ GP_1_0_FN, GPSR1_0, ))
+ },
+ { PINMUX_CFG_REG("GPSR2", 0xe6050840, 32, 1, GROUP(
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ GP_2_24_FN, GPSR2_24,
+ GP_2_23_FN, GPSR2_23,
+ GP_2_22_FN, GPSR2_22,
+ GP_2_21_FN, GPSR2_21,
+ GP_2_20_FN, GPSR2_20,
+ GP_2_19_FN, GPSR2_19,
+ GP_2_18_FN, GPSR2_18,
+ GP_2_17_FN, GPSR2_17,
+ GP_2_16_FN, GPSR2_16,
+ GP_2_15_FN, GPSR2_15,
+ GP_2_14_FN, GPSR2_14,
+ GP_2_13_FN, GPSR2_13,
+ GP_2_12_FN, GPSR2_12,
+ GP_2_11_FN, GPSR2_11,
+ GP_2_10_FN, GPSR2_10,
+ GP_2_9_FN, GPSR2_9,
+ GP_2_8_FN, GPSR2_8,
+ GP_2_7_FN, GPSR2_7,
+ GP_2_6_FN, GPSR2_6,
+ GP_2_5_FN, GPSR2_5,
+ GP_2_4_FN, GPSR2_4,
+ GP_2_3_FN, GPSR2_3,
+ GP_2_2_FN, GPSR2_2,
+ GP_2_1_FN, GPSR2_1,
+ GP_2_0_FN, GPSR2_0, ))
+ },
+ { PINMUX_CFG_REG("GPSR3", 0xe6058840, 32, 1, GROUP(
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ GP_3_16_FN, GPSR3_16,
+ GP_3_15_FN, GPSR3_15,
+ GP_3_14_FN, GPSR3_14,
+ GP_3_13_FN, GPSR3_13,
+ GP_3_12_FN, GPSR3_12,
+ GP_3_11_FN, GPSR3_11,
+ GP_3_10_FN, GPSR3_10,
+ GP_3_9_FN, GPSR3_9,
+ GP_3_8_FN, GPSR3_8,
+ GP_3_7_FN, GPSR3_7,
+ GP_3_6_FN, GPSR3_6,
+ GP_3_5_FN, GPSR3_5,
+ GP_3_4_FN, GPSR3_4,
+ GP_3_3_FN, GPSR3_3,
+ GP_3_2_FN, GPSR3_2,
+ GP_3_1_FN, GPSR3_1,
+ GP_3_0_FN, GPSR3_0, ))
+ },
+ { PINMUX_CFG_REG("GPSR4", 0xe6060040, 32, 1, GROUP(
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ GP_4_26_FN, GPSR4_26,
+ GP_4_25_FN, GPSR4_25,
+ GP_4_24_FN, GPSR4_24,
+ GP_4_23_FN, GPSR4_23,
+ GP_4_22_FN, GPSR4_22,
+ GP_4_21_FN, GPSR4_21,
+ GP_4_20_FN, GPSR4_20,
+ GP_4_19_FN, GPSR4_19,
+ GP_4_18_FN, GPSR4_18,
+ GP_4_17_FN, GPSR4_17,
+ GP_4_16_FN, GPSR4_16,
+ GP_4_15_FN, GPSR4_15,
+ GP_4_14_FN, GPSR4_14,
+ GP_4_13_FN, GPSR4_13,
+ GP_4_12_FN, GPSR4_12,
+ GP_4_11_FN, GPSR4_11,
+ GP_4_10_FN, GPSR4_10,
+ GP_4_9_FN, GPSR4_9,
+ GP_4_8_FN, GPSR4_8,
+ GP_4_7_FN, GPSR4_7,
+ GP_4_6_FN, GPSR4_6,
+ GP_4_5_FN, GPSR4_5,
+ GP_4_4_FN, GPSR4_4,
+ GP_4_3_FN, GPSR4_3,
+ GP_4_2_FN, GPSR4_2,
+ GP_4_1_FN, GPSR4_1,
+ GP_4_0_FN, GPSR4_0, ))
+ },
+ { PINMUX_CFG_REG("GPSR5", 0xe6060840, 32, 1, GROUP(
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ GP_5_20_FN, GPSR5_20,
+ GP_5_19_FN, GPSR5_19,
+ GP_5_18_FN, GPSR5_18,
+ GP_5_17_FN, GPSR5_17,
+ GP_5_16_FN, GPSR5_16,
+ GP_5_15_FN, GPSR5_15,
+ GP_5_14_FN, GPSR5_14,
+ GP_5_13_FN, GPSR5_13,
+ GP_5_12_FN, GPSR5_12,
+ GP_5_11_FN, GPSR5_11,
+ GP_5_10_FN, GPSR5_10,
+ GP_5_9_FN, GPSR5_9,
+ GP_5_8_FN, GPSR5_8,
+ GP_5_7_FN, GPSR5_7,
+ GP_5_6_FN, GPSR5_6,
+ GP_5_5_FN, GPSR5_5,
+ GP_5_4_FN, GPSR5_4,
+ GP_5_3_FN, GPSR5_3,
+ GP_5_2_FN, GPSR5_2,
+ GP_5_1_FN, GPSR5_1,
+ GP_5_0_FN, GPSR5_0, ))
+ },
+ { PINMUX_CFG_REG("GPSR6", 0xe6068040, 32, 1, GROUP(
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ GP_6_20_FN, GPSR6_20,
+ GP_6_19_FN, GPSR6_19,
+ GP_6_18_FN, GPSR6_18,
+ GP_6_17_FN, GPSR6_17,
+ GP_6_16_FN, GPSR6_16,
+ GP_6_15_FN, GPSR6_15,
+ GP_6_14_FN, GPSR6_14,
+ GP_6_13_FN, GPSR6_13,
+ GP_6_12_FN, GPSR6_12,
+ GP_6_11_FN, GPSR6_11,
+ GP_6_10_FN, GPSR6_10,
+ GP_6_9_FN, GPSR6_9,
+ GP_6_8_FN, GPSR6_8,
+ GP_6_7_FN, GPSR6_7,
+ GP_6_6_FN, GPSR6_6,
+ GP_6_5_FN, GPSR6_5,
+ GP_6_4_FN, GPSR6_4,
+ GP_6_3_FN, GPSR6_3,
+ GP_6_2_FN, GPSR6_2,
+ GP_6_1_FN, GPSR6_1,
+ GP_6_0_FN, GPSR6_0, ))
+ },
+ { PINMUX_CFG_REG("GPSR7", 0xe6068840, 32, 1, GROUP(
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ GP_7_20_FN, GPSR7_20,
+ GP_7_19_FN, GPSR7_19,
+ GP_7_18_FN, GPSR7_18,
+ GP_7_17_FN, GPSR7_17,
+ GP_7_16_FN, GPSR7_16,
+ GP_7_15_FN, GPSR7_15,
+ GP_7_14_FN, GPSR7_14,
+ GP_7_13_FN, GPSR7_13,
+ GP_7_12_FN, GPSR7_12,
+ GP_7_11_FN, GPSR7_11,
+ GP_7_10_FN, GPSR7_10,
+ GP_7_9_FN, GPSR7_9,
+ GP_7_8_FN, GPSR7_8,
+ GP_7_7_FN, GPSR7_7,
+ GP_7_6_FN, GPSR7_6,
+ GP_7_5_FN, GPSR7_5,
+ GP_7_4_FN, GPSR7_4,
+ GP_7_3_FN, GPSR7_3,
+ GP_7_2_FN, GPSR7_2,
+ GP_7_1_FN, GPSR7_1,
+ GP_7_0_FN, GPSR7_0, ))
+ },
+ { PINMUX_CFG_REG("GPSR8", 0xe6069040, 32, 1, GROUP(
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ GP_8_20_FN, GPSR8_20,
+ GP_8_19_FN, GPSR8_19,
+ GP_8_18_FN, GPSR8_18,
+ GP_8_17_FN, GPSR8_17,
+ GP_8_16_FN, GPSR8_16,
+ GP_8_15_FN, GPSR8_15,
+ GP_8_14_FN, GPSR8_14,
+ GP_8_13_FN, GPSR8_13,
+ GP_8_12_FN, GPSR8_12,
+ GP_8_11_FN, GPSR8_11,
+ GP_8_10_FN, GPSR8_10,
+ GP_8_9_FN, GPSR8_9,
+ GP_8_8_FN, GPSR8_8,
+ GP_8_7_FN, GPSR8_7,
+ GP_8_6_FN, GPSR8_6,
+ GP_8_5_FN, GPSR8_5,
+ GP_8_4_FN, GPSR8_4,
+ GP_8_3_FN, GPSR8_3,
+ GP_8_2_FN, GPSR8_2,
+ GP_8_1_FN, GPSR8_1,
+ GP_8_0_FN, GPSR8_0, ))
+ },
+ { PINMUX_CFG_REG("GPSR9", 0xe6069840, 32, 1, GROUP(
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ GP_9_20_FN, GPSR9_20,
+ GP_9_19_FN, GPSR9_19,
+ GP_9_18_FN, GPSR9_18,
+ GP_9_17_FN, GPSR9_17,
+ GP_9_16_FN, GPSR9_16,
+ GP_9_15_FN, GPSR9_15,
+ GP_9_14_FN, GPSR9_14,
+ GP_9_13_FN, GPSR9_13,
+ GP_9_12_FN, GPSR9_12,
+ GP_9_11_FN, GPSR9_11,
+ GP_9_10_FN, GPSR9_10,
+ GP_9_9_FN, GPSR9_9,
+ GP_9_8_FN, GPSR9_8,
+ GP_9_7_FN, GPSR9_7,
+ GP_9_6_FN, GPSR9_6,
+ GP_9_5_FN, GPSR9_5,
+ GP_9_4_FN, GPSR9_4,
+ GP_9_3_FN, GPSR9_3,
+ GP_9_2_FN, GPSR9_2,
+ GP_9_1_FN, GPSR9_1,
+ GP_9_0_FN, GPSR9_0, ))
+ },
+#undef F_
+#undef FM
+
+#define F_(x, y) x,
+#define FM(x) FN_##x,
+ { PINMUX_CFG_REG("IP0SR1", 0xe6050060, 32, 4, GROUP(
+ IP0SR1_31_28
+ IP0SR1_27_24
+ IP0SR1_23_20
+ IP0SR1_19_16
+ IP0SR1_15_12
+ IP0SR1_11_8
+ IP0SR1_7_4
+ IP0SR1_3_0))
+ },
+ { PINMUX_CFG_REG("IP1SR1", 0xe6050064, 32, 4, GROUP(
+ IP1SR1_31_28
+ IP1SR1_27_24
+ IP1SR1_23_20
+ IP1SR1_19_16
+ IP1SR1_15_12
+ IP1SR1_11_8
+ IP1SR1_7_4
+ IP1SR1_3_0))
+ },
+ { PINMUX_CFG_REG("IP2SR1", 0xe6050068, 32, 4, GROUP(
+ IP2SR1_31_28
+ IP2SR1_27_24
+ IP2SR1_23_20
+ IP2SR1_19_16
+ IP2SR1_15_12
+ IP2SR1_11_8
+ IP2SR1_7_4
+ IP2SR1_3_0))
+ },
+ { PINMUX_CFG_REG("IP3SR1", 0xe605006c, 32, 4, GROUP(
+ IP3SR1_31_28
+ IP3SR1_27_24
+ IP3SR1_23_20
+ IP3SR1_19_16
+ IP3SR1_15_12
+ IP3SR1_11_8
+ IP3SR1_7_4
+ IP3SR1_3_0))
+ },
+ { PINMUX_CFG_REG("IP0SR2", 0xe6050860, 32, 4, GROUP(
+ IP0SR2_31_28
+ IP0SR2_27_24
+ IP0SR2_23_20
+ IP0SR2_19_16
+ IP0SR2_15_12
+ IP0SR2_11_8
+ IP0SR2_7_4
+ IP0SR2_3_0))
+ },
+ { PINMUX_CFG_REG("IP1SR2", 0xe6050864, 32, 4, GROUP(
+ IP1SR2_31_28
+ IP1SR2_27_24
+ IP1SR2_23_20
+ IP1SR2_19_16
+ IP1SR2_15_12
+ IP1SR2_11_8
+ IP1SR2_7_4
+ IP1SR2_3_0))
+ },
+ { PINMUX_CFG_REG("IP2SR2", 0xe6050868, 32, 4, GROUP(
+ IP2SR2_31_28
+ IP2SR2_27_24
+ IP2SR2_23_20
+ IP2SR2_19_16
+ IP2SR2_15_12
+ IP2SR2_11_8
+ IP2SR2_7_4
+ IP2SR2_3_0))
+ },
+ { PINMUX_CFG_REG("IP0SR3", 0xe6058860, 32, 4, GROUP(
+ IP0SR3_31_28
+ IP0SR3_27_24
+ IP0SR3_23_20
+ IP0SR3_19_16
+ IP0SR3_15_12
+ IP0SR3_11_8
+ IP0SR3_7_4
+ IP0SR3_3_0))
+ },
+ { PINMUX_CFG_REG("IP1SR3", 0xe6058864, 32, 4, GROUP(
+ IP1SR3_31_28
+ IP1SR3_27_24
+ IP1SR3_23_20
+ IP1SR3_19_16
+ IP1SR3_15_12
+ IP1SR3_11_8
+ IP1SR3_7_4
+ IP1SR3_3_0))
+ },
+ { PINMUX_CFG_REG("IP0SR4", 0xe6060060, 32, 4, GROUP(
+ IP0SR4_31_28
+ IP0SR4_27_24
+ IP0SR4_23_20
+ IP0SR4_19_16
+ IP0SR4_15_12
+ IP0SR4_11_8
+ IP0SR4_7_4
+ IP0SR4_3_0))
+ },
+ { PINMUX_CFG_REG("IP1SR4", 0xe6060064, 32, 4, GROUP(
+ IP1SR4_31_28
+ IP1SR4_27_24
+ IP1SR4_23_20
+ IP1SR4_19_16
+ IP1SR4_15_12
+ IP1SR4_11_8
+ IP1SR4_7_4
+ IP1SR4_3_0))
+ },
+ { PINMUX_CFG_REG("IP2SR4", 0xe6060068, 32, 4, GROUP(
+ IP2SR4_31_28
+ IP2SR4_27_24
+ IP2SR4_23_20
+ IP2SR4_19_16
+ IP2SR4_15_12
+ IP2SR4_11_8
+ IP2SR4_7_4
+ IP2SR4_3_0))
+ },
+ { PINMUX_CFG_REG("IP0SR5", 0xe6060860, 32, 4, GROUP(
+ IP0SR5_31_28
+ IP0SR5_27_24
+ IP0SR5_23_20
+ IP0SR5_19_16
+ IP0SR5_15_12
+ IP0SR5_11_8
+ IP0SR5_7_4
+ IP0SR5_3_0))
+ },
+ { PINMUX_CFG_REG("IP1SR5", 0xe6060864, 32, 4, GROUP(
+ IP1SR5_31_28
+ IP1SR5_27_24
+ IP1SR5_23_20
+ IP1SR5_19_16
+ IP1SR5_15_12
+ IP1SR5_11_8
+ IP1SR5_7_4
+ IP1SR5_3_0))
+ },
+ { PINMUX_CFG_REG("IP2SR5", 0xe6060868, 32, 4, GROUP(
+ IP2SR5_31_28
+ IP2SR5_27_24
+ IP2SR5_23_20
+ IP2SR5_19_16
+ IP2SR5_15_12
+ IP2SR5_11_8
+ IP2SR5_7_4
+ IP2SR5_3_0))
+ },
+#undef F_
+#undef FM
+
+#define F_(x, y) x,
+#define FM(x) FN_##x,
+ { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xe6050900, 32,
+ GROUP(4, 4, 4, 4, 2, 2, 2, 2, 2, 2, 2, 1, 1),
+ GROUP(
+ /* RESERVED 31, 30, 29, 28 */
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ /* RESERVED 27, 26, 25, 24 */
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ /* RESERVED 23, 22, 21, 20 */
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ /* RESERVED 19, 18, 17, 16 */
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ MOD_SEL2_14_15
+ MOD_SEL2_12_13
+ MOD_SEL2_10_11
+ MOD_SEL2_8_9
+ MOD_SEL2_6_7
+ MOD_SEL2_4_5
+ MOD_SEL2_2_3
+ 0, 0,
+ 0, 0, ))
+ },
+ { },
+};
+
+static const struct pinmux_drive_reg pinmux_drive_regs[] = {
+ { PINMUX_DRIVE_REG("DRV0CTRL0", 0xe6058080) {
+ { RCAR_GP_PIN(0, 7), 28, 2 }, /* QSPI1_MOSI_IO0 */
+ { RCAR_GP_PIN(0, 6), 24, 2 }, /* QSPI1_SPCLK */
+ { RCAR_GP_PIN(0, 5), 20, 2 }, /* QSPI0_SSL */
+ { RCAR_GP_PIN(0, 4), 16, 2 }, /* QSPI0_IO3 */
+ { RCAR_GP_PIN(0, 3), 12, 2 }, /* QSPI0_IO2 */
+ { RCAR_GP_PIN(0, 2), 8, 2 }, /* QSPI0_MISO_IO1 */
+ { RCAR_GP_PIN(0, 1), 4, 2 }, /* QSPI0_MOSI_IO0 */
+ { RCAR_GP_PIN(0, 0), 0, 2 }, /* QSPI0_SPCLK */
+ } },
+ { PINMUX_DRIVE_REG("DRV1CTRL0", 0xe6058084) {
+ { RCAR_GP_PIN(0, 15), 28, 3 }, /* SD_WP */
+ { RCAR_GP_PIN(0, 14), 24, 2 }, /* RPC_INT_N */
+ { RCAR_GP_PIN(0, 13), 20, 2 }, /* RPC_WP_N */
+ { RCAR_GP_PIN(0, 12), 16, 2 }, /* RPC_RESET_N */
+ { RCAR_GP_PIN(0, 11), 12, 2 }, /* QSPI1_SSL */
+ { RCAR_GP_PIN(0, 10), 8, 2 }, /* QSPI1_IO3 */
+ { RCAR_GP_PIN(0, 9), 4, 2 }, /* QSPI1_IO2 */
+ { RCAR_GP_PIN(0, 8), 0, 2 }, /* QSPI1_MISO_IO1 */
+ } },
+ { PINMUX_DRIVE_REG("DRV2CTRL0", 0xe6058088) {
+ { RCAR_GP_PIN(0, 23), 28, 3 }, /* MMC_SD_CLK */
+ { RCAR_GP_PIN(0, 22), 24, 3 }, /* MMC_SD_D3 */
+ { RCAR_GP_PIN(0, 21), 20, 3 }, /* MMC_SD_D2 */
+ { RCAR_GP_PIN(0, 20), 16, 3 }, /* MMC_SD_D1 */
+ { RCAR_GP_PIN(0, 19), 12, 3 }, /* MMC_SD_D0 */
+ { RCAR_GP_PIN(0, 18), 8, 3 }, /* MMC_SD_CMD */
+ { RCAR_GP_PIN(0, 17), 4, 3 }, /* MMC_DS */
+ { RCAR_GP_PIN(0, 16), 0, 3 }, /* SD_CD */
+ } },
+ { PINMUX_DRIVE_REG("DRV3CTRL0", 0xe605808c) {
+ { RCAR_GP_PIN(0, 27), 12, 3 }, /* MMC_D7 */
+ { RCAR_GP_PIN(0, 26), 8, 3 }, /* MMC_D6 */
+ { RCAR_GP_PIN(0, 25), 4, 3 }, /* MMC_D5 */
+ { RCAR_GP_PIN(0, 24), 0, 3 }, /* MMC_D4 */
+ } },
+ { PINMUX_DRIVE_REG("DRV0CTRL1", 0xe6050080) {
+ { RCAR_GP_PIN(1, 7), 28, 3 }, /* MSIOF0_TXD */
+ { RCAR_GP_PIN(1, 6), 24, 3 }, /* MSIOF0_RXD */
+ { RCAR_GP_PIN(1, 5), 20, 3 }, /* HTX0 */
+ { RCAR_GP_PIN(1, 4), 16, 3 }, /* HCTS0_N */
+ { RCAR_GP_PIN(1, 3), 12, 3 }, /* HRTS0_N */
+ { RCAR_GP_PIN(1, 2), 8, 3 }, /* HSCK0 */
+ { RCAR_GP_PIN(1, 1), 4, 3 }, /* HRX0 */
+ { RCAR_GP_PIN(1, 0), 0, 3 }, /* SCIF_CLK */
+ } },
+ { PINMUX_DRIVE_REG("DRV1CTRL1", 0xe6050084) {
+ { RCAR_GP_PIN(1, 15), 28, 3 }, /* MSIOF1_SYNC */
+ { RCAR_GP_PIN(1, 14), 24, 3 }, /* MSIOF1_SCK */
+ { RCAR_GP_PIN(1, 13), 20, 3 }, /* MSIOF1_TXD */
+ { RCAR_GP_PIN(1, 12), 16, 3 }, /* MSIOF1_RXD */
+ { RCAR_GP_PIN(1, 11), 12, 3 }, /* MSIOF0_SS2 */
+ { RCAR_GP_PIN(1, 10), 8, 3 }, /* MSIOF0_SS1 */
+ { RCAR_GP_PIN(1, 9), 4, 3 }, /* MSIOF0_SYNC */
+ { RCAR_GP_PIN(1, 8), 0, 3 }, /* MSIOF0_SCK */
+ } },
+ { PINMUX_DRIVE_REG("DRV2CTRL1", 0xe6050088) {
+ { RCAR_GP_PIN(1, 23), 28, 3 }, /* MSIOF2_SS2 */
+ { RCAR_GP_PIN(1, 22), 24, 3 }, /* MSIOF2_SS1 */
+ { RCAR_GP_PIN(1, 21), 20, 3 }, /* MSIOF2_SYNC */
+ { RCAR_GP_PIN(1, 20), 16, 3 }, /* MSIOF2_SCK */
+ { RCAR_GP_PIN(1, 19), 12, 3 }, /* MSIOF2_TXD */
+ { RCAR_GP_PIN(1, 18), 8, 3 }, /* MSIOF2_RXD */
+ { RCAR_GP_PIN(1, 17), 4, 3 }, /* MSIOF1_SS2 */
+ { RCAR_GP_PIN(1, 16), 0, 3 }, /* MSIOF1_SS1 */
+ } },
+ { PINMUX_DRIVE_REG("DRV3CTRL1", 0xe605008c) {
+ { RCAR_GP_PIN(1, 30), 24, 3 }, /* GP1_30 */
+ { RCAR_GP_PIN(1, 29), 20, 3 }, /* GP1_29 */
+ { RCAR_GP_PIN(1, 28), 16, 3 }, /* GP1_28 */
+ { RCAR_GP_PIN(1, 27), 12, 3 }, /* IRQ3 */
+ { RCAR_GP_PIN(1, 26), 8, 3 }, /* IRQ2 */
+ { RCAR_GP_PIN(1, 25), 4, 3 }, /* IRQ1 */
+ { RCAR_GP_PIN(1, 24), 0, 3 }, /* IRQ0 */
+ } },
+ { PINMUX_DRIVE_REG("DRV0CTRL2", 0xe6050880) {
+ { RCAR_GP_PIN(2, 7), 28, 3 }, /* GP2_07 */
+ { RCAR_GP_PIN(2, 6), 24, 3 }, /* GP2_06 */
+ { RCAR_GP_PIN(2, 5), 20, 3 }, /* GP2_05 */
+ { RCAR_GP_PIN(2, 4), 16, 3 }, /* GP2_04 */
+ { RCAR_GP_PIN(2, 3), 12, 3 }, /* GP2_03 */
+ { RCAR_GP_PIN(2, 2), 8, 3 }, /* GP2_02 */
+ { RCAR_GP_PIN(2, 1), 4, 2 }, /* IPC_CLKOUT */
+ { RCAR_GP_PIN(2, 0), 0, 2 }, /* IPC_CLKIN */
+ } },
+ { PINMUX_DRIVE_REG("DRV1CTRL2", 0xe6050884) {
+ { RCAR_GP_PIN(2, 15), 28, 3 }, /* GP2_15 */
+ { RCAR_GP_PIN(2, 14), 24, 3 }, /* GP2_14 */
+ { RCAR_GP_PIN(2, 13), 20, 3 }, /* GP2_13 */
+ { RCAR_GP_PIN(2, 12), 16, 3 }, /* GP2_12 */
+ { RCAR_GP_PIN(2, 11), 12, 3 }, /* GP2_11 */
+ { RCAR_GP_PIN(2, 10), 8, 3 }, /* GP2_10 */
+ { RCAR_GP_PIN(2, 9), 4, 3 }, /* GP2_9 */
+ { RCAR_GP_PIN(2, 8), 0, 3 }, /* GP2_8 */
+ } },
+ { PINMUX_DRIVE_REG("DRV2CTRL2", 0xe6050888) {
+ { RCAR_GP_PIN(2, 23), 28, 3 }, /* TCLK1_A */
+ { RCAR_GP_PIN(2, 22), 24, 3 }, /* TPU0TO1 */
+ { RCAR_GP_PIN(2, 21), 20, 3 }, /* TPU0TO0 */
+ { RCAR_GP_PIN(2, 20), 16, 3 }, /* CLK_EXTFXR */
+ { RCAR_GP_PIN(2, 19), 12, 3 }, /* RXDB_EXTFXR */
+ { RCAR_GP_PIN(2, 18), 8, 3 }, /* FXR_TXDB */
+ { RCAR_GP_PIN(2, 17), 4, 3 }, /* RXDA_EXTFXR_A */
+ { RCAR_GP_PIN(2, 16), 0, 3 }, /* FXR_TXDA_A */
+ } },
+ { PINMUX_DRIVE_REG("DRV3CTRL2", 0xe605088c) {
+ { RCAR_GP_PIN(2, 24), 0, 3 }, /* TCLK2_A */
+ } },
+ { PINMUX_DRIVE_REG("DRV0CTRL3", 0xe6058880) {
+ { RCAR_GP_PIN(3, 7), 28, 3 }, /* CANFD3_TX */
+ { RCAR_GP_PIN(3, 6), 24, 3 }, /* CANFD2_RX */
+ { RCAR_GP_PIN(3, 5), 20, 3 }, /* CANFD2_TX */
+ { RCAR_GP_PIN(3, 4), 16, 3 }, /* CANFD1_RX */
+ { RCAR_GP_PIN(3, 3), 12, 3 }, /* CANFD1_TX */
+ { RCAR_GP_PIN(3, 2), 8, 3 }, /* CANFD0_RX */
+ { RCAR_GP_PIN(3, 1), 4, 2 }, /* CANFD0_TX */
+ { RCAR_GP_PIN(3, 0), 0, 2 }, /* CAN_CLK */
+ } },
+ { PINMUX_DRIVE_REG("DRV1CTRL3", 0xe6058884) {
+ { RCAR_GP_PIN(3, 15), 28, 3 }, /* CANFD7_TX */
+ { RCAR_GP_PIN(3, 14), 24, 3 }, /* CANFD6_RX */
+ { RCAR_GP_PIN(3, 13), 20, 3 }, /* CANFD6_TX */
+ { RCAR_GP_PIN(3, 12), 16, 3 }, /* CANFD5_RX */
+ { RCAR_GP_PIN(3, 11), 12, 3 }, /* CANFD5_TX */
+ { RCAR_GP_PIN(3, 10), 8, 3 }, /* CANFD4_RX */
+ { RCAR_GP_PIN(3, 9), 4, 3 }, /* CANFD4_TX*/
+ { RCAR_GP_PIN(3, 8), 0, 3 }, /* CANFD3_RX */
+ } },
+ { PINMUX_DRIVE_REG("DRV2CTRL3", 0xe6058888) {
+ { RCAR_GP_PIN(3, 16), 0, 3 }, /* CANFD7_RX */
+ } },
+ { PINMUX_DRIVE_REG("DRV0CTRL4", 0xe6060080) {
+ { RCAR_GP_PIN(4, 7), 28, 3 }, /* AVB0_TXC */
+ { RCAR_GP_PIN(4, 6), 24, 3 }, /* AVB0_TX_CTL */
+ { RCAR_GP_PIN(4, 5), 20, 3 }, /* AVB0_RD3 */
+ { RCAR_GP_PIN(4, 4), 16, 3 }, /* AVB0_RD2 */
+ { RCAR_GP_PIN(4, 3), 12, 3 }, /* AVB0_RD1 */
+ { RCAR_GP_PIN(4, 2), 8, 3 }, /* AVB0_RD0 */
+ { RCAR_GP_PIN(4, 1), 4, 3 }, /* AVB0_RXC */
+ { RCAR_GP_PIN(4, 0), 0, 3 }, /* AVB0_RX_CTL */
+ } },
+ { PINMUX_DRIVE_REG("DRV1CTRL4", 0xe6060084) {
+ { RCAR_GP_PIN(4, 15), 28, 3 }, /* AVB0_MAGIC */
+ { RCAR_GP_PIN(4, 14), 24, 3 }, /* AVB0_MDC */
+ { RCAR_GP_PIN(4, 13), 20, 3 }, /* AVB0_MDIO */
+ { RCAR_GP_PIN(4, 12), 16, 3 }, /* AVB0_TXCREFCLK */
+ { RCAR_GP_PIN(4, 11), 12, 3 }, /* AVB0_TD3 */
+ { RCAR_GP_PIN(4, 10), 8, 3 }, /* AVB0_TD2 */
+ { RCAR_GP_PIN(4, 9), 4, 3 }, /* AVB0_TD1*/
+ { RCAR_GP_PIN(4, 8), 0, 3 }, /* AVB0_TD0 */
+ } },
+ { PINMUX_DRIVE_REG("DRV2CTRL4", 0xe6060088) {
+ { RCAR_GP_PIN(4, 23), 28, 3 }, /* PCIE2_CLKREQ_N */
+ { RCAR_GP_PIN(4, 22), 24, 3 }, /* PCIE1_CLKREQ_N */
+ { RCAR_GP_PIN(4, 21), 20, 3 }, /* PCIE0_CLKREQ_N */
+ { RCAR_GP_PIN(4, 20), 16, 3 }, /* AVB0_AVTP_PPS */
+ { RCAR_GP_PIN(4, 19), 12, 3 }, /* AVB0_AVTP_CAPTURE */
+ { RCAR_GP_PIN(4, 18), 8, 3 }, /* AVB0_AVTP_MATCH */
+ { RCAR_GP_PIN(4, 17), 4, 3 }, /* AVB0_LINK */
+ { RCAR_GP_PIN(4, 16), 0, 3 }, /* AVB0_PHY_INT */
+ } },
+ { PINMUX_DRIVE_REG("DRV3CTRL4", 0xe606008c) {
+ { RCAR_GP_PIN(4, 26), 8, 3 }, /* AVS1 */
+ { RCAR_GP_PIN(4, 25), 4, 3 }, /* AVS0 */
+ { RCAR_GP_PIN(4, 24), 0, 3 }, /* PCIE3_CLKREQ_N */
+ } },
+ { PINMUX_DRIVE_REG("DRV0CTRL5", 0xe6060880) {
+ { RCAR_GP_PIN(5, 7), 28, 3 }, /* AVB1_TXC */
+ { RCAR_GP_PIN(5, 6), 24, 3 }, /* AVB1_TX_CTL */
+ { RCAR_GP_PIN(5, 5), 20, 3 }, /* AVB1_RD3 */
+ { RCAR_GP_PIN(5, 4), 16, 3 }, /* AVB1_RD2 */
+ { RCAR_GP_PIN(5, 3), 12, 3 }, /* AVB1_RD1 */
+ { RCAR_GP_PIN(5, 2), 8, 3 }, /* AVB1_RD0 */
+ { RCAR_GP_PIN(5, 1), 4, 3 }, /* AVB1_RXC */
+ { RCAR_GP_PIN(5, 0), 0, 3 }, /* AVB1_RX_CTL */
+ } },
+ { PINMUX_DRIVE_REG("DRV1CTRL5", 0xe6060884) {
+ { RCAR_GP_PIN(5, 15), 28, 3 }, /* AVB1_MAGIC */
+ { RCAR_GP_PIN(5, 14), 24, 3 }, /* AVB1_MDC */
+ { RCAR_GP_PIN(5, 13), 20, 3 }, /* AVB1_MDIO */
+ { RCAR_GP_PIN(5, 12), 16, 3 }, /* AVB1_TXCREFCLK */
+ { RCAR_GP_PIN(5, 11), 12, 3 }, /* AVB1_TD3 */
+ { RCAR_GP_PIN(5, 10), 8, 3 }, /* AVB1_TD2 */
+ { RCAR_GP_PIN(5, 9), 4, 3 }, /* AVB1_TD1*/
+ { RCAR_GP_PIN(5, 8), 0, 3 }, /* AVB1_TD0 */
+ } },
+ { PINMUX_DRIVE_REG("DRV2CTRL5", 0xe6060888) {
+ { RCAR_GP_PIN(5, 20), 16, 3 }, /* AVB1_AVTP_PPS */
+ { RCAR_GP_PIN(5, 19), 12, 3 }, /* AVB1_AVTP_CAPTURE */
+ { RCAR_GP_PIN(5, 18), 8, 3 }, /* AVB1_AVTP_MATCH */
+ { RCAR_GP_PIN(5, 17), 4, 3 }, /* AVB1_LINK */
+ { RCAR_GP_PIN(5, 16), 0, 3 }, /* AVB1_PHY_INT */
+ } },
+ { PINMUX_DRIVE_REG("DRV0CTRL6", 0xe6068080) {
+ { RCAR_GP_PIN(6, 7), 28, 3 }, /* AVB2_TXC */
+ { RCAR_GP_PIN(6, 6), 24, 3 }, /* AVB2_TX_CTL */
+ { RCAR_GP_PIN(6, 5), 20, 3 }, /* AVB2_RD3 */
+ { RCAR_GP_PIN(6, 4), 16, 3 }, /* AVB2_RD2 */
+ { RCAR_GP_PIN(6, 3), 12, 3 }, /* AVB2_RD1 */
+ { RCAR_GP_PIN(6, 2), 8, 3 }, /* AVB2_RD0 */
+ { RCAR_GP_PIN(6, 1), 4, 3 }, /* AVB2_RXC */
+ { RCAR_GP_PIN(6, 0), 0, 3 }, /* AVB2_RX_CTL */
+ } },
+ { PINMUX_DRIVE_REG("DRV1CTRL6", 0xe6068084) {
+ { RCAR_GP_PIN(6, 15), 28, 3 }, /* AVB2_MAGIC */
+ { RCAR_GP_PIN(6, 14), 24, 3 }, /* AVB2_MDC */
+ { RCAR_GP_PIN(6, 13), 20, 3 }, /* AVB2_MDIO */
+ { RCAR_GP_PIN(6, 12), 16, 3 }, /* AVB2_TXCREFCLK */
+ { RCAR_GP_PIN(6, 11), 12, 3 }, /* AVB2_TD3 */
+ { RCAR_GP_PIN(6, 10), 8, 3 }, /* AVB2_TD2 */
+ { RCAR_GP_PIN(6, 9), 4, 3 }, /* AVB2_TD1*/
+ { RCAR_GP_PIN(6, 8), 0, 3 }, /* AVB2_TD0 */
+ } },
+ { PINMUX_DRIVE_REG("DRV2CTRL6", 0xe6068088) {
+ { RCAR_GP_PIN(6, 20), 16, 3 }, /* AVB2_AVTP_PPS */
+ { RCAR_GP_PIN(6, 19), 12, 3 }, /* AVB2_AVTP_CAPTURE */
+ { RCAR_GP_PIN(6, 18), 8, 3 }, /* AVB2_AVTP_MATCH */
+ { RCAR_GP_PIN(6, 17), 4, 3 }, /* AVB2_LINK */
+ { RCAR_GP_PIN(6, 16), 0, 3 }, /* AVB2_PHY_INT */
+ } },
+ { PINMUX_DRIVE_REG("DRV0CTRL7", 0xe6068880) {
+ { RCAR_GP_PIN(7, 7), 28, 3 }, /* AVB3_TXC */
+ { RCAR_GP_PIN(7, 6), 24, 3 }, /* AVB3_TX_CTL */
+ { RCAR_GP_PIN(7, 5), 20, 3 }, /* AVB3_RD3 */
+ { RCAR_GP_PIN(7, 4), 16, 3 }, /* AVB3_RD2 */
+ { RCAR_GP_PIN(7, 3), 12, 3 }, /* AVB3_RD1 */
+ { RCAR_GP_PIN(7, 2), 8, 3 }, /* AVB3_RD0 */
+ { RCAR_GP_PIN(7, 1), 4, 3 }, /* AVB3_RXC */
+ { RCAR_GP_PIN(7, 0), 0, 3 }, /* AVB3_RX_CTL */
+ } },
+ { PINMUX_DRIVE_REG("DRV1CTRL7", 0xe6068884) {
+ { RCAR_GP_PIN(7, 15), 28, 3 }, /* AVB3_MAGIC */
+ { RCAR_GP_PIN(7, 14), 24, 3 }, /* AVB3_MDC */
+ { RCAR_GP_PIN(7, 13), 20, 3 }, /* AVB3_MDIO */
+ { RCAR_GP_PIN(7, 12), 16, 3 }, /* AVB3_TXCREFCLK */
+ { RCAR_GP_PIN(7, 11), 12, 3 }, /* AVB3_TD3 */
+ { RCAR_GP_PIN(7, 10), 8, 3 }, /* AVB3_TD2 */
+ { RCAR_GP_PIN(7, 9), 4, 3 }, /* AVB3_TD1*/
+ { RCAR_GP_PIN(7, 8), 0, 3 }, /* AVB3_TD0 */
+ } },
+ { PINMUX_DRIVE_REG("DRV2CTRL7", 0xe6068888) {
+ { RCAR_GP_PIN(7, 20), 16, 3 }, /* AVB3_AVTP_PPS */
+ { RCAR_GP_PIN(7, 19), 12, 3 }, /* AVB3_AVTP_CAPTURE */
+ { RCAR_GP_PIN(7, 18), 8, 3 }, /* AVB3_AVTP_MATCH */
+ { RCAR_GP_PIN(7, 17), 4, 3 }, /* AVB3_LINK */
+ { RCAR_GP_PIN(7, 16), 0, 3 }, /* AVB3_PHY_INT */
+ } },
+ { PINMUX_DRIVE_REG("DRV0CTRL8", 0xe6069080) {
+ { RCAR_GP_PIN(8, 7), 28, 3 }, /* AVB4_TXC */
+ { RCAR_GP_PIN(8, 6), 24, 3 }, /* AVB4_TX_CTL */
+ { RCAR_GP_PIN(8, 5), 20, 3 }, /* AVB4_RD3 */
+ { RCAR_GP_PIN(8, 4), 16, 3 }, /* AVB4_RD2 */
+ { RCAR_GP_PIN(8, 3), 12, 3 }, /* AVB4_RD1 */
+ { RCAR_GP_PIN(8, 2), 8, 3 }, /* AVB4_RD0 */
+ { RCAR_GP_PIN(8, 1), 4, 3 }, /* AVB4_RXC */
+ { RCAR_GP_PIN(8, 0), 0, 3 }, /* AVB4_RX_CTL */
+ } },
+ { PINMUX_DRIVE_REG("DRV1CTRL8", 0xe6069084) {
+ { RCAR_GP_PIN(8, 15), 28, 3 }, /* AVB4_MAGIC */
+ { RCAR_GP_PIN(8, 14), 24, 3 }, /* AVB4_MDC */
+ { RCAR_GP_PIN(8, 13), 20, 3 }, /* AVB4_MDIO */
+ { RCAR_GP_PIN(8, 12), 16, 3 }, /* AVB4_TXCREFCLK */
+ { RCAR_GP_PIN(8, 11), 12, 3 }, /* AVB4_TD3 */
+ { RCAR_GP_PIN(8, 10), 8, 3 }, /* AVB4_TD2 */
+ { RCAR_GP_PIN(8, 9), 4, 3 }, /* AVB4_TD1*/
+ { RCAR_GP_PIN(8, 8), 0, 3 }, /* AVB4_TD0 */
+ } },
+ { PINMUX_DRIVE_REG("DRV2CTRL8", 0xe6069088) {
+ { RCAR_GP_PIN(8, 20), 16, 3 }, /* AVB4_AVTP_PPS */
+ { RCAR_GP_PIN(8, 19), 12, 3 }, /* AVB4_AVTP_CAPTURE */
+ { RCAR_GP_PIN(8, 18), 8, 3 }, /* AVB4_AVTP_MATCH */
+ { RCAR_GP_PIN(8, 17), 4, 3 }, /* AVB4_LINK */
+ { RCAR_GP_PIN(8, 16), 0, 3 }, /* AVB4_PHY_INT */
+ } },
+ { PINMUX_DRIVE_REG("DRV0CTRL9", 0xe6069880) {
+ { RCAR_GP_PIN(9, 7), 28, 3 }, /* AVB5_TXC */
+ { RCAR_GP_PIN(9, 6), 24, 3 }, /* AVB5_TX_CTL */
+ { RCAR_GP_PIN(9, 5), 20, 3 }, /* AVB5_RD3 */
+ { RCAR_GP_PIN(9, 4), 16, 3 }, /* AVB5_RD2 */
+ { RCAR_GP_PIN(9, 3), 12, 3 }, /* AVB5_RD1 */
+ { RCAR_GP_PIN(9, 2), 8, 3 }, /* AVB5_RD0 */
+ { RCAR_GP_PIN(9, 1), 4, 3 }, /* AVB5_RXC */
+ { RCAR_GP_PIN(9, 0), 0, 3 }, /* AVB5_RX_CTL */
+ } },
+ { PINMUX_DRIVE_REG("DRV1CTRL9", 0xe6069884) {
+ { RCAR_GP_PIN(9, 15), 28, 3 }, /* AVB5_MAGIC */
+ { RCAR_GP_PIN(9, 14), 24, 3 }, /* AVB5_MDC */
+ { RCAR_GP_PIN(9, 13), 20, 3 }, /* AVB5_MDIO */
+ { RCAR_GP_PIN(9, 12), 16, 3 }, /* AVB5_TXCREFCLK */
+ { RCAR_GP_PIN(9, 11), 12, 3 }, /* AVB5_TD3 */
+ { RCAR_GP_PIN(9, 10), 8, 3 }, /* AVB5_TD2 */
+ { RCAR_GP_PIN(9, 9), 4, 3 }, /* AVB5_TD1*/
+ { RCAR_GP_PIN(9, 8), 0, 3 }, /* AVB5_TD0 */
+ } },
+ { PINMUX_DRIVE_REG("DRV2CTRL9", 0xe6069888) {
+ { RCAR_GP_PIN(9, 20), 16, 3 }, /* AVB5_AVTP_PPS */
+ { RCAR_GP_PIN(9, 19), 12, 3 }, /* AVB5_AVTP_CAPTURE */
+ { RCAR_GP_PIN(9, 18), 8, 3 }, /* AVB5_AVTP_MATCH */
+ { RCAR_GP_PIN(9, 17), 4, 3 }, /* AVB5_LINK */
+ { RCAR_GP_PIN(9, 16), 0, 3 }, /* AVB5_PHY_INT */
+ } },
+ { },
+};
+
+enum ioctrl_regs {
+ POC0,
+ POC1,
+ POC2,
+ POC4,
+ POC5,
+ POC6,
+ POC7,
+ POC8,
+ POC9,
+ TD1SEL0,
+};
+
+static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
+ [POC0] = { 0xe60580a0, },
+ [POC1] = { 0xe60500a0, },
+ [POC2] = { 0xe60508a0, },
+ [POC4] = { 0xe60600a0, },
+ [POC5] = { 0xe60608a0, },
+ [POC6] = { 0xe60680a0, },
+ [POC7] = { 0xe60688a0, },
+ [POC8] = { 0xe60690a0, },
+ [POC9] = { 0xe60698a0, },
+ [TD1SEL0] = { 0xe6058124, },
+ { /* sentinel */ },
+};
+
+static int r8a779a0_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin,
+ u32 *pocctrl)
+{
+ int bit = pin & 0x1f;
+
+ *pocctrl = pinmux_ioctrl_regs[POC0].reg;
+ if (pin >= RCAR_GP_PIN(0, 15) && pin <= RCAR_GP_PIN(0, 27))
+ return bit;
+
+ *pocctrl = pinmux_ioctrl_regs[POC1].reg;
+ if (pin >= RCAR_GP_PIN(1, 0) && pin <= RCAR_GP_PIN(1, 30))
+ return bit;
+
+ *pocctrl = pinmux_ioctrl_regs[POC2].reg;
+ if (pin >= RCAR_GP_PIN(2, 2) && pin <= RCAR_GP_PIN(2, 15))
+ return bit;
+
+ *pocctrl = pinmux_ioctrl_regs[POC4].reg;
+ if (pin >= RCAR_GP_PIN(4, 0) && pin <= RCAR_GP_PIN(4, 17))
+ return bit;
+
+ *pocctrl = pinmux_ioctrl_regs[POC5].reg;
+ if (pin >= RCAR_GP_PIN(5, 0) && pin <= RCAR_GP_PIN(5, 17))
+ return bit;
+
+ *pocctrl = pinmux_ioctrl_regs[POC6].reg;
+ if (pin >= RCAR_GP_PIN(6, 0) && pin <= RCAR_GP_PIN(6, 17))
+ return bit;
+
+ *pocctrl = pinmux_ioctrl_regs[POC7].reg;
+ if (pin >= RCAR_GP_PIN(7, 0) && pin <= RCAR_GP_PIN(7, 17))
+ return bit;
+
+ *pocctrl = pinmux_ioctrl_regs[POC8].reg;
+ if (pin >= RCAR_GP_PIN(8, 0) && pin <= RCAR_GP_PIN(8, 17))
+ return bit;
+
+ *pocctrl = pinmux_ioctrl_regs[POC9].reg;
+ if (pin >= RCAR_GP_PIN(9, 0) && pin <= RCAR_GP_PIN(9, 17))
+ return bit;
+
+ return -EINVAL;
+}
+
+static const struct pinmux_bias_reg pinmux_bias_regs[] = {
+ { PINMUX_BIAS_REG("PUEN0", 0xe60580c0, "PUD0", 0xe60580e0) {
+ [ 0] = RCAR_GP_PIN(0, 0), /* QSPI0_SPCLK */
+ [ 1] = RCAR_GP_PIN(0, 1), /* QSPI0_MOSI_IO0 */
+ [ 2] = RCAR_GP_PIN(0, 2), /* QSPI0_MISO_IO1 */
+ [ 3] = RCAR_GP_PIN(0, 3), /* QSPI0_IO2 */
+ [ 4] = RCAR_GP_PIN(0, 4), /* QSPI0_IO3 */
+ [ 5] = RCAR_GP_PIN(0, 5), /* QSPI0_SSL */
+ [ 6] = RCAR_GP_PIN(0, 6), /* QSPI1_SPCLK */
+ [ 7] = RCAR_GP_PIN(0, 7), /* QSPI1_MOSI_IO0 */
+ [ 8] = RCAR_GP_PIN(0, 8), /* QSPI1_MISO_IO1 */
+ [ 9] = RCAR_GP_PIN(0, 9), /* QSPI1_IO2 */
+ [10] = RCAR_GP_PIN(0, 10), /* QSPI1_IO3 */
+ [11] = RCAR_GP_PIN(0, 11), /* QSPI1_SSL */
+ [12] = RCAR_GP_PIN(0, 12), /* RPC_RESET_N */
+ [13] = RCAR_GP_PIN(0, 13), /* RPC_WP_N */
+ [14] = RCAR_GP_PIN(0, 14), /* RPC_INT_N */
+ [15] = RCAR_GP_PIN(0, 15), /* SD_WP */
+ [16] = RCAR_GP_PIN(0, 16), /* SD_CD */
+ [17] = RCAR_GP_PIN(0, 17), /* MMC_DS */
+ [18] = RCAR_GP_PIN(0, 18), /* MMC_SD_CMD */
+ [19] = RCAR_GP_PIN(0, 19), /* MMC_SD_D0 */
+ [20] = RCAR_GP_PIN(0, 20), /* MMC_SD_D1 */
+ [21] = RCAR_GP_PIN(0, 21), /* MMC_SD_D2 */
+ [22] = RCAR_GP_PIN(0, 22), /* MMC_SD_D3 */
+ [23] = RCAR_GP_PIN(0, 23), /* MMC_SD_CLK */
+ [24] = RCAR_GP_PIN(0, 24), /* MMC_D4 */
+ [25] = RCAR_GP_PIN(0, 25), /* MMC_D5 */
+ [26] = RCAR_GP_PIN(0, 26), /* MMC_D6 */
+ [27] = RCAR_GP_PIN(0, 27), /* MMC_D7 */
+ [28] = SH_PFC_PIN_NONE,
+ [29] = SH_PFC_PIN_NONE,
+ [30] = SH_PFC_PIN_NONE,
+ [31] = SH_PFC_PIN_NONE,
+ } },
+ { PINMUX_BIAS_REG("PUEN1", 0xe60500c0, "PUD1", 0xe60500e0) {
+ [ 0] = RCAR_GP_PIN(1, 0), /* SCIF_CLK */
+ [ 1] = RCAR_GP_PIN(1, 1), /* HRX0 */
+ [ 2] = RCAR_GP_PIN(1, 2), /* HSCK0 */
+ [ 3] = RCAR_GP_PIN(1, 3), /* HRTS0_N */
+ [ 4] = RCAR_GP_PIN(1, 4), /* HCTS0_N */
+ [ 5] = RCAR_GP_PIN(1, 5), /* HTX0 */
+ [ 6] = RCAR_GP_PIN(1, 6), /* MSIOF0_RXD */
+ [ 7] = RCAR_GP_PIN(1, 7), /* MSIOF0_TXD */
+ [ 8] = RCAR_GP_PIN(1, 8), /* MSIOF0_SCK */
+ [ 9] = RCAR_GP_PIN(1, 9), /* MSIOF0_SYNC */
+ [10] = RCAR_GP_PIN(1, 10), /* MSIOF0_SS1 */
+ [11] = RCAR_GP_PIN(1, 11), /* MSIOF0_SS2 */
+ [12] = RCAR_GP_PIN(1, 12), /* MSIOF1_RXD */
+ [13] = RCAR_GP_PIN(1, 13), /* MSIOF1_TXD */
+ [14] = RCAR_GP_PIN(1, 14), /* MSIOF1_SCK */
+ [15] = RCAR_GP_PIN(1, 15), /* MSIOF1_SYNC */
+ [16] = RCAR_GP_PIN(1, 16), /* MSIOF1_SS1 */
+ [17] = RCAR_GP_PIN(1, 17), /* MSIOF1_SS2 */
+ [18] = RCAR_GP_PIN(1, 18), /* MSIOF2_RXD */
+ [19] = RCAR_GP_PIN(1, 19), /* MSIOF2_TXD */
+ [20] = RCAR_GP_PIN(1, 20), /* MSIOF2_SCK */
+ [21] = RCAR_GP_PIN(1, 21), /* MSIOF2_SYNC */
+ [22] = RCAR_GP_PIN(1, 22), /* MSIOF2_SS1 */
+ [23] = RCAR_GP_PIN(1, 23), /* MSIOF2_SS2 */
+ [24] = RCAR_GP_PIN(1, 24), /* IRQ0 */
+ [25] = RCAR_GP_PIN(1, 25), /* IRQ1 */
+ [26] = RCAR_GP_PIN(1, 26), /* IRQ2 */
+ [27] = RCAR_GP_PIN(1, 27), /* IRQ3 */
+ [28] = RCAR_GP_PIN(1, 28), /* GP1_28 */
+ [29] = RCAR_GP_PIN(1, 29), /* GP1_29 */
+ [30] = RCAR_GP_PIN(1, 30), /* GP1_30 */
+ [31] = SH_PFC_PIN_NONE,
+ } },
+ { PINMUX_BIAS_REG("PUEN2", 0xe60508c0, "PUD2", 0xe60508e0) {
+ [ 0] = RCAR_GP_PIN(2, 0), /* IPC_CLKIN */
+ [ 1] = RCAR_GP_PIN(2, 1), /* IPC_CLKOUT */
+ [ 2] = RCAR_GP_PIN(2, 2), /* GP2_02 */
+ [ 3] = RCAR_GP_PIN(2, 3), /* GP2_03 */
+ [ 4] = RCAR_GP_PIN(2, 4), /* GP2_04 */
+ [ 5] = RCAR_GP_PIN(2, 5), /* GP2_05 */
+ [ 6] = RCAR_GP_PIN(2, 6), /* GP2_06 */
+ [ 7] = RCAR_GP_PIN(2, 7), /* GP2_07 */
+ [ 8] = RCAR_GP_PIN(2, 8), /* GP2_08 */
+ [ 9] = RCAR_GP_PIN(2, 9), /* GP2_09 */
+ [10] = RCAR_GP_PIN(2, 10), /* GP2_10 */
+ [11] = RCAR_GP_PIN(2, 11), /* GP2_11 */
+ [12] = RCAR_GP_PIN(2, 12), /* GP2_12 */
+ [13] = RCAR_GP_PIN(2, 13), /* GP2_13 */
+ [14] = RCAR_GP_PIN(2, 14), /* GP2_14 */
+ [15] = RCAR_GP_PIN(2, 15), /* GP2_15 */
+ [16] = RCAR_GP_PIN(2, 16), /* FXR_TXDA_A */
+ [17] = RCAR_GP_PIN(2, 17), /* RXDA_EXTFXR_A */
+ [18] = RCAR_GP_PIN(2, 18), /* FXR_TXDB */
+ [19] = RCAR_GP_PIN(2, 19), /* RXDB_EXTFXR */
+ [20] = RCAR_GP_PIN(2, 20), /* CLK_EXTFXR */
+ [21] = RCAR_GP_PIN(2, 21), /* TPU0TO0 */
+ [22] = RCAR_GP_PIN(2, 22), /* TPU0TO1 */
+ [23] = RCAR_GP_PIN(2, 23), /* TCLK1_A */
+ [24] = RCAR_GP_PIN(2, 24), /* TCLK2_A */
+ [25] = SH_PFC_PIN_NONE,
+ [26] = SH_PFC_PIN_NONE,
+ [27] = SH_PFC_PIN_NONE,
+ [28] = SH_PFC_PIN_NONE,
+ [29] = SH_PFC_PIN_NONE,
+ [30] = SH_PFC_PIN_NONE,
+ [31] = SH_PFC_PIN_NONE,
+ } },
+ { PINMUX_BIAS_REG("PUEN3", 0xe60588c0, "PUD3", 0xe60588e0) {
+ [ 0] = RCAR_GP_PIN(3, 0), /* CAN_CLK */
+ [ 1] = RCAR_GP_PIN(3, 1), /* CANFD0_TX */
+ [ 2] = RCAR_GP_PIN(3, 2), /* CANFD0_RX */
+ [ 3] = RCAR_GP_PIN(3, 3), /* CANFD1_TX */
+ [ 4] = RCAR_GP_PIN(3, 4), /* CANFD1_RX */
+ [ 5] = RCAR_GP_PIN(3, 5), /* CANFD2_TX */
+ [ 6] = RCAR_GP_PIN(3, 6), /* CANFD2_RX */
+ [ 7] = RCAR_GP_PIN(3, 7), /* CANFD3_TX */
+ [ 8] = RCAR_GP_PIN(3, 8), /* CANFD3_RX */
+ [ 9] = RCAR_GP_PIN(3, 9), /* CANFD4_TX */
+ [10] = RCAR_GP_PIN(3, 10), /* CANFD4_RX */
+ [11] = RCAR_GP_PIN(3, 11), /* CANFD5_TX */
+ [12] = RCAR_GP_PIN(3, 12), /* CANFD5_RX */
+ [13] = RCAR_GP_PIN(3, 13), /* CANFD6_TX */
+ [14] = RCAR_GP_PIN(3, 14), /* CANFD6_RX */
+ [15] = RCAR_GP_PIN(3, 15), /* CANFD7_TX */
+ [16] = RCAR_GP_PIN(3, 16), /* CANFD7_RX */
+ [17] = SH_PFC_PIN_NONE,
+ [18] = SH_PFC_PIN_NONE,
+ [19] = SH_PFC_PIN_NONE,
+ [20] = SH_PFC_PIN_NONE,
+ [21] = SH_PFC_PIN_NONE,
+ [22] = SH_PFC_PIN_NONE,
+ [23] = SH_PFC_PIN_NONE,
+ [24] = SH_PFC_PIN_NONE,
+ [25] = SH_PFC_PIN_NONE,
+ [26] = SH_PFC_PIN_NONE,
+ [27] = SH_PFC_PIN_NONE,
+ [28] = SH_PFC_PIN_NONE,
+ [29] = SH_PFC_PIN_NONE,
+ [30] = SH_PFC_PIN_NONE,
+ [31] = SH_PFC_PIN_NONE,
+ } },
+ { PINMUX_BIAS_REG("PUEN4", 0xe60600c0, "PUD4", 0xe60600e0) {
+ [ 0] = RCAR_GP_PIN(4, 0), /* AVB0_RX_CTL */
+ [ 1] = RCAR_GP_PIN(4, 1), /* AVB0_RXC */
+ [ 2] = RCAR_GP_PIN(4, 2), /* AVB0_RD0 */
+ [ 3] = RCAR_GP_PIN(4, 3), /* AVB0_RD1 */
+ [ 4] = RCAR_GP_PIN(4, 4), /* AVB0_RD2 */
+ [ 5] = RCAR_GP_PIN(4, 5), /* AVB0_RD3 */
+ [ 6] = RCAR_GP_PIN(4, 6), /* AVB0_TX_CTL */
+ [ 7] = RCAR_GP_PIN(4, 7), /* AVB0_TXC */
+ [ 8] = RCAR_GP_PIN(4, 8), /* AVB0_TD0 */
+ [ 9] = RCAR_GP_PIN(4, 9), /* AVB0_TD1 */
+ [10] = RCAR_GP_PIN(4, 10), /* AVB0_TD2 */
+ [11] = RCAR_GP_PIN(4, 11), /* AVB0_TD3 */
+ [12] = RCAR_GP_PIN(4, 12), /* AVB0_TXREFCLK */
+ [13] = RCAR_GP_PIN(4, 13), /* AVB0_MDIO */
+ [14] = RCAR_GP_PIN(4, 14), /* AVB0_MDC */
+ [15] = RCAR_GP_PIN(4, 15), /* AVB0_MAGIC */
+ [16] = RCAR_GP_PIN(4, 16), /* AVB0_PHY_INT */
+ [17] = RCAR_GP_PIN(4, 17), /* AVB0_LINK */
+ [18] = RCAR_GP_PIN(4, 18), /* AVB0_AVTP_MATCH */
+ [19] = RCAR_GP_PIN(4, 19), /* AVB0_AVTP_CAPTURE */
+ [20] = RCAR_GP_PIN(4, 20), /* AVB0_AVTP_PPS */
+ [21] = RCAR_GP_PIN(4, 21), /* PCIE0_CLKREQ_N */
+ [22] = RCAR_GP_PIN(4, 22), /* PCIE1_CLKREQ_N */
+ [23] = RCAR_GP_PIN(4, 23), /* PCIE2_CLKREQ_N */
+ [24] = RCAR_GP_PIN(4, 24), /* PCIE3_CLKREQ_N */
+ [25] = RCAR_GP_PIN(4, 25), /* AVS0 */
+ [26] = RCAR_GP_PIN(4, 26), /* AVS1 */
+ [27] = SH_PFC_PIN_NONE,
+ [28] = SH_PFC_PIN_NONE,
+ [29] = SH_PFC_PIN_NONE,
+ [30] = SH_PFC_PIN_NONE,
+ [31] = SH_PFC_PIN_NONE,
+ } },
+ { PINMUX_BIAS_REG("PUEN5", 0xe60608c0, "PUD5", 0xe60608e0) {
+ [ 0] = RCAR_GP_PIN(5, 0), /* AVB1_RX_CTL */
+ [ 1] = RCAR_GP_PIN(5, 1), /* AVB1_RXC */
+ [ 2] = RCAR_GP_PIN(5, 2), /* AVB1_RD0 */
+ [ 3] = RCAR_GP_PIN(5, 3), /* AVB1_RD1 */
+ [ 4] = RCAR_GP_PIN(5, 4), /* AVB1_RD2 */
+ [ 5] = RCAR_GP_PIN(5, 5), /* AVB1_RD3 */
+ [ 6] = RCAR_GP_PIN(5, 6), /* AVB1_TX_CTL */
+ [ 7] = RCAR_GP_PIN(5, 7), /* AVB1_TXC */
+ [ 8] = RCAR_GP_PIN(5, 8), /* AVB1_TD0 */
+ [ 9] = RCAR_GP_PIN(5, 9), /* AVB1_TD1 */
+ [10] = RCAR_GP_PIN(5, 10), /* AVB1_TD2 */
+ [11] = RCAR_GP_PIN(5, 11), /* AVB1_TD3 */
+ [12] = RCAR_GP_PIN(5, 12), /* AVB1_TXCREFCLK */
+ [13] = RCAR_GP_PIN(5, 13), /* AVB1_MDIO */
+ [14] = RCAR_GP_PIN(5, 14), /* AVB1_MDC */
+ [15] = RCAR_GP_PIN(5, 15), /* AVB1_MAGIC */
+ [16] = RCAR_GP_PIN(5, 16), /* AVB1_PHY_INT */
+ [17] = RCAR_GP_PIN(5, 17), /* AVB1_LINK */
+ [18] = RCAR_GP_PIN(5, 18), /* AVB1_AVTP_MATCH */
+ [19] = RCAR_GP_PIN(5, 19), /* AVB1_AVTP_CAPTURE */
+ [20] = RCAR_GP_PIN(5, 20), /* AVB1_AVTP_PPS */
+ [21] = SH_PFC_PIN_NONE,
+ [22] = SH_PFC_PIN_NONE,
+ [23] = SH_PFC_PIN_NONE,
+ [24] = SH_PFC_PIN_NONE,
+ [25] = SH_PFC_PIN_NONE,
+ [26] = SH_PFC_PIN_NONE,
+ [27] = SH_PFC_PIN_NONE,
+ [28] = SH_PFC_PIN_NONE,
+ [29] = SH_PFC_PIN_NONE,
+ [30] = SH_PFC_PIN_NONE,
+ [31] = SH_PFC_PIN_NONE,
+ } },
+ { PINMUX_BIAS_REG("PUEN6", 0xe60680c0, "PUD6", 0xe60680e0) {
+ [ 0] = RCAR_GP_PIN(6, 0), /* AVB2_RX_CTL */
+ [ 1] = RCAR_GP_PIN(6, 1), /* AVB2_RXC */
+ [ 2] = RCAR_GP_PIN(6, 2), /* AVB2_RD0 */
+ [ 3] = RCAR_GP_PIN(6, 3), /* AVB2_RD1 */
+ [ 4] = RCAR_GP_PIN(6, 4), /* AVB2_RD2 */
+ [ 5] = RCAR_GP_PIN(6, 5), /* AVB2_RD3 */
+ [ 6] = RCAR_GP_PIN(6, 6), /* AVB2_TX_CTL */
+ [ 7] = RCAR_GP_PIN(6, 7), /* AVB2_TXC */
+ [ 8] = RCAR_GP_PIN(6, 8), /* AVB2_TD0 */
+ [ 9] = RCAR_GP_PIN(6, 9), /* AVB2_TD1 */
+ [10] = RCAR_GP_PIN(6, 10), /* AVB2_TD2 */
+ [11] = RCAR_GP_PIN(6, 11), /* AVB2_TD3 */
+ [12] = RCAR_GP_PIN(6, 12), /* AVB2_TXCREFCLK */
+ [13] = RCAR_GP_PIN(6, 13), /* AVB2_MDIO */
+ [14] = RCAR_GP_PIN(6, 14), /* AVB2_MDC*/
+ [15] = RCAR_GP_PIN(6, 15), /* AVB2_MAGIC */
+ [16] = RCAR_GP_PIN(6, 16), /* AVB2_PHY_INT */
+ [17] = RCAR_GP_PIN(6, 17), /* AVB2_LINK */
+ [18] = RCAR_GP_PIN(6, 18), /* AVB2_AVTP_MATCH */
+ [19] = RCAR_GP_PIN(6, 19), /* AVB2_AVTP_CAPTURE */
+ [20] = RCAR_GP_PIN(6, 20), /* AVB2_AVTP_PPS */
+ [21] = SH_PFC_PIN_NONE,
+ [22] = SH_PFC_PIN_NONE,
+ [23] = SH_PFC_PIN_NONE,
+ [24] = SH_PFC_PIN_NONE,
+ [25] = SH_PFC_PIN_NONE,
+ [26] = SH_PFC_PIN_NONE,
+ [27] = SH_PFC_PIN_NONE,
+ [28] = SH_PFC_PIN_NONE,
+ [29] = SH_PFC_PIN_NONE,
+ [30] = SH_PFC_PIN_NONE,
+ [31] = SH_PFC_PIN_NONE,
+ } },
+ { PINMUX_BIAS_REG("PUEN7", 0xe60688c0, "PUD7", 0xe60688e0) {
+ [ 0] = RCAR_GP_PIN(7, 0), /* AVB3_RX_CTL */
+ [ 1] = RCAR_GP_PIN(7, 1), /* AVB3_RXC */
+ [ 2] = RCAR_GP_PIN(7, 2), /* AVB3_RD0 */
+ [ 3] = RCAR_GP_PIN(7, 3), /* AVB3_RD1 */
+ [ 4] = RCAR_GP_PIN(7, 4), /* AVB3_RD2 */
+ [ 5] = RCAR_GP_PIN(7, 5), /* AVB3_RD3 */
+ [ 6] = RCAR_GP_PIN(7, 6), /* AVB3_TX_CTL */
+ [ 7] = RCAR_GP_PIN(7, 7), /* AVB3_TXC */
+ [ 8] = RCAR_GP_PIN(7, 8), /* AVB3_TD0 */
+ [ 9] = RCAR_GP_PIN(7, 9), /* AVB3_TD1 */
+ [10] = RCAR_GP_PIN(7, 10), /* AVB3_TD2 */
+ [11] = RCAR_GP_PIN(7, 11), /* AVB3_TD3 */
+ [12] = RCAR_GP_PIN(7, 12), /* AVB3_TXCREFCLK */
+ [13] = RCAR_GP_PIN(7, 13), /* AVB3_MDIO */
+ [14] = RCAR_GP_PIN(7, 14), /* AVB3_MDC */
+ [15] = RCAR_GP_PIN(7, 15), /* AVB3_MAGIC */
+ [16] = RCAR_GP_PIN(7, 16), /* AVB3_PHY_INT */
+ [17] = RCAR_GP_PIN(7, 17), /* AVB3_LINK */
+ [18] = RCAR_GP_PIN(7, 18), /* AVB3_AVTP_MATCH */
+ [19] = RCAR_GP_PIN(7, 19), /* AVB3_AVTP_CAPTURE */
+ [20] = RCAR_GP_PIN(7, 20), /* AVB3_AVTP_PPS */
+ [21] = SH_PFC_PIN_NONE,
+ [22] = SH_PFC_PIN_NONE,
+ [23] = SH_PFC_PIN_NONE,
+ [24] = SH_PFC_PIN_NONE,
+ [25] = SH_PFC_PIN_NONE,
+ [26] = SH_PFC_PIN_NONE,
+ [27] = SH_PFC_PIN_NONE,
+ [28] = SH_PFC_PIN_NONE,
+ [29] = SH_PFC_PIN_NONE,
+ [30] = SH_PFC_PIN_NONE,
+ [31] = SH_PFC_PIN_NONE,
+ } },
+ { PINMUX_BIAS_REG("PUEN8", 0xe60690c0, "PUD8", 0xe60690e0) {
+ [ 0] = RCAR_GP_PIN(8, 0), /* AVB4_RX_CTL */
+ [ 1] = RCAR_GP_PIN(8, 1), /* AVB4_RXC */
+ [ 2] = RCAR_GP_PIN(8, 2), /* AVB4_RD0 */
+ [ 3] = RCAR_GP_PIN(8, 3), /* AVB4_RD1 */
+ [ 4] = RCAR_GP_PIN(8, 4), /* AVB4_RD2 */
+ [ 5] = RCAR_GP_PIN(8, 5), /* AVB4_RD3 */
+ [ 6] = RCAR_GP_PIN(8, 6), /* AVB4_TX_CTL */
+ [ 7] = RCAR_GP_PIN(8, 7), /* AVB4_TXC */
+ [ 8] = RCAR_GP_PIN(8, 8), /* AVB4_TD0 */
+ [ 9] = RCAR_GP_PIN(8, 9), /* AVB4_TD1 */
+ [10] = RCAR_GP_PIN(8, 10), /* AVB4_TD2 */
+ [11] = RCAR_GP_PIN(8, 11), /* AVB4_TD3 */
+ [12] = RCAR_GP_PIN(8, 12), /* AVB4_TXCREFCLK */
+ [13] = RCAR_GP_PIN(8, 13), /* AVB4_MDIO */
+ [14] = RCAR_GP_PIN(8, 14), /* AVB4_MDC */
+ [15] = RCAR_GP_PIN(8, 15), /* AVB4_MAGIC */
+ [16] = RCAR_GP_PIN(8, 16), /* AVB4_PHY_INT */
+ [17] = RCAR_GP_PIN(8, 17), /* AVB4_LINK */
+ [18] = RCAR_GP_PIN(8, 18), /* AVB4_AVTP_MATCH */
+ [19] = RCAR_GP_PIN(8, 19), /* AVB4_AVTP_CAPTURE */
+ [20] = RCAR_GP_PIN(8, 20), /* AVB4_AVTP_PPS */
+ [21] = SH_PFC_PIN_NONE,
+ [22] = SH_PFC_PIN_NONE,
+ [23] = SH_PFC_PIN_NONE,
+ [24] = SH_PFC_PIN_NONE,
+ [25] = SH_PFC_PIN_NONE,
+ [26] = SH_PFC_PIN_NONE,
+ [27] = SH_PFC_PIN_NONE,
+ [28] = SH_PFC_PIN_NONE,
+ [29] = SH_PFC_PIN_NONE,
+ [30] = SH_PFC_PIN_NONE,
+ [31] = SH_PFC_PIN_NONE,
+ } },
+ { PINMUX_BIAS_REG("PUEN9", 0xe60698c0, "PUD9", 0xe60698e0) {
+ [ 0] = RCAR_GP_PIN(9, 0), /* AVB5_RX_CTL */
+ [ 1] = RCAR_GP_PIN(9, 1), /* AVB5_RXC */
+ [ 2] = RCAR_GP_PIN(9, 2), /* AVB5_RD0 */
+ [ 3] = RCAR_GP_PIN(9, 3), /* AVB5_RD1 */
+ [ 4] = RCAR_GP_PIN(9, 4), /* AVB5_RD2 */
+ [ 5] = RCAR_GP_PIN(9, 5), /* AVB5_RD3 */
+ [ 6] = RCAR_GP_PIN(9, 6), /* AVB5_TX_CTL */
+ [ 7] = RCAR_GP_PIN(9, 7), /* AVB5_TXC */
+ [ 8] = RCAR_GP_PIN(9, 8), /* AVB5_TD0 */
+ [ 9] = RCAR_GP_PIN(9, 9), /* AVB5_TD1 */
+ [10] = RCAR_GP_PIN(9, 10), /* AVB5_TD2 */
+ [11] = RCAR_GP_PIN(9, 11), /* AVB5_TD3 */
+ [12] = RCAR_GP_PIN(9, 12), /* AVB5_TXCREFCLK */
+ [13] = RCAR_GP_PIN(9, 13), /* AVB5_MDIO */
+ [14] = RCAR_GP_PIN(9, 14), /* AVB5_MDC */
+ [15] = RCAR_GP_PIN(9, 15), /* AVB5_MAGIC */
+ [16] = RCAR_GP_PIN(9, 16), /* AVB5_PHY_INT */
+ [17] = RCAR_GP_PIN(9, 17), /* AVB5_LINK */
+ [18] = RCAR_GP_PIN(9, 18), /* AVB5_AVTP_MATCH */
+ [19] = RCAR_GP_PIN(9, 19), /* AVB5_AVTP_CAPTURE */
+ [20] = RCAR_GP_PIN(9, 20), /* AVB5_AVTP_PPS */
+ [21] = SH_PFC_PIN_NONE,
+ [22] = SH_PFC_PIN_NONE,
+ [23] = SH_PFC_PIN_NONE,
+ [24] = SH_PFC_PIN_NONE,
+ [25] = SH_PFC_PIN_NONE,
+ [26] = SH_PFC_PIN_NONE,
+ [27] = SH_PFC_PIN_NONE,
+ [28] = SH_PFC_PIN_NONE,
+ [29] = SH_PFC_PIN_NONE,
+ [30] = SH_PFC_PIN_NONE,
+ [31] = SH_PFC_PIN_NONE,
+ } },
+ { /* sentinel */ },
+};
+
+static const struct sh_pfc_soc_operations pinmux_ops = {
+ .pin_to_pocctrl = r8a779a0_pin_to_pocctrl,
+ .get_bias = rcar_pinmux_get_bias,
+ .set_bias = rcar_pinmux_set_bias,
+};
+
+const struct sh_pfc_soc_info r8a779a0_pinmux_info = {
+ .name = "r8a779a0_pfc",
+ .ops = &pinmux_ops,
+ .unlock_reg = 0x1ff, /* PMMRn mask */
+
+ .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
+
+ .pins = pinmux_pins,
+ .nr_pins = ARRAY_SIZE(pinmux_pins),
+ .groups = pinmux_groups,
+ .nr_groups = ARRAY_SIZE(pinmux_groups),
+ .functions = pinmux_functions,
+ .nr_functions = ARRAY_SIZE(pinmux_functions),
+
+ .cfg_regs = pinmux_config_regs,
+ .drive_regs = pinmux_drive_regs,
+ .bias_regs = pinmux_bias_regs,
+ .ioctrl_regs = pinmux_ioctrl_regs,
+
+ .pinmux_data = pinmux_data,
+ .pinmux_data_size = ARRAY_SIZE(pinmux_data),
+};
diff --git a/drivers/pinctrl/renesas/pinctrl.c b/drivers/pinctrl/renesas/pinctrl.c
index ac542d2..a49f747 100644
--- a/drivers/pinctrl/renesas/pinctrl.c
+++ b/drivers/pinctrl/renesas/pinctrl.c
@@ -634,6 +634,9 @@
}
case PIN_CONFIG_POWER_SOURCE: {
+ int idx = sh_pfc_get_pin_index(pfc, _pin);
+ const struct sh_pfc_pin *pin = &pfc->info->pins[idx];
+ unsigned int lower_voltage;
u32 pocctrl, val;
int bit;
@@ -648,7 +651,10 @@
val = sh_pfc_read(pfc, pocctrl);
spin_unlock_irqrestore(&pfc->lock, flags);
- arg = (val & BIT(bit)) ? 3300 : 1800;
+ lower_voltage = (pin->configs & SH_PFC_PIN_VOLTAGE_25_33) ?
+ 2500 : 1800;
+
+ arg = (val & BIT(bit)) ? 3300 : lower_voltage;
break;
}
@@ -702,6 +708,9 @@
case PIN_CONFIG_POWER_SOURCE: {
unsigned int mV = pinconf_to_config_argument(configs[i]);
+ int idx = sh_pfc_get_pin_index(pfc, _pin);
+ const struct sh_pfc_pin *pin = &pfc->info->pins[idx];
+ unsigned int lower_voltage;
u32 pocctrl, val;
int bit;
@@ -712,7 +721,10 @@
if (WARN(bit < 0, "invalid pin %#x", _pin))
return bit;
- if (mV != 1800 && mV != 3300)
+ lower_voltage = (pin->configs & SH_PFC_PIN_VOLTAGE_25_33) ?
+ 2500 : 1800;
+
+ if (mV != lower_voltage && mV != 3300)
return -EINVAL;
spin_lock_irqsave(&pfc->lock, flags);
diff --git a/drivers/pinctrl/renesas/sh_pfc.h b/drivers/pinctrl/renesas/sh_pfc.h
index dc484c1..5934fae 100644
--- a/drivers/pinctrl/renesas/sh_pfc.h
+++ b/drivers/pinctrl/renesas/sh_pfc.h
@@ -31,6 +31,15 @@
SH_PFC_PIN_CFG_PULL_DOWN)
#define SH_PFC_PIN_CFG_IO_VOLTAGE (1 << 4)
#define SH_PFC_PIN_CFG_DRIVE_STRENGTH (1 << 5)
+
+#define SH_PFC_PIN_VOLTAGE_18_33 (0 << 6)
+#define SH_PFC_PIN_VOLTAGE_25_33 (1 << 6)
+
+#define SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 (SH_PFC_PIN_CFG_IO_VOLTAGE | \
+ SH_PFC_PIN_VOLTAGE_18_33)
+#define SH_PFC_PIN_CFG_IO_VOLTAGE_25_33 (SH_PFC_PIN_CFG_IO_VOLTAGE | \
+ SH_PFC_PIN_VOLTAGE_25_33)
+
#define SH_PFC_PIN_CFG_NO_GPIO (1 << 31)
struct sh_pfc_pin {
@@ -300,7 +309,7 @@
const u16 *pinmux_data;
unsigned int pinmux_data_size;
- u32 unlock_reg;
+ u32 unlock_reg; /* can be literal address or mask */
};
extern const struct sh_pfc_soc_info emev2_pinmux_info;
@@ -331,6 +340,7 @@
extern const struct sh_pfc_soc_info r8a77980_pinmux_info;
extern const struct sh_pfc_soc_info r8a77990_pinmux_info;
extern const struct sh_pfc_soc_info r8a77995_pinmux_info;
+extern const struct sh_pfc_soc_info r8a779a0_pinmux_info;
extern const struct sh_pfc_soc_info sh7203_pinmux_info;
extern const struct sh_pfc_soc_info sh7264_pinmux_info;
extern const struct sh_pfc_soc_info sh7269_pinmux_info;
@@ -451,9 +461,13 @@
fn(bank, pin, GP_##bank##_##pin, sfx, cfg)
#define PORT_GP_1(bank, pin, fn, sfx) PORT_GP_CFG_1(bank, pin, fn, sfx, 0)
-#define PORT_GP_CFG_4(bank, fn, sfx, cfg) \
+#define PORT_GP_CFG_2(bank, fn, sfx, cfg) \
PORT_GP_CFG_1(bank, 0, fn, sfx, cfg), \
- PORT_GP_CFG_1(bank, 1, fn, sfx, cfg), \
+ PORT_GP_CFG_1(bank, 1, fn, sfx, cfg)
+#define PORT_GP_2(bank, fn, sfx) PORT_GP_CFG_2(bank, fn, sfx, 0)
+
+#define PORT_GP_CFG_4(bank, fn, sfx, cfg) \
+ PORT_GP_CFG_2(bank, fn, sfx, cfg), \
PORT_GP_CFG_1(bank, 2, fn, sfx, cfg), \
PORT_GP_CFG_1(bank, 3, fn, sfx, cfg)
#define PORT_GP_4(bank, fn, sfx) PORT_GP_CFG_4(bank, fn, sfx, 0)
@@ -572,9 +586,13 @@
PORT_GP_CFG_1(bank, 29, fn, sfx, cfg)
#define PORT_GP_30(bank, fn, sfx) PORT_GP_CFG_30(bank, fn, sfx, 0)
-#define PORT_GP_CFG_32(bank, fn, sfx, cfg) \
+#define PORT_GP_CFG_31(bank, fn, sfx, cfg) \
PORT_GP_CFG_30(bank, fn, sfx, cfg), \
- PORT_GP_CFG_1(bank, 30, fn, sfx, cfg), \
+ PORT_GP_CFG_1(bank, 30, fn, sfx, cfg)
+#define PORT_GP_31(bank, fn, sfx) PORT_GP_CFG_31(bank, fn, sfx, 0)
+
+#define PORT_GP_CFG_32(bank, fn, sfx, cfg) \
+ PORT_GP_CFG_31(bank, fn, sfx, cfg), \
PORT_GP_CFG_1(bank, 31, fn, sfx, cfg)
#define PORT_GP_32(bank, fn, sfx) PORT_GP_CFG_32(bank, fn, sfx, 0)
diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.c b/drivers/pinctrl/samsung/pinctrl-exynos.c
index b9ea09f..0cd7f33 100644
--- a/drivers/pinctrl/samsung/pinctrl-exynos.c
+++ b/drivers/pinctrl/samsung/pinctrl-exynos.c
@@ -58,13 +58,13 @@
unsigned long mask;
unsigned long flags;
- spin_lock_irqsave(&bank->slock, flags);
+ raw_spin_lock_irqsave(&bank->slock, flags);
mask = readl(bank->eint_base + reg_mask);
mask |= 1 << irqd->hwirq;
writel(mask, bank->eint_base + reg_mask);
- spin_unlock_irqrestore(&bank->slock, flags);
+ raw_spin_unlock_irqrestore(&bank->slock, flags);
}
static void exynos_irq_ack(struct irq_data *irqd)
@@ -97,13 +97,13 @@
if (irqd_get_trigger_type(irqd) & IRQ_TYPE_LEVEL_MASK)
exynos_irq_ack(irqd);
- spin_lock_irqsave(&bank->slock, flags);
+ raw_spin_lock_irqsave(&bank->slock, flags);
mask = readl(bank->eint_base + reg_mask);
mask &= ~(1 << irqd->hwirq);
writel(mask, bank->eint_base + reg_mask);
- spin_unlock_irqrestore(&bank->slock, flags);
+ raw_spin_unlock_irqrestore(&bank->slock, flags);
}
static int exynos_irq_set_type(struct irq_data *irqd, unsigned int type)
@@ -169,14 +169,14 @@
shift = irqd->hwirq * bank_type->fld_width[PINCFG_TYPE_FUNC];
mask = (1 << bank_type->fld_width[PINCFG_TYPE_FUNC]) - 1;
- spin_lock_irqsave(&bank->slock, flags);
+ raw_spin_lock_irqsave(&bank->slock, flags);
con = readl(bank->pctl_base + reg_con);
con &= ~(mask << shift);
con |= EXYNOS_PIN_FUNC_EINT << shift;
writel(con, bank->pctl_base + reg_con);
- spin_unlock_irqrestore(&bank->slock, flags);
+ raw_spin_unlock_irqrestore(&bank->slock, flags);
return 0;
}
@@ -192,14 +192,14 @@
shift = irqd->hwirq * bank_type->fld_width[PINCFG_TYPE_FUNC];
mask = (1 << bank_type->fld_width[PINCFG_TYPE_FUNC]) - 1;
- spin_lock_irqsave(&bank->slock, flags);
+ raw_spin_lock_irqsave(&bank->slock, flags);
con = readl(bank->pctl_base + reg_con);
con &= ~(mask << shift);
con |= EXYNOS_PIN_FUNC_INPUT << shift;
writel(con, bank->pctl_base + reg_con);
- spin_unlock_irqrestore(&bank->slock, flags);
+ raw_spin_unlock_irqrestore(&bank->slock, flags);
gpiochip_unlock_as_irq(&bank->gpio_chip, irqd->hwirq);
}
diff --git a/drivers/pinctrl/samsung/pinctrl-s3c24xx.c b/drivers/pinctrl/samsung/pinctrl-s3c24xx.c
index 2223ead..00d77d6 100644
--- a/drivers/pinctrl/samsung/pinctrl-s3c24xx.c
+++ b/drivers/pinctrl/samsung/pinctrl-s3c24xx.c
@@ -145,14 +145,14 @@
shift = pin * bank_type->fld_width[PINCFG_TYPE_FUNC];
mask = (1 << bank_type->fld_width[PINCFG_TYPE_FUNC]) - 1;
- spin_lock_irqsave(&bank->slock, flags);
+ raw_spin_lock_irqsave(&bank->slock, flags);
val = readl(reg);
val &= ~(mask << shift);
val |= bank->eint_func << shift;
writel(val, reg);
- spin_unlock_irqrestore(&bank->slock, flags);
+ raw_spin_unlock_irqrestore(&bank->slock, flags);
}
static int s3c24xx_eint_type(struct irq_data *data, unsigned int type)
diff --git a/drivers/pinctrl/samsung/pinctrl-s3c64xx.c b/drivers/pinctrl/samsung/pinctrl-s3c64xx.c
index b8166e3..53e2a641 100644
--- a/drivers/pinctrl/samsung/pinctrl-s3c64xx.c
+++ b/drivers/pinctrl/samsung/pinctrl-s3c64xx.c
@@ -286,14 +286,14 @@
shift = shift * bank_type->fld_width[PINCFG_TYPE_FUNC];
mask = (1 << bank_type->fld_width[PINCFG_TYPE_FUNC]) - 1;
- spin_lock_irqsave(&bank->slock, flags);
+ raw_spin_lock_irqsave(&bank->slock, flags);
val = readl(reg);
val &= ~(mask << shift);
val |= bank->eint_func << shift;
writel(val, reg);
- spin_unlock_irqrestore(&bank->slock, flags);
+ raw_spin_unlock_irqrestore(&bank->slock, flags);
}
/*
diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.c b/drivers/pinctrl/samsung/pinctrl-samsung.c
index 608eb5a..376876b 100644
--- a/drivers/pinctrl/samsung/pinctrl-samsung.c
+++ b/drivers/pinctrl/samsung/pinctrl-samsung.c
@@ -400,14 +400,14 @@
reg += 4;
}
- spin_lock_irqsave(&bank->slock, flags);
+ raw_spin_lock_irqsave(&bank->slock, flags);
data = readl(reg + type->reg_offset[PINCFG_TYPE_FUNC]);
data &= ~(mask << shift);
data |= func->val << shift;
writel(data, reg + type->reg_offset[PINCFG_TYPE_FUNC]);
- spin_unlock_irqrestore(&bank->slock, flags);
+ raw_spin_unlock_irqrestore(&bank->slock, flags);
}
/* enable a specified pinmux by writing to registers */
@@ -451,7 +451,7 @@
width = type->fld_width[cfg_type];
cfg_reg = type->reg_offset[cfg_type];
- spin_lock_irqsave(&bank->slock, flags);
+ raw_spin_lock_irqsave(&bank->slock, flags);
mask = (1 << width) - 1;
shift = pin_offset * width;
@@ -468,7 +468,7 @@
*config = PINCFG_PACK(cfg_type, data);
}
- spin_unlock_irqrestore(&bank->slock, flags);
+ raw_spin_unlock_irqrestore(&bank->slock, flags);
return 0;
}
@@ -561,9 +561,9 @@
struct samsung_pin_bank *bank = gpiochip_get_data(gc);
unsigned long flags;
- spin_lock_irqsave(&bank->slock, flags);
+ raw_spin_lock_irqsave(&bank->slock, flags);
samsung_gpio_set_value(gc, offset, value);
- spin_unlock_irqrestore(&bank->slock, flags);
+ raw_spin_unlock_irqrestore(&bank->slock, flags);
}
/* gpiolib gpio_get callback function */
@@ -626,9 +626,9 @@
unsigned long flags;
int ret;
- spin_lock_irqsave(&bank->slock, flags);
+ raw_spin_lock_irqsave(&bank->slock, flags);
ret = samsung_gpio_set_direction(gc, offset, true);
- spin_unlock_irqrestore(&bank->slock, flags);
+ raw_spin_unlock_irqrestore(&bank->slock, flags);
return ret;
}
@@ -640,10 +640,10 @@
unsigned long flags;
int ret;
- spin_lock_irqsave(&bank->slock, flags);
+ raw_spin_lock_irqsave(&bank->slock, flags);
samsung_gpio_set_value(gc, offset, value);
ret = samsung_gpio_set_direction(gc, offset, false);
- spin_unlock_irqrestore(&bank->slock, flags);
+ raw_spin_unlock_irqrestore(&bank->slock, flags);
return ret;
}
@@ -1057,7 +1057,7 @@
bank->eint_offset = bdata->eint_offset;
bank->name = bdata->name;
- spin_lock_init(&bank->slock);
+ raw_spin_lock_init(&bank->slock);
bank->drvdata = d;
bank->pin_base = d->nr_pins;
d->nr_pins += bank->nr_pins;
diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.h b/drivers/pinctrl/samsung/pinctrl-samsung.h
index 379f34a..de44f8e 100644
--- a/drivers/pinctrl/samsung/pinctrl-samsung.h
+++ b/drivers/pinctrl/samsung/pinctrl-samsung.h
@@ -171,7 +171,7 @@
struct gpio_chip gpio_chip;
struct pinctrl_gpio_range grange;
struct exynos_irq_chip *irq_chip;
- spinlock_t slock;
+ raw_spinlock_t slock;
u32 pm_save[PINCFG_TYPE_NUM + 1]; /* +1 to handle double CON registers*/
};
diff --git a/drivers/pinctrl/sirf/Makefile b/drivers/pinctrl/sirf/Makefile
deleted file mode 100644
index 1ab0742..0000000
--- a/drivers/pinctrl/sirf/Makefile
+++ /dev/null
@@ -1,7 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0-only
-# CSR SiRFsoc pinmux support
-
-obj-y += pinctrl-sirf.o
-obj-y += pinctrl-prima2.o
-obj-y += pinctrl-atlas6.o
-obj-y += pinctrl-atlas7.o
diff --git a/drivers/pinctrl/sirf/pinctrl-atlas6.c b/drivers/pinctrl/sirf/pinctrl-atlas6.c
deleted file mode 100644
index ab35d59..0000000
--- a/drivers/pinctrl/sirf/pinctrl-atlas6.c
+++ /dev/null
@@ -1,1137 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-/*
- * pinctrl pads, groups, functions for CSR SiRFatlasVI
- *
- * Copyright (c) 2011 - 2014 Cambridge Silicon Radio Limited, a CSR plc group
- * company.
- */
-
-#include <linux/pinctrl/pinctrl.h>
-#include <linux/bitops.h>
-
-#include "pinctrl-sirf.h"
-
-/*
- * pad list for the pinmux subsystem
- * refer to atlasVI_io_table_v0.93.xls
- */
-static const struct pinctrl_pin_desc sirfsoc_pads[] = {
- PINCTRL_PIN(0, "gpio0-0"),
- PINCTRL_PIN(1, "gpio0-1"),
- PINCTRL_PIN(2, "gpio0-2"),
- PINCTRL_PIN(3, "gpio0-3"),
- PINCTRL_PIN(4, "pwm0"),
- PINCTRL_PIN(5, "pwm1"),
- PINCTRL_PIN(6, "pwm2"),
- PINCTRL_PIN(7, "pwm3"),
- PINCTRL_PIN(8, "warm_rst_b"),
- PINCTRL_PIN(9, "odo_0"),
- PINCTRL_PIN(10, "odo_1"),
- PINCTRL_PIN(11, "dr_dir"),
- PINCTRL_PIN(12, "rts_0"),
- PINCTRL_PIN(13, "scl_1"),
- PINCTRL_PIN(14, "ntrst"),
- PINCTRL_PIN(15, "sda_1"),
- PINCTRL_PIN(16, "x_ldd[16]"),
- PINCTRL_PIN(17, "x_ldd[17]"),
- PINCTRL_PIN(18, "x_ldd[18]"),
- PINCTRL_PIN(19, "x_ldd[19]"),
- PINCTRL_PIN(20, "x_ldd[20]"),
- PINCTRL_PIN(21, "x_ldd[21]"),
- PINCTRL_PIN(22, "x_ldd[22]"),
- PINCTRL_PIN(23, "x_ldd[23]"),
- PINCTRL_PIN(24, "gps_sgn"),
- PINCTRL_PIN(25, "gps_mag"),
- PINCTRL_PIN(26, "gps_clk"),
- PINCTRL_PIN(27, "sd_cd_b_2"),
- PINCTRL_PIN(28, "sd_vcc_on_2"),
- PINCTRL_PIN(29, "sd_wp_b_2"),
- PINCTRL_PIN(30, "sd_clk_3"),
- PINCTRL_PIN(31, "sd_cmd_3"),
-
- PINCTRL_PIN(32, "x_sd_dat_3[0]"),
- PINCTRL_PIN(33, "x_sd_dat_3[1]"),
- PINCTRL_PIN(34, "x_sd_dat_3[2]"),
- PINCTRL_PIN(35, "x_sd_dat_3[3]"),
- PINCTRL_PIN(36, "usb_clk"),
- PINCTRL_PIN(37, "usb_dir"),
- PINCTRL_PIN(38, "usb_nxt"),
- PINCTRL_PIN(39, "usb_stp"),
- PINCTRL_PIN(40, "usb_dat[7]"),
- PINCTRL_PIN(41, "usb_dat[6]"),
- PINCTRL_PIN(42, "x_cko_1"),
- PINCTRL_PIN(43, "spi_clk_1"),
- PINCTRL_PIN(44, "spi_dout_1"),
- PINCTRL_PIN(45, "spi_din_1"),
- PINCTRL_PIN(46, "spi_en_1"),
- PINCTRL_PIN(47, "x_txd_1"),
- PINCTRL_PIN(48, "x_txd_2"),
- PINCTRL_PIN(49, "x_rxd_1"),
- PINCTRL_PIN(50, "x_rxd_2"),
- PINCTRL_PIN(51, "x_usclk_0"),
- PINCTRL_PIN(52, "x_utxd_0"),
- PINCTRL_PIN(53, "x_urxd_0"),
- PINCTRL_PIN(54, "x_utfs_0"),
- PINCTRL_PIN(55, "x_urfs_0"),
- PINCTRL_PIN(56, "usb_dat5"),
- PINCTRL_PIN(57, "usb_dat4"),
- PINCTRL_PIN(58, "usb_dat3"),
- PINCTRL_PIN(59, "usb_dat2"),
- PINCTRL_PIN(60, "usb_dat1"),
- PINCTRL_PIN(61, "usb_dat0"),
- PINCTRL_PIN(62, "x_ldd[14]"),
- PINCTRL_PIN(63, "x_ldd[15]"),
-
- PINCTRL_PIN(64, "x_gps_gpio"),
- PINCTRL_PIN(65, "x_ldd[13]"),
- PINCTRL_PIN(66, "x_df_we_b"),
- PINCTRL_PIN(67, "x_df_re_b"),
- PINCTRL_PIN(68, "x_txd_0"),
- PINCTRL_PIN(69, "x_rxd_0"),
- PINCTRL_PIN(70, "x_l_lck"),
- PINCTRL_PIN(71, "x_l_fck"),
- PINCTRL_PIN(72, "x_l_de"),
- PINCTRL_PIN(73, "x_ldd[0]"),
- PINCTRL_PIN(74, "x_ldd[1]"),
- PINCTRL_PIN(75, "x_ldd[2]"),
- PINCTRL_PIN(76, "x_ldd[3]"),
- PINCTRL_PIN(77, "x_ldd[4]"),
- PINCTRL_PIN(78, "x_cko_0"),
- PINCTRL_PIN(79, "x_ldd[5]"),
- PINCTRL_PIN(80, "x_ldd[6]"),
- PINCTRL_PIN(81, "x_ldd[7]"),
- PINCTRL_PIN(82, "x_ldd[8]"),
- PINCTRL_PIN(83, "x_ldd[9]"),
- PINCTRL_PIN(84, "x_ldd[10]"),
- PINCTRL_PIN(85, "x_ldd[11]"),
- PINCTRL_PIN(86, "x_ldd[12]"),
- PINCTRL_PIN(87, "x_vip_vsync"),
- PINCTRL_PIN(88, "x_vip_hsync"),
- PINCTRL_PIN(89, "x_vip_pxclk"),
- PINCTRL_PIN(90, "x_sda_0"),
- PINCTRL_PIN(91, "x_scl_0"),
- PINCTRL_PIN(92, "x_df_ry_by"),
- PINCTRL_PIN(93, "x_df_cs_b[1]"),
- PINCTRL_PIN(94, "x_df_cs_b[0]"),
- PINCTRL_PIN(95, "x_l_pclk"),
-
- PINCTRL_PIN(96, "x_df_dqs"),
- PINCTRL_PIN(97, "x_df_wp_b"),
- PINCTRL_PIN(98, "ac97_sync"),
- PINCTRL_PIN(99, "ac97_bit_clk "),
- PINCTRL_PIN(100, "ac97_dout"),
- PINCTRL_PIN(101, "ac97_din"),
- PINCTRL_PIN(102, "x_rtc_io"),
-
- PINCTRL_PIN(103, "x_usb1_dp"),
- PINCTRL_PIN(104, "x_usb1_dn"),
-};
-
-static const struct sirfsoc_muxmask lcd_16bits_sirfsoc_muxmask[] = {
- {
- .group = 1,
- .mask = BIT(30) | BIT(31),
- }, {
- .group = 2,
- .mask = BIT(1) | BIT(6) | BIT(7) | BIT(8) | BIT(9) |
- BIT(10) | BIT(11) | BIT(12) | BIT(13) | BIT(15) |
- BIT(16) | BIT(17) | BIT(18) | BIT(19) |
- BIT(20) | BIT(21) | BIT(22) | BIT(31),
- },
-};
-
-static const struct sirfsoc_padmux lcd_16bits_padmux = {
- .muxmask_counts = ARRAY_SIZE(lcd_16bits_sirfsoc_muxmask),
- .muxmask = lcd_16bits_sirfsoc_muxmask,
- .ctrlreg = SIRFSOC_RSC_PIN_MUX,
- .funcmask = BIT(4),
- .funcval = 0,
-};
-
-static const unsigned lcd_16bits_pins[] = { 62, 63, 65, 70, 71, 72, 73, 74, 75,
- 76, 77, 79, 80, 81, 82, 83, 84, 85, 86, 95 };
-
-static const struct sirfsoc_muxmask lcd_18bits_muxmask[] = {
- {
- .group = 2,
- .mask = BIT(1) | BIT(6) | BIT(7) | BIT(8) | BIT(9) |
- BIT(10) | BIT(11) | BIT(12) | BIT(13) | BIT(15) |
- BIT(16) | BIT(17) | BIT(18) | BIT(19) |
- BIT(20) | BIT(21) | BIT(22) | BIT(31),
- }, {
- .group = 1,
- .mask = BIT(30) | BIT(31),
- }, {
- .group = 0,
- .mask = BIT(16) | BIT(17),
- },
-};
-
-static const struct sirfsoc_padmux lcd_18bits_padmux = {
- .muxmask_counts = ARRAY_SIZE(lcd_18bits_muxmask),
- .muxmask = lcd_18bits_muxmask,
- .ctrlreg = SIRFSOC_RSC_PIN_MUX,
- .funcmask = BIT(4) | BIT(15),
- .funcval = 0,
-};
-
-static const unsigned lcd_18bits_pins[] = { 16, 17, 62, 63, 65, 70, 71, 72, 73,
- 74, 75, 76, 77, 79, 80, 81, 82, 83, 84, 85, 86, 95 };
-
-static const struct sirfsoc_muxmask lcd_24bits_muxmask[] = {
- {
- .group = 2,
- .mask = BIT(1) | BIT(6) | BIT(7) | BIT(8) | BIT(9) |
- BIT(10) | BIT(11) | BIT(12) | BIT(13) | BIT(15) |
- BIT(16) | BIT(17) | BIT(18) | BIT(19) |
- BIT(20) | BIT(21) | BIT(22) | BIT(31),
- }, {
- .group = 1,
- .mask = BIT(30) | BIT(31),
- }, {
- .group = 0,
- .mask = BIT(16) | BIT(17) | BIT(18) | BIT(19) | BIT(20) |
- BIT(21) | BIT(22) | BIT(23),
- },
-};
-
-static const struct sirfsoc_padmux lcd_24bits_padmux = {
- .muxmask_counts = ARRAY_SIZE(lcd_24bits_muxmask),
- .muxmask = lcd_24bits_muxmask,
- .ctrlreg = SIRFSOC_RSC_PIN_MUX,
- .funcmask = BIT(4) | BIT(15),
- .funcval = 0,
-};
-
-static const unsigned lcd_24bits_pins[] = { 16, 17, 18, 19, 20, 21, 22, 23, 62,
- 63, 65, 70, 71, 72, 73, 74, 75, 76, 77, 79, 80, 81, 82, 83, 84,
- 85, 86, 95};
-
-static const struct sirfsoc_muxmask lcdrom_muxmask[] = {
- {
- .group = 2,
- .mask = BIT(1) | BIT(6) | BIT(7) | BIT(8) | BIT(9) | BIT(10) |
- BIT(11) | BIT(12) | BIT(13) | BIT(15) | BIT(16) |
- BIT(17) | BIT(18) | BIT(19) |
- BIT(20) | BIT(21) | BIT(22) | BIT(31),
- }, {
- .group = 1,
- .mask = BIT(30) | BIT(31),
- }, {
- .group = 0,
- .mask = BIT(8),
- },
-};
-
-static const struct sirfsoc_padmux lcdrom_padmux = {
- .muxmask_counts = ARRAY_SIZE(lcdrom_muxmask),
- .muxmask = lcdrom_muxmask,
- .ctrlreg = SIRFSOC_RSC_PIN_MUX,
- .funcmask = BIT(4),
- .funcval = BIT(4),
-};
-
-static const unsigned lcdrom_pins[] = { 8, 62, 63, 65, 70, 71, 72, 73, 74, 75,
- 76, 77, 79, 80, 81, 82, 83, 84, 85, 86, 95};
-
-static const struct sirfsoc_muxmask uart0_muxmask[] = {
- {
- .group = 0,
- .mask = BIT(12),
- }, {
- .group = 1,
- .mask = BIT(23),
- }, {
- .group = 2,
- .mask = BIT(4) | BIT(5),
- },
-};
-
-static const struct sirfsoc_padmux uart0_padmux = {
- .muxmask_counts = ARRAY_SIZE(uart0_muxmask),
- .muxmask = uart0_muxmask,
- .ctrlreg = SIRFSOC_RSC_PIN_MUX,
- .funcmask = BIT(9),
- .funcval = BIT(9),
-};
-
-static const unsigned uart0_pins[] = { 12, 55, 68, 69 };
-
-static const struct sirfsoc_muxmask uart0_nostreamctrl_muxmask[] = {
- {
- .group = 2,
- .mask = BIT(4) | BIT(5),
- },
-};
-
-static const struct sirfsoc_padmux uart0_nostreamctrl_padmux = {
- .muxmask_counts = ARRAY_SIZE(uart0_nostreamctrl_muxmask),
- .muxmask = uart0_nostreamctrl_muxmask,
-};
-
-static const unsigned uart0_nostreamctrl_pins[] = { 68, 69 };
-
-static const struct sirfsoc_muxmask uart1_muxmask[] = {
- {
- .group = 1,
- .mask = BIT(15) | BIT(17),
- },
-};
-
-static const struct sirfsoc_padmux uart1_padmux = {
- .muxmask_counts = ARRAY_SIZE(uart1_muxmask),
- .muxmask = uart1_muxmask,
-};
-
-static const unsigned uart1_pins[] = { 47, 49 };
-
-static const struct sirfsoc_muxmask uart2_muxmask[] = {
- {
- .group = 0,
- .mask = BIT(10) | BIT(14),
- }, {
- .group = 1,
- .mask = BIT(16) | BIT(18),
- },
-};
-
-static const struct sirfsoc_padmux uart2_padmux = {
- .muxmask_counts = ARRAY_SIZE(uart2_muxmask),
- .muxmask = uart2_muxmask,
- .ctrlreg = SIRFSOC_RSC_PIN_MUX,
- .funcmask = BIT(10),
- .funcval = BIT(10),
-};
-
-static const unsigned uart2_pins[] = { 10, 14, 48, 50 };
-
-static const struct sirfsoc_muxmask uart2_nostreamctrl_muxmask[] = {
- {
- .group = 1,
- .mask = BIT(16) | BIT(18),
- },
-};
-
-static const struct sirfsoc_padmux uart2_nostreamctrl_padmux = {
- .muxmask_counts = ARRAY_SIZE(uart2_nostreamctrl_muxmask),
- .muxmask = uart2_nostreamctrl_muxmask,
-};
-
-static const unsigned uart2_nostreamctrl_pins[] = { 48, 50 };
-
-static const struct sirfsoc_muxmask sdmmc3_muxmask[] = {
- {
- .group = 0,
- .mask = BIT(30) | BIT(31),
- }, {
- .group = 1,
- .mask = BIT(0) | BIT(1) | BIT(2) | BIT(3),
- },
-};
-
-static const struct sirfsoc_padmux sdmmc3_padmux = {
- .muxmask_counts = ARRAY_SIZE(sdmmc3_muxmask),
- .muxmask = sdmmc3_muxmask,
- .ctrlreg = SIRFSOC_RSC_PIN_MUX,
- .funcmask = BIT(7),
- .funcval = 0,
-};
-
-static const unsigned sdmmc3_pins[] = { 30, 31, 32, 33, 34, 35 };
-
-static const struct sirfsoc_muxmask spi0_muxmask[] = {
- {
- .group = 0,
- .mask = BIT(30),
- }, {
- .group = 1,
- .mask = BIT(0) | BIT(2) | BIT(3),
- },
-};
-
-static const struct sirfsoc_padmux spi0_padmux = {
- .muxmask_counts = ARRAY_SIZE(spi0_muxmask),
- .muxmask = spi0_muxmask,
- .ctrlreg = SIRFSOC_RSC_PIN_MUX,
- .funcmask = BIT(7),
- .funcval = BIT(7),
-};
-
-static const unsigned spi0_pins[] = { 30, 32, 34, 35 };
-
-static const struct sirfsoc_muxmask cko1_muxmask[] = {
- {
- .group = 1,
- .mask = BIT(10),
- },
-};
-
-static const struct sirfsoc_padmux cko1_padmux = {
- .muxmask_counts = ARRAY_SIZE(cko1_muxmask),
- .muxmask = cko1_muxmask,
- .ctrlreg = SIRFSOC_RSC_PIN_MUX,
- .funcmask = BIT(3),
- .funcval = 0,
-};
-
-static const unsigned cko1_pins[] = { 42 };
-
-static const struct sirfsoc_muxmask i2s_mclk_muxmask[] = {
- {
- .group = 1,
- .mask = BIT(10),
- },
-};
-
-static const struct sirfsoc_padmux i2s_mclk_padmux = {
- .muxmask_counts = ARRAY_SIZE(i2s_mclk_muxmask),
- .muxmask = i2s_mclk_muxmask,
- .ctrlreg = SIRFSOC_RSC_PIN_MUX,
- .funcmask = BIT(3),
- .funcval = BIT(3),
-};
-
-static const unsigned i2s_mclk_pins[] = { 42 };
-
-static const struct sirfsoc_muxmask i2s_ext_clk_input_muxmask[] = {
- {
- .group = 1,
- .mask = BIT(19),
- },
-};
-
-static const struct sirfsoc_padmux i2s_ext_clk_input_padmux = {
- .muxmask_counts = ARRAY_SIZE(i2s_ext_clk_input_muxmask),
- .muxmask = i2s_ext_clk_input_muxmask,
- .ctrlreg = SIRFSOC_RSC_PIN_MUX,
- .funcmask = BIT(2),
- .funcval = BIT(2),
-};
-
-static const unsigned i2s_ext_clk_input_pins[] = { 51 };
-
-static const struct sirfsoc_muxmask i2s_muxmask[] = {
- {
- .group = 3,
- .mask = BIT(2) | BIT(3) | BIT(4) | BIT(5),
- },
-};
-
-static const struct sirfsoc_padmux i2s_padmux = {
- .muxmask_counts = ARRAY_SIZE(i2s_muxmask),
- .muxmask = i2s_muxmask,
- .ctrlreg = SIRFSOC_RSC_PIN_MUX,
-};
-
-static const unsigned i2s_pins[] = { 98, 99, 100, 101 };
-
-static const struct sirfsoc_muxmask i2s_no_din_muxmask[] = {
- {
- .group = 3,
- .mask = BIT(2) | BIT(3) | BIT(4),
- },
-};
-
-static const struct sirfsoc_padmux i2s_no_din_padmux = {
- .muxmask_counts = ARRAY_SIZE(i2s_no_din_muxmask),
- .muxmask = i2s_no_din_muxmask,
- .ctrlreg = SIRFSOC_RSC_PIN_MUX,
-};
-
-static const unsigned i2s_no_din_pins[] = { 98, 99, 100 };
-
-static const struct sirfsoc_muxmask i2s_6chn_muxmask[] = {
- {
- .group = 3,
- .mask = BIT(2) | BIT(3) | BIT(4) | BIT(5),
- },
-};
-
-static const struct sirfsoc_padmux i2s_6chn_padmux = {
- .muxmask_counts = ARRAY_SIZE(i2s_6chn_muxmask),
- .muxmask = i2s_6chn_muxmask,
- .ctrlreg = SIRFSOC_RSC_PIN_MUX,
- .funcmask = BIT(1) | BIT(9),
- .funcval = BIT(1) | BIT(9),
-};
-
-static const unsigned i2s_6chn_pins[] = { 52, 55, 98, 99, 100, 101 };
-
-static const struct sirfsoc_muxmask ac97_muxmask[] = {
- {
- .group = 3,
- .mask = BIT(2) | BIT(3) | BIT(4) | BIT(5),
- },
-};
-
-static const struct sirfsoc_padmux ac97_padmux = {
- .muxmask_counts = ARRAY_SIZE(ac97_muxmask),
- .muxmask = ac97_muxmask,
-};
-
-static const unsigned ac97_pins[] = { 98, 99, 100, 101 };
-
-static const struct sirfsoc_muxmask spi1_muxmask[] = {
- {
- .group = 1,
- .mask = BIT(11) | BIT(12) | BIT(13) | BIT(14),
- },
-};
-
-static const struct sirfsoc_padmux spi1_padmux = {
- .muxmask_counts = ARRAY_SIZE(spi1_muxmask),
- .muxmask = spi1_muxmask,
- .ctrlreg = SIRFSOC_RSC_PIN_MUX,
- .funcmask = BIT(16),
- .funcval = 0,
-};
-
-static const unsigned spi1_pins[] = { 43, 44, 45, 46 };
-
-static const struct sirfsoc_muxmask sdmmc1_muxmask[] = {
- {
- .group = 2,
- .mask = BIT(2) | BIT(3),
- },
-};
-
-static const struct sirfsoc_padmux sdmmc1_padmux = {
- .muxmask_counts = ARRAY_SIZE(sdmmc1_muxmask),
- .muxmask = sdmmc1_muxmask,
- .ctrlreg = SIRFSOC_RSC_PIN_MUX,
- .funcmask = BIT(5),
- .funcval = BIT(5),
-};
-
-static const unsigned sdmmc1_pins[] = { 66, 67 };
-
-static const struct sirfsoc_muxmask gps_muxmask[] = {
- {
- .group = 0,
- .mask = BIT(24) | BIT(25) | BIT(26),
- },
-};
-
-static const struct sirfsoc_padmux gps_padmux = {
- .muxmask_counts = ARRAY_SIZE(gps_muxmask),
- .muxmask = gps_muxmask,
- .ctrlreg = SIRFSOC_RSC_PIN_MUX,
- .funcmask = BIT(13),
- .funcval = 0,
-};
-
-static const unsigned gps_pins[] = { 24, 25, 26 };
-
-static const struct sirfsoc_muxmask sdmmc5_muxmask[] = {
- {
- .group = 0,
- .mask = BIT(24) | BIT(25) | BIT(26),
- },
-};
-
-static const struct sirfsoc_padmux sdmmc5_padmux = {
- .muxmask_counts = ARRAY_SIZE(sdmmc5_muxmask),
- .muxmask = sdmmc5_muxmask,
- .ctrlreg = SIRFSOC_RSC_PIN_MUX,
- .funcmask = BIT(13),
- .funcval = BIT(13),
-};
-
-static const unsigned sdmmc5_pins[] = { 24, 25, 26 };
-
-static const struct sirfsoc_muxmask usp0_muxmask[] = {
- {
- .group = 1,
- .mask = BIT(19) | BIT(20) | BIT(21) | BIT(22) | BIT(23),
- },
-};
-
-static const struct sirfsoc_padmux usp0_padmux = {
- .muxmask_counts = ARRAY_SIZE(usp0_muxmask),
- .muxmask = usp0_muxmask,
- .ctrlreg = SIRFSOC_RSC_PIN_MUX,
- .funcmask = BIT(1) | BIT(2) | BIT(9),
- .funcval = 0,
-};
-
-static const unsigned usp0_pins[] = { 51, 52, 53, 54, 55 };
-
-static const struct sirfsoc_muxmask usp0_only_utfs_muxmask[] = {
- {
- .group = 1,
- .mask = BIT(19) | BIT(20) | BIT(21) | BIT(22),
- },
-};
-
-static const struct sirfsoc_padmux usp0_only_utfs_padmux = {
- .muxmask_counts = ARRAY_SIZE(usp0_only_utfs_muxmask),
- .muxmask = usp0_only_utfs_muxmask,
- .ctrlreg = SIRFSOC_RSC_PIN_MUX,
- .funcmask = BIT(1) | BIT(2) | BIT(6),
- .funcval = 0,
-};
-
-static const unsigned usp0_only_utfs_pins[] = { 51, 52, 53, 54 };
-
-static const struct sirfsoc_muxmask usp0_only_urfs_muxmask[] = {
- {
- .group = 1,
- .mask = BIT(19) | BIT(20) | BIT(21) | BIT(23),
- },
-};
-
-static const struct sirfsoc_padmux usp0_only_urfs_padmux = {
- .muxmask_counts = ARRAY_SIZE(usp0_only_urfs_muxmask),
- .muxmask = usp0_only_urfs_muxmask,
- .ctrlreg = SIRFSOC_RSC_PIN_MUX,
- .funcmask = BIT(1) | BIT(2) | BIT(9),
- .funcval = 0,
-};
-
-static const unsigned usp0_only_urfs_pins[] = { 51, 52, 53, 55 };
-
-static const struct sirfsoc_muxmask usp0_uart_nostreamctrl_muxmask[] = {
- {
- .group = 1,
- .mask = BIT(20) | BIT(21),
- },
-};
-
-static const struct sirfsoc_padmux usp0_uart_nostreamctrl_padmux = {
- .muxmask_counts = ARRAY_SIZE(usp0_uart_nostreamctrl_muxmask),
- .muxmask = usp0_uart_nostreamctrl_muxmask,
-};
-
-static const unsigned usp0_uart_nostreamctrl_pins[] = { 52, 53 };
-static const struct sirfsoc_muxmask usp1_muxmask[] = {
- {
- .group = 0,
- .mask = BIT(15),
- }, {
- .group = 1,
- .mask = BIT(11) | BIT(12) | BIT(13) | BIT(14),
- },
-};
-
-static const struct sirfsoc_padmux usp1_padmux = {
- .muxmask_counts = ARRAY_SIZE(usp1_muxmask),
- .muxmask = usp1_muxmask,
- .ctrlreg = SIRFSOC_RSC_PIN_MUX,
- .funcmask = BIT(16),
- .funcval = BIT(16),
-};
-
-static const unsigned usp1_pins[] = { 15, 43, 44, 45, 46 };
-
-static const struct sirfsoc_muxmask usp1_uart_nostreamctrl_muxmask[] = {
- {
- .group = 1,
- .mask = BIT(12) | BIT(13),
- },
-};
-
-static const struct sirfsoc_padmux usp1_uart_nostreamctrl_padmux = {
- .muxmask_counts = ARRAY_SIZE(usp1_uart_nostreamctrl_muxmask),
- .muxmask = usp1_uart_nostreamctrl_muxmask,
- .ctrlreg = SIRFSOC_RSC_PIN_MUX,
- .funcmask = BIT(16),
- .funcval = BIT(16),
-};
-
-static const unsigned usp1_uart_nostreamctrl_pins[] = { 44, 45 };
-
-static const struct sirfsoc_muxmask nand_muxmask[] = {
- {
- .group = 2,
- .mask = BIT(2) | BIT(3) | BIT(28) | BIT(29) | BIT(30),
- }, {
- .group = 3,
- .mask = BIT(0) | BIT(1),
- },
-};
-
-static const struct sirfsoc_padmux nand_padmux = {
- .muxmask_counts = ARRAY_SIZE(nand_muxmask),
- .muxmask = nand_muxmask,
- .ctrlreg = SIRFSOC_RSC_PIN_MUX,
- .funcmask = BIT(5) | BIT(19),
- .funcval = 0,
-};
-
-static const unsigned nand_pins[] = { 66, 67, 92, 93, 94, 96, 97 };
-
-static const struct sirfsoc_muxmask sdmmc0_muxmask[] = {
- {
- .group = 3,
- .mask = BIT(1),
- },
-};
-
-static const struct sirfsoc_padmux sdmmc0_padmux = {
- .muxmask_counts = ARRAY_SIZE(sdmmc0_muxmask),
- .muxmask = sdmmc0_muxmask,
- .ctrlreg = SIRFSOC_RSC_PIN_MUX,
- .funcmask = BIT(5) | BIT(19),
- .funcval = BIT(19),
-};
-
-static const unsigned sdmmc0_pins[] = { 97 };
-
-static const struct sirfsoc_muxmask sdmmc2_muxmask[] = {
- {
- .group = 0,
- .mask = BIT(27) | BIT(28) | BIT(29),
- },
-};
-
-static const struct sirfsoc_padmux sdmmc2_padmux = {
- .muxmask_counts = ARRAY_SIZE(sdmmc2_muxmask),
- .muxmask = sdmmc2_muxmask,
- .ctrlreg = SIRFSOC_RSC_PIN_MUX,
- .funcmask = BIT(11),
- .funcval = 0,
-};
-
-static const unsigned sdmmc2_pins[] = { 27, 28, 29 };
-
-static const struct sirfsoc_muxmask sdmmc2_nowp_muxmask[] = {
- {
- .group = 0,
- .mask = BIT(27) | BIT(28),
- },
-};
-
-static const struct sirfsoc_padmux sdmmc2_nowp_padmux = {
- .muxmask_counts = ARRAY_SIZE(sdmmc2_nowp_muxmask),
- .muxmask = sdmmc2_nowp_muxmask,
- .ctrlreg = SIRFSOC_RSC_PIN_MUX,
- .funcmask = BIT(11),
- .funcval = 0,
-};
-
-static const unsigned sdmmc2_nowp_pins[] = { 27, 28 };
-
-static const struct sirfsoc_muxmask cko0_muxmask[] = {
- {
- .group = 2,
- .mask = BIT(14),
- },
-};
-
-static const struct sirfsoc_padmux cko0_padmux = {
- .muxmask_counts = ARRAY_SIZE(cko0_muxmask),
- .muxmask = cko0_muxmask,
-};
-
-static const unsigned cko0_pins[] = { 78 };
-
-static const struct sirfsoc_muxmask vip_muxmask[] = {
- {
- .group = 1,
- .mask = BIT(4) | BIT(5) | BIT(6) | BIT(8) | BIT(9)
- | BIT(24) | BIT(25) | BIT(26) | BIT(27) | BIT(28) |
- BIT(29),
- },
-};
-
-static const struct sirfsoc_padmux vip_padmux = {
- .muxmask_counts = ARRAY_SIZE(vip_muxmask),
- .muxmask = vip_muxmask,
- .ctrlreg = SIRFSOC_RSC_PIN_MUX,
- .funcmask = BIT(18),
- .funcval = BIT(18),
-};
-
-static const unsigned vip_pins[] = { 36, 37, 38, 40, 41, 56, 57, 58, 59,
- 60, 61 };
-
-static const struct sirfsoc_muxmask vip_noupli_muxmask[] = {
- {
- .group = 0,
- .mask = BIT(16) | BIT(17) | BIT(18) | BIT(19) | BIT(20)
- | BIT(21) | BIT(22) | BIT(23),
- }, {
- .group = 2,
- .mask = BIT(23) | BIT(24) | BIT(25),
- },
-};
-
-static const struct sirfsoc_padmux vip_noupli_padmux = {
- .muxmask_counts = ARRAY_SIZE(vip_noupli_muxmask),
- .muxmask = vip_noupli_muxmask,
- .ctrlreg = SIRFSOC_RSC_PIN_MUX,
- .funcmask = BIT(15),
- .funcval = BIT(15),
-};
-
-static const unsigned vip_noupli_pins[] = { 16, 17, 18, 19, 20, 21, 22, 23,
- 87, 88, 89 };
-
-static const struct sirfsoc_muxmask i2c0_muxmask[] = {
- {
- .group = 2,
- .mask = BIT(26) | BIT(27),
- },
-};
-
-static const struct sirfsoc_padmux i2c0_padmux = {
- .muxmask_counts = ARRAY_SIZE(i2c0_muxmask),
- .muxmask = i2c0_muxmask,
-};
-
-static const unsigned i2c0_pins[] = { 90, 91 };
-
-static const struct sirfsoc_muxmask i2c1_muxmask[] = {
- {
- .group = 0,
- .mask = BIT(13) | BIT(15),
- },
-};
-
-static const struct sirfsoc_padmux i2c1_padmux = {
- .muxmask_counts = ARRAY_SIZE(i2c1_muxmask),
- .muxmask = i2c1_muxmask,
- .ctrlreg = SIRFSOC_RSC_PIN_MUX,
- .funcmask = BIT(16),
- .funcval = 0,
-};
-
-static const unsigned i2c1_pins[] = { 13, 15 };
-
-static const struct sirfsoc_muxmask pwm0_muxmask[] = {
- {
- .group = 0,
- .mask = BIT(4),
- },
-};
-
-static const struct sirfsoc_padmux pwm0_padmux = {
- .muxmask_counts = ARRAY_SIZE(pwm0_muxmask),
- .muxmask = pwm0_muxmask,
- .ctrlreg = SIRFSOC_RSC_PIN_MUX,
- .funcmask = BIT(12),
- .funcval = 0,
-};
-
-static const unsigned pwm0_pins[] = { 4 };
-
-static const struct sirfsoc_muxmask pwm1_muxmask[] = {
- {
- .group = 0,
- .mask = BIT(5),
- },
-};
-
-static const struct sirfsoc_padmux pwm1_padmux = {
- .muxmask_counts = ARRAY_SIZE(pwm1_muxmask),
- .muxmask = pwm1_muxmask,
-};
-
-static const unsigned pwm1_pins[] = { 5 };
-
-static const struct sirfsoc_muxmask pwm2_muxmask[] = {
- {
- .group = 0,
- .mask = BIT(6),
- },
-};
-
-static const struct sirfsoc_padmux pwm2_padmux = {
- .muxmask_counts = ARRAY_SIZE(pwm2_muxmask),
- .muxmask = pwm2_muxmask,
-};
-
-static const unsigned pwm2_pins[] = { 6 };
-
-static const struct sirfsoc_muxmask pwm3_muxmask[] = {
- {
- .group = 0,
- .mask = BIT(7),
- },
-};
-
-static const struct sirfsoc_padmux pwm3_padmux = {
- .muxmask_counts = ARRAY_SIZE(pwm3_muxmask),
- .muxmask = pwm3_muxmask,
-};
-
-static const unsigned pwm3_pins[] = { 7 };
-
-static const struct sirfsoc_muxmask pwm4_muxmask[] = {
- {
- .group = 2,
- .mask = BIT(14),
- },
-};
-
-static const struct sirfsoc_padmux pwm4_padmux = {
- .muxmask_counts = ARRAY_SIZE(pwm4_muxmask),
- .muxmask = pwm4_muxmask,
-};
-
-static const unsigned pwm4_pins[] = { 78 };
-
-static const struct sirfsoc_muxmask warm_rst_muxmask[] = {
- {
- .group = 0,
- .mask = BIT(8),
- },
-};
-
-static const struct sirfsoc_padmux warm_rst_padmux = {
- .muxmask_counts = ARRAY_SIZE(warm_rst_muxmask),
- .muxmask = warm_rst_muxmask,
- .ctrlreg = SIRFSOC_RSC_PIN_MUX,
- .funcmask = BIT(4),
- .funcval = 0,
-};
-
-static const unsigned warm_rst_pins[] = { 8 };
-
-static const struct sirfsoc_muxmask usb0_upli_drvbus_muxmask[] = {
- {
- .group = 1,
- .mask = BIT(4) | BIT(5) | BIT(6) | BIT(7) | BIT(8)
- | BIT(9) | BIT(24) | BIT(25) | BIT(26) |
- BIT(27) | BIT(28) | BIT(29),
- },
-};
-static const struct sirfsoc_padmux usb0_upli_drvbus_padmux = {
- .muxmask_counts = ARRAY_SIZE(usb0_upli_drvbus_muxmask),
- .muxmask = usb0_upli_drvbus_muxmask,
- .ctrlreg = SIRFSOC_RSC_PIN_MUX,
- .funcmask = BIT(18),
- .funcval = 0,
-};
-
-static const unsigned usb0_upli_drvbus_pins[] = { 36, 37, 38, 39, 40,
- 41, 56, 57, 58, 59, 60, 61 };
-
-static const struct sirfsoc_muxmask usb1_utmi_drvbus_muxmask[] = {
- {
- .group = 0,
- .mask = BIT(28),
- },
-};
-
-static const struct sirfsoc_padmux usb1_utmi_drvbus_padmux = {
- .muxmask_counts = ARRAY_SIZE(usb1_utmi_drvbus_muxmask),
- .muxmask = usb1_utmi_drvbus_muxmask,
- .ctrlreg = SIRFSOC_RSC_PIN_MUX,
- .funcmask = BIT(11),
- .funcval = BIT(11), /* refer to PAD_UTMI_DRVVBUS1_ENABLE */
-};
-
-static const unsigned usb1_utmi_drvbus_pins[] = { 28 };
-
-static const struct sirfsoc_padmux usb1_dp_dn_padmux = {
- .muxmask_counts = 0,
- .ctrlreg = SIRFSOC_RSC_USB_UART_SHARE,
- .funcmask = BIT(2),
- .funcval = BIT(2),
-};
-
-static const unsigned usb1_dp_dn_pins[] = { 103, 104 };
-
-static const struct sirfsoc_padmux uart1_route_io_usb1_padmux = {
- .muxmask_counts = 0,
- .ctrlreg = SIRFSOC_RSC_USB_UART_SHARE,
- .funcmask = BIT(2),
- .funcval = 0,
-};
-
-static const unsigned uart1_route_io_usb1_pins[] = { 103, 104 };
-
-static const struct sirfsoc_muxmask pulse_count_muxmask[] = {
- {
- .group = 0,
- .mask = BIT(9) | BIT(10) | BIT(11),
- },
-};
-
-static const struct sirfsoc_padmux pulse_count_padmux = {
- .muxmask_counts = ARRAY_SIZE(pulse_count_muxmask),
- .muxmask = pulse_count_muxmask,
-};
-
-static const unsigned pulse_count_pins[] = { 9, 10, 11 };
-
-static const struct sirfsoc_pin_group sirfsoc_pin_groups[] = {
- SIRFSOC_PIN_GROUP("lcd_16bitsgrp", lcd_16bits_pins),
- SIRFSOC_PIN_GROUP("lcd_18bitsgrp", lcd_18bits_pins),
- SIRFSOC_PIN_GROUP("lcd_24bitsgrp", lcd_24bits_pins),
- SIRFSOC_PIN_GROUP("lcdrom_grp", lcdrom_pins),
- SIRFSOC_PIN_GROUP("uart0grp", uart0_pins),
- SIRFSOC_PIN_GROUP("uart0_nostreamctrlgrp", uart0_nostreamctrl_pins),
- SIRFSOC_PIN_GROUP("uart1grp", uart1_pins),
- SIRFSOC_PIN_GROUP("uart2grp", uart2_pins),
- SIRFSOC_PIN_GROUP("uart2_nostreamctrlgrp", uart2_nostreamctrl_pins),
- SIRFSOC_PIN_GROUP("usp0grp", usp0_pins),
- SIRFSOC_PIN_GROUP("usp0_uart_nostreamctrl_grp",
- usp0_uart_nostreamctrl_pins),
- SIRFSOC_PIN_GROUP("usp0_only_utfs_grp", usp0_only_utfs_pins),
- SIRFSOC_PIN_GROUP("usp0_only_urfs_grp", usp0_only_urfs_pins),
- SIRFSOC_PIN_GROUP("usp1grp", usp1_pins),
- SIRFSOC_PIN_GROUP("usp1_uart_nostreamctrl_grp",
- usp1_uart_nostreamctrl_pins),
- SIRFSOC_PIN_GROUP("i2c0grp", i2c0_pins),
- SIRFSOC_PIN_GROUP("i2c1grp", i2c1_pins),
- SIRFSOC_PIN_GROUP("pwm0grp", pwm0_pins),
- SIRFSOC_PIN_GROUP("pwm1grp", pwm1_pins),
- SIRFSOC_PIN_GROUP("pwm2grp", pwm2_pins),
- SIRFSOC_PIN_GROUP("pwm3grp", pwm3_pins),
- SIRFSOC_PIN_GROUP("pwm4grp", pwm4_pins),
- SIRFSOC_PIN_GROUP("vipgrp", vip_pins),
- SIRFSOC_PIN_GROUP("vip_noupligrp", vip_noupli_pins),
- SIRFSOC_PIN_GROUP("warm_rstgrp", warm_rst_pins),
- SIRFSOC_PIN_GROUP("cko0grp", cko0_pins),
- SIRFSOC_PIN_GROUP("cko1grp", cko1_pins),
- SIRFSOC_PIN_GROUP("sdmmc0grp", sdmmc0_pins),
- SIRFSOC_PIN_GROUP("sdmmc1grp", sdmmc1_pins),
- SIRFSOC_PIN_GROUP("sdmmc2grp", sdmmc2_pins),
- SIRFSOC_PIN_GROUP("sdmmc2_nowpgrp", sdmmc2_nowp_pins),
- SIRFSOC_PIN_GROUP("sdmmc3grp", sdmmc3_pins),
- SIRFSOC_PIN_GROUP("sdmmc5grp", sdmmc5_pins),
- SIRFSOC_PIN_GROUP("usb0_upli_drvbusgrp", usb0_upli_drvbus_pins),
- SIRFSOC_PIN_GROUP("usb1_utmi_drvbusgrp", usb1_utmi_drvbus_pins),
- SIRFSOC_PIN_GROUP("usb1_dp_dngrp", usb1_dp_dn_pins),
- SIRFSOC_PIN_GROUP("uart1_route_io_usb1grp", uart1_route_io_usb1_pins),
- SIRFSOC_PIN_GROUP("pulse_countgrp", pulse_count_pins),
- SIRFSOC_PIN_GROUP("i2smclkgrp", i2s_mclk_pins),
- SIRFSOC_PIN_GROUP("i2s_ext_clk_inputgrp", i2s_ext_clk_input_pins),
- SIRFSOC_PIN_GROUP("i2sgrp", i2s_pins),
- SIRFSOC_PIN_GROUP("i2s_no_dingrp", i2s_no_din_pins),
- SIRFSOC_PIN_GROUP("i2s_6chngrp", i2s_6chn_pins),
- SIRFSOC_PIN_GROUP("ac97grp", ac97_pins),
- SIRFSOC_PIN_GROUP("nandgrp", nand_pins),
- SIRFSOC_PIN_GROUP("spi0grp", spi0_pins),
- SIRFSOC_PIN_GROUP("spi1grp", spi1_pins),
- SIRFSOC_PIN_GROUP("gpsgrp", gps_pins),
-};
-
-static const char * const lcd_16bitsgrp[] = { "lcd_16bitsgrp" };
-static const char * const lcd_18bitsgrp[] = { "lcd_18bitsgrp" };
-static const char * const lcd_24bitsgrp[] = { "lcd_24bitsgrp" };
-static const char * const lcdromgrp[] = { "lcdromgrp" };
-static const char * const uart0grp[] = { "uart0grp" };
-static const char * const uart0_nostreamctrlgrp[] = { "uart0_nostreamctrlgrp" };
-static const char * const uart1grp[] = { "uart1grp" };
-static const char * const uart2grp[] = { "uart2grp" };
-static const char * const uart2_nostreamctrlgrp[] = { "uart2_nostreamctrlgrp" };
-static const char * const usp0_uart_nostreamctrl_grp[] = {
- "usp0_uart_nostreamctrl_grp" };
-static const char * const usp0grp[] = { "usp0grp" };
-static const char * const usp0_only_utfs_grp[] = { "usp0_only_utfs_grp" };
-static const char * const usp0_only_urfs_grp[] = { "usp0_only_urfs_grp" };
-
-static const char * const usp1grp[] = { "usp1grp" };
-static const char * const usp1_uart_nostreamctrl_grp[] = {
- "usp1_uart_nostreamctrl_grp" };
-static const char * const i2c0grp[] = { "i2c0grp" };
-static const char * const i2c1grp[] = { "i2c1grp" };
-static const char * const pwm0grp[] = { "pwm0grp" };
-static const char * const pwm1grp[] = { "pwm1grp" };
-static const char * const pwm2grp[] = { "pwm2grp" };
-static const char * const pwm3grp[] = { "pwm3grp" };
-static const char * const pwm4grp[] = { "pwm4grp" };
-static const char * const vipgrp[] = { "vipgrp" };
-static const char * const vip_noupligrp[] = { "vip_noupligrp" };
-static const char * const warm_rstgrp[] = { "warm_rstgrp" };
-static const char * const cko0grp[] = { "cko0grp" };
-static const char * const cko1grp[] = { "cko1grp" };
-static const char * const sdmmc0grp[] = { "sdmmc0grp" };
-static const char * const sdmmc1grp[] = { "sdmmc1grp" };
-static const char * const sdmmc2grp[] = { "sdmmc2grp" };
-static const char * const sdmmc3grp[] = { "sdmmc3grp" };
-static const char * const sdmmc5grp[] = { "sdmmc5grp" };
-static const char * const sdmmc2_nowpgrp[] = { "sdmmc2_nowpgrp" };
-static const char * const usb0_upli_drvbusgrp[] = { "usb0_upli_drvbusgrp" };
-static const char * const usb1_utmi_drvbusgrp[] = { "usb1_utmi_drvbusgrp" };
-static const char * const usb1_dp_dngrp[] = { "usb1_dp_dngrp" };
-static const char * const
- uart1_route_io_usb1grp[] = { "uart1_route_io_usb1grp" };
-static const char * const pulse_countgrp[] = { "pulse_countgrp" };
-static const char * const i2smclkgrp[] = { "i2smclkgrp" };
-static const char * const i2s_ext_clk_inputgrp[] = { "i2s_ext_clk_inputgrp" };
-static const char * const i2sgrp[] = { "i2sgrp" };
-static const char * const i2s_no_dingrp[] = { "i2s_no_dingrp" };
-static const char * const i2s_6chngrp[] = { "i2s_6chngrp" };
-static const char * const ac97grp[] = { "ac97grp" };
-static const char * const nandgrp[] = { "nandgrp" };
-static const char * const spi0grp[] = { "spi0grp" };
-static const char * const spi1grp[] = { "spi1grp" };
-static const char * const gpsgrp[] = { "gpsgrp" };
-
-static const struct sirfsoc_pmx_func sirfsoc_pmx_functions[] = {
- SIRFSOC_PMX_FUNCTION("lcd_16bits", lcd_16bitsgrp, lcd_16bits_padmux),
- SIRFSOC_PMX_FUNCTION("lcd_18bits", lcd_18bitsgrp, lcd_18bits_padmux),
- SIRFSOC_PMX_FUNCTION("lcd_24bits", lcd_24bitsgrp, lcd_24bits_padmux),
- SIRFSOC_PMX_FUNCTION("lcdrom", lcdromgrp, lcdrom_padmux),
- SIRFSOC_PMX_FUNCTION("uart0", uart0grp, uart0_padmux),
- SIRFSOC_PMX_FUNCTION("uart0_nostreamctrl", uart0_nostreamctrlgrp,
- uart0_nostreamctrl_padmux),
- SIRFSOC_PMX_FUNCTION("uart1", uart1grp, uart1_padmux),
- SIRFSOC_PMX_FUNCTION("uart2", uart2grp, uart2_padmux),
- SIRFSOC_PMX_FUNCTION("uart2_nostreamctrl",
- uart2_nostreamctrlgrp, uart2_nostreamctrl_padmux),
- SIRFSOC_PMX_FUNCTION("usp0", usp0grp, usp0_padmux),
- SIRFSOC_PMX_FUNCTION("usp0_uart_nostreamctrl",
- usp0_uart_nostreamctrl_grp,
- usp0_uart_nostreamctrl_padmux),
- SIRFSOC_PMX_FUNCTION("usp0_only_utfs", usp0_only_utfs_grp,
- usp0_only_utfs_padmux),
- SIRFSOC_PMX_FUNCTION("usp0_only_urfs", usp0_only_urfs_grp,
- usp0_only_urfs_padmux),
- SIRFSOC_PMX_FUNCTION("usp1", usp1grp, usp1_padmux),
- SIRFSOC_PMX_FUNCTION("usp1_uart_nostreamctrl",
- usp1_uart_nostreamctrl_grp,
- usp1_uart_nostreamctrl_padmux),
- SIRFSOC_PMX_FUNCTION("i2c0", i2c0grp, i2c0_padmux),
- SIRFSOC_PMX_FUNCTION("i2c1", i2c1grp, i2c1_padmux),
- SIRFSOC_PMX_FUNCTION("pwm0", pwm0grp, pwm0_padmux),
- SIRFSOC_PMX_FUNCTION("pwm1", pwm1grp, pwm1_padmux),
- SIRFSOC_PMX_FUNCTION("pwm2", pwm2grp, pwm2_padmux),
- SIRFSOC_PMX_FUNCTION("pwm3", pwm3grp, pwm3_padmux),
- SIRFSOC_PMX_FUNCTION("pwm4", pwm4grp, pwm4_padmux),
- SIRFSOC_PMX_FUNCTION("vip", vipgrp, vip_padmux),
- SIRFSOC_PMX_FUNCTION("vip_noupli", vip_noupligrp, vip_noupli_padmux),
- SIRFSOC_PMX_FUNCTION("warm_rst", warm_rstgrp, warm_rst_padmux),
- SIRFSOC_PMX_FUNCTION("cko0", cko0grp, cko0_padmux),
- SIRFSOC_PMX_FUNCTION("cko1", cko1grp, cko1_padmux),
- SIRFSOC_PMX_FUNCTION("sdmmc0", sdmmc0grp, sdmmc0_padmux),
- SIRFSOC_PMX_FUNCTION("sdmmc1", sdmmc1grp, sdmmc1_padmux),
- SIRFSOC_PMX_FUNCTION("sdmmc2", sdmmc2grp, sdmmc2_padmux),
- SIRFSOC_PMX_FUNCTION("sdmmc3", sdmmc3grp, sdmmc3_padmux),
- SIRFSOC_PMX_FUNCTION("sdmmc5", sdmmc5grp, sdmmc5_padmux),
- SIRFSOC_PMX_FUNCTION("sdmmc2_nowp",
- sdmmc2_nowpgrp, sdmmc2_nowp_padmux),
- SIRFSOC_PMX_FUNCTION("usb0_upli_drvbus",
- usb0_upli_drvbusgrp, usb0_upli_drvbus_padmux),
- SIRFSOC_PMX_FUNCTION("usb1_utmi_drvbus",
- usb1_utmi_drvbusgrp, usb1_utmi_drvbus_padmux),
- SIRFSOC_PMX_FUNCTION("usb1_dp_dn", usb1_dp_dngrp, usb1_dp_dn_padmux),
- SIRFSOC_PMX_FUNCTION("uart1_route_io_usb1",
- uart1_route_io_usb1grp, uart1_route_io_usb1_padmux),
- SIRFSOC_PMX_FUNCTION("pulse_count", pulse_countgrp, pulse_count_padmux),
- SIRFSOC_PMX_FUNCTION("i2s_mclk", i2smclkgrp, i2s_mclk_padmux),
- SIRFSOC_PMX_FUNCTION("i2s_ext_clk_input", i2s_ext_clk_inputgrp,
- i2s_ext_clk_input_padmux),
- SIRFSOC_PMX_FUNCTION("i2s", i2sgrp, i2s_padmux),
- SIRFSOC_PMX_FUNCTION("i2s_no_din", i2s_no_dingrp, i2s_no_din_padmux),
- SIRFSOC_PMX_FUNCTION("i2s_6chn", i2s_6chngrp, i2s_6chn_padmux),
- SIRFSOC_PMX_FUNCTION("ac97", ac97grp, ac97_padmux),
- SIRFSOC_PMX_FUNCTION("nand", nandgrp, nand_padmux),
- SIRFSOC_PMX_FUNCTION("spi0", spi0grp, spi0_padmux),
- SIRFSOC_PMX_FUNCTION("spi1", spi1grp, spi1_padmux),
- SIRFSOC_PMX_FUNCTION("gps", gpsgrp, gps_padmux),
-};
-
-struct sirfsoc_pinctrl_data atlas6_pinctrl_data = {
- (struct pinctrl_pin_desc *)sirfsoc_pads,
- ARRAY_SIZE(sirfsoc_pads),
- (struct sirfsoc_pin_group *)sirfsoc_pin_groups,
- ARRAY_SIZE(sirfsoc_pin_groups),
- (struct sirfsoc_pmx_func *)sirfsoc_pmx_functions,
- ARRAY_SIZE(sirfsoc_pmx_functions),
-};
-
diff --git a/drivers/pinctrl/sirf/pinctrl-atlas7.c b/drivers/pinctrl/sirf/pinctrl-atlas7.c
deleted file mode 100644
index e54a6e3..0000000
--- a/drivers/pinctrl/sirf/pinctrl-atlas7.c
+++ /dev/null
@@ -1,6157 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-/*
- * pinctrl pads, groups, functions for CSR SiRFatlasVII
- *
- * Copyright (c) 2011 - 2014 Cambridge Silicon Radio Limited, a CSR plc group
- * company.
- */
-
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/io.h>
-#include <linux/bitops.h>
-#include <linux/irq.h>
-#include <linux/slab.h>
-#include <linux/clk.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-#include <linux/of_device.h>
-#include <linux/of_platform.h>
-#include <linux/of_irq.h>
-#include <linux/pinctrl/machine.h>
-#include <linux/pinctrl/pinconf.h>
-#include <linux/pinctrl/pinctrl.h>
-#include <linux/pinctrl/pinmux.h>
-#include <linux/pinctrl/consumer.h>
-#include <linux/pinctrl/pinconf-generic.h>
-#include <linux/gpio/driver.h>
-
-/* Definition of Pad&Mux Properties */
-#define N 0
-
-/* The Bank contains input-disable regisgers */
-#define BANK_DS 0
-
-/* Clear Register offset */
-#define CLR_REG(r) ((r) + 0x04)
-
-/* Definition of multiple function select register */
-#define FUNC_CLEAR_MASK 0x7
-#define FUNC_GPIO 0
-#define FUNC_ANALOGUE 0x8
-#define ANA_CLEAR_MASK 0x1
-
-/* The Atlas7's Pad Type List */
-enum altas7_pad_type {
- PAD_T_4WE_PD = 0, /* ZIO_PAD3V_4WE_PD */
- PAD_T_4WE_PU, /* ZIO_PAD3V_4WE_PD */
- PAD_T_16ST, /* ZIO_PAD3V_SDCLK_PD */
- PAD_T_M31_0204_PD, /* PRDW0204SDGZ_M311311_PD */
- PAD_T_M31_0204_PU, /* PRDW0204SDGZ_M311311_PU */
- PAD_T_M31_0610_PD, /* PRUW0610SDGZ_M311311_PD */
- PAD_T_M31_0610_PU, /* PRUW0610SDGZ_M311311_PU */
- PAD_T_AD, /* PRDWUWHW08SCDG_HZ */
-};
-
-/* Raw value of Driver-Strength Bits */
-#define DS3 BIT(3)
-#define DS2 BIT(2)
-#define DS1 BIT(1)
-#define DS0 BIT(0)
-#define DSZ 0
-
-/* Drive-Strength Intermediate Values */
-#define DS_NULL -1
-#define DS_1BIT_IM_VAL DS0
-#define DS_1BIT_MASK 0x1
-#define DS_2BIT_IM_VAL (DS1 | DS0)
-#define DS_2BIT_MASK 0x3
-#define DS_4BIT_IM_VAL (DS3 | DS2 | DS1 | DS0)
-#define DS_4BIT_MASK 0xf
-
-/* The Drive-Strength of 4WE Pad DS1 0 CO */
-#define DS_4WE_3 (DS1 | DS0) /* 1 1 3 */
-#define DS_4WE_2 (DS1) /* 1 0 2 */
-#define DS_4WE_1 (DS0) /* 0 1 1 */
-#define DS_4WE_0 (DSZ) /* 0 0 0 */
-
-/* The Drive-Strength of 16st Pad DS3 2 1 0 CO */
-#define DS_16ST_15 (DS3 | DS2 | DS1 | DS0) /* 1 1 1 1 15 */
-#define DS_16ST_14 (DS3 | DS2 | DS0) /* 1 1 0 1 13 */
-#define DS_16ST_13 (DS3 | DS2 | DS1) /* 1 1 1 0 14 */
-#define DS_16ST_12 (DS2 | DS1 | DS0) /* 0 1 1 1 7 */
-#define DS_16ST_11 (DS2 | DS0) /* 0 1 0 1 5 */
-#define DS_16ST_10 (DS3 | DS1 | DS0) /* 1 0 1 1 11 */
-#define DS_16ST_9 (DS3 | DS0) /* 1 0 0 1 9 */
-#define DS_16ST_8 (DS1 | DS0) /* 0 0 1 1 3 */
-#define DS_16ST_7 (DS2 | DS1) /* 0 1 1 0 6 */
-#define DS_16ST_6 (DS3 | DS2) /* 1 1 0 0 12 */
-#define DS_16ST_5 (DS2) /* 0 1 0 0 4 */
-#define DS_16ST_4 (DS3 | DS1) /* 1 0 1 0 10 */
-#define DS_16ST_3 (DS1) /* 0 0 1 0 2 */
-#define DS_16ST_2 (DS0) /* 0 0 0 1 1 */
-#define DS_16ST_1 (DSZ) /* 0 0 0 0 0 */
-#define DS_16ST_0 (DS3) /* 1 0 0 0 8 */
-
-/* The Drive-Strength of M31 Pad DS0 CO */
-#define DS_M31_0 (DSZ) /* 0 0 */
-#define DS_M31_1 (DS0) /* 1 1 */
-
-/* Raw values of Pull Option Bits */
-#define PUN BIT(1)
-#define PD BIT(0)
-#define PE BIT(0)
-#define PZ 0
-
-/* Definition of Pull Types */
-#define PULL_UP 0
-#define HIGH_HYSTERESIS 1
-#define HIGH_Z 2
-#define PULL_DOWN 3
-#define PULL_DISABLE 4
-#define PULL_ENABLE 5
-#define PULL_UNKNOWN -1
-
-/* Pull Options for 4WE Pad PUN PD CO */
-#define P4WE_PULL_MASK 0x3
-#define P4WE_PULL_DOWN (PUN | PD) /* 1 1 3 */
-#define P4WE_HIGH_Z (PUN) /* 1 0 2 */
-#define P4WE_HIGH_HYSTERESIS (PD) /* 0 1 1 */
-#define P4WE_PULL_UP (PZ) /* 0 0 0 */
-
-/* Pull Options for 16ST Pad PUN PD CO */
-#define P16ST_PULL_MASK 0x3
-#define P16ST_PULL_DOWN (PUN | PD) /* 1 1 3 */
-#define P16ST_HIGH_Z (PUN) /* 1 0 2 */
-#define P16ST_PULL_UP (PZ) /* 0 0 0 */
-
-/* Pull Options for M31 Pad PE */
-#define PM31_PULL_MASK 0x1
-#define PM31_PULL_ENABLED (PE) /* 1 */
-#define PM31_PULL_DISABLED (PZ) /* 0 */
-
-/* Pull Options for A/D Pad PUN PD CO */
-#define PANGD_PULL_MASK 0x3
-#define PANGD_PULL_DOWN (PUN | PD) /* 1 1 3 */
-#define PANGD_HIGH_Z (PUN) /* 1 0 2 */
-#define PANGD_PULL_UP (PZ) /* 0 0 0 */
-
-/* Definition of Input Disable */
-#define DI_MASK 0x1
-#define DI_DISABLE 0x1
-#define DI_ENABLE 0x0
-
-/* Definition of Input Disable Value */
-#define DIV_MASK 0x1
-#define DIV_DISABLE 0x1
-#define DIV_ENABLE 0x0
-
-/* Number of Function input disable registers */
-#define NUM_OF_IN_DISABLE_REG 0x2
-
-/* Offset of Function input disable registers */
-#define IN_DISABLE_0_REG_SET 0x0A00
-#define IN_DISABLE_0_REG_CLR 0x0A04
-#define IN_DISABLE_1_REG_SET 0x0A08
-#define IN_DISABLE_1_REG_CLR 0x0A0C
-#define IN_DISABLE_VAL_0_REG_SET 0x0A80
-#define IN_DISABLE_VAL_0_REG_CLR 0x0A84
-#define IN_DISABLE_VAL_1_REG_SET 0x0A88
-#define IN_DISABLE_VAL_1_REG_CLR 0x0A8C
-
-/* Offset of the SDIO9SEL*/
-#define SYS2PCI_SDIO9SEL 0x14
-
-struct dt_params {
- const char *property;
- int value;
-};
-
-/**
- * struct atlas7_pad_conf - Atlas7 Pad Configuration
- * @id: The ID of this Pad.
- * @type: The type of this Pad.
- * @mux_reg: The mux register offset.
- * This register contains the mux.
- * @pupd_reg: The pull-up/down register offset.
- * @drvstr_reg: The drive-strength register offset.
- * @ad_ctrl_reg: The Analogue/Digital Control register.
- *
- * @mux_bit: The start bit of mux register.
- * @pupd_bit: The start bit of pull-up/down register.
- * @drvstr_bit: The start bit of drive-strength register.
- * @ad_ctrl_bit: The start bit of analogue/digital register.
- */
-struct atlas7_pad_config {
- const u32 id;
- u32 type;
- u32 mux_reg;
- u32 pupd_reg;
- u32 drvstr_reg;
- u32 ad_ctrl_reg;
- /* bits in register */
- u8 mux_bit;
- u8 pupd_bit;
- u8 drvstr_bit;
- u8 ad_ctrl_bit;
-};
-
-#define PADCONF(pad, t, mr, pr, dsr, adr, mb, pb, dsb, adb) \
- { \
- .id = pad, \
- .type = t, \
- .mux_reg = mr, \
- .pupd_reg = pr, \
- .drvstr_reg = dsr, \
- .ad_ctrl_reg = adr, \
- .mux_bit = mb, \
- .pupd_bit = pb, \
- .drvstr_bit = dsb, \
- .ad_ctrl_bit = adb, \
- }
-
-/*
- * struct atlas7_pad_status - Atlas7 Pad status
- */
-struct atlas7_pad_status {
- u8 func;
- u8 pull;
- u8 dstr;
- u8 reserved;
-};
-
-/**
- * struct atlas7_pad_mux - Atlas7 mux
- * @bank: The bank of this pad's registers on.
- * @pin : The ID of this Pad.
- * @func: The mux func on this Pad.
- * @dinput_reg: The Input-Disable register offset.
- * @dinput_bit: The start bit of Input-Disable register.
- * @dinput_val_reg: The Input-Disable-value register offset.
- * This register is used to set the value of this pad
- * if this pad was disabled.
- * @dinput_val_bit: The start bit of Input-Disable Value register.
- */
-struct atlas7_pad_mux {
- u32 bank;
- u32 pin;
- u32 func;
- u32 dinput_reg;
- u32 dinput_bit;
- u32 dinput_val_reg;
- u32 dinput_val_bit;
-};
-
-#define MUX(b, pad, f, dr, db, dvr, dvb) \
- { \
- .bank = b, \
- .pin = pad, \
- .func = f, \
- .dinput_reg = dr, \
- .dinput_bit = db, \
- .dinput_val_reg = dvr, \
- .dinput_val_bit = dvb, \
- }
-
-struct atlas7_grp_mux {
- unsigned int group;
- unsigned int pad_mux_count;
- const struct atlas7_pad_mux *pad_mux_list;
-};
-
- /**
- * struct sirfsoc_pin_group - describes a SiRFprimaII pin group
- * @name: the name of this specific pin group
- * @pins: an array of discrete physical pins used in this group, taken
- * from the driver-local pin enumeration space
- * @num_pins: the number of pins in this group array, i.e. the number of
- * elements in .pins so we can iterate over that array
- */
-struct atlas7_pin_group {
- const char *name;
- const unsigned int *pins;
- const unsigned num_pins;
-};
-
-#define GROUP(n, p) \
- { \
- .name = n, \
- .pins = p, \
- .num_pins = ARRAY_SIZE(p), \
- }
-
-struct atlas7_pmx_func {
- const char *name;
- const char * const *groups;
- const unsigned num_groups;
- const struct atlas7_grp_mux *grpmux;
-};
-
-#define FUNCTION(n, g, m) \
- { \
- .name = n, \
- .groups = g, \
- .num_groups = ARRAY_SIZE(g), \
- .grpmux = m, \
- }
-
-struct atlas7_pinctrl_data {
- struct pinctrl_pin_desc *pads;
- int pads_cnt;
- struct atlas7_pin_group *grps;
- int grps_cnt;
- struct atlas7_pmx_func *funcs;
- int funcs_cnt;
- struct atlas7_pad_config *confs;
- int confs_cnt;
-};
-
-/* Platform info of atlas7 pinctrl */
-#define ATLAS7_PINCTRL_REG_BANKS 2
-#define ATLAS7_PINCTRL_BANK_0_PINS 18
-#define ATLAS7_PINCTRL_BANK_1_PINS 141
-#define ATLAS7_PINCTRL_TOTAL_PINS \
- (ATLAS7_PINCTRL_BANK_0_PINS + ATLAS7_PINCTRL_BANK_1_PINS)
-
-/**
- * Atlas7 GPIO Chip
- */
-
-#define NGPIO_OF_BANK 32
-#define GPIO_TO_BANK(gpio) ((gpio) / NGPIO_OF_BANK)
-
-/* Registers of GPIO Controllers */
-#define ATLAS7_GPIO_BASE(g, b) ((g)->reg + 0x100 * (b))
-#define ATLAS7_GPIO_CTRL(b, i) ((b)->base + 4 * (i))
-#define ATLAS7_GPIO_INT_STATUS(b) ((b)->base + 0x8C)
-
-/* Definition bits of GPIO Control Registers */
-#define ATLAS7_GPIO_CTL_INTR_LOW_MASK BIT(0)
-#define ATLAS7_GPIO_CTL_INTR_HIGH_MASK BIT(1)
-#define ATLAS7_GPIO_CTL_INTR_TYPE_MASK BIT(2)
-#define ATLAS7_GPIO_CTL_INTR_EN_MASK BIT(3)
-#define ATLAS7_GPIO_CTL_INTR_STATUS_MASK BIT(4)
-#define ATLAS7_GPIO_CTL_OUT_EN_MASK BIT(5)
-#define ATLAS7_GPIO_CTL_DATAOUT_MASK BIT(6)
-#define ATLAS7_GPIO_CTL_DATAIN_MASK BIT(7)
-
-struct atlas7_gpio_bank {
- int id;
- int irq;
- void __iomem *base;
- unsigned int gpio_offset;
- unsigned int ngpio;
- const unsigned int *gpio_pins;
- u32 sleep_data[NGPIO_OF_BANK];
-};
-
-struct atlas7_gpio_chip {
- const char *name;
- void __iomem *reg;
- struct clk *clk;
- int nbank;
- raw_spinlock_t lock;
- struct gpio_chip chip;
- struct atlas7_gpio_bank banks[];
-};
-
-struct atlas7_pmx {
- struct device *dev;
- struct pinctrl_dev *pctl;
- struct pinctrl_desc pctl_desc;
- struct atlas7_pinctrl_data *pctl_data;
- void __iomem *regs[ATLAS7_PINCTRL_REG_BANKS];
- void __iomem *sys2pci_base;
- u32 status_ds[NUM_OF_IN_DISABLE_REG];
- u32 status_dsv[NUM_OF_IN_DISABLE_REG];
- struct atlas7_pad_status sleep_data[ATLAS7_PINCTRL_TOTAL_PINS];
-};
-
-/*
- * Pad list for the pinmux subsystem
- * refer to A7DA IO Summary - CS-314158-DD-4E.xls
- */
-
-/* Pads in IOC RTC & TOP */
-static const struct pinctrl_pin_desc atlas7_ioc_pads[] = {
- /* RTC PADs */
- PINCTRL_PIN(0, "rtc_gpio_0"),
- PINCTRL_PIN(1, "rtc_gpio_1"),
- PINCTRL_PIN(2, "rtc_gpio_2"),
- PINCTRL_PIN(3, "rtc_gpio_3"),
- PINCTRL_PIN(4, "low_bat_ind_b"),
- PINCTRL_PIN(5, "on_key_b"),
- PINCTRL_PIN(6, "ext_on"),
- PINCTRL_PIN(7, "mem_on"),
- PINCTRL_PIN(8, "core_on"),
- PINCTRL_PIN(9, "io_on"),
- PINCTRL_PIN(10, "can0_tx"),
- PINCTRL_PIN(11, "can0_rx"),
- PINCTRL_PIN(12, "spi0_clk"),
- PINCTRL_PIN(13, "spi0_cs_b"),
- PINCTRL_PIN(14, "spi0_io_0"),
- PINCTRL_PIN(15, "spi0_io_1"),
- PINCTRL_PIN(16, "spi0_io_2"),
- PINCTRL_PIN(17, "spi0_io_3"),
-
- /* TOP PADs */
- PINCTRL_PIN(18, "spi1_en"),
- PINCTRL_PIN(19, "spi1_clk"),
- PINCTRL_PIN(20, "spi1_din"),
- PINCTRL_PIN(21, "spi1_dout"),
- PINCTRL_PIN(22, "trg_spi_clk"),
- PINCTRL_PIN(23, "trg_spi_di"),
- PINCTRL_PIN(24, "trg_spi_do"),
- PINCTRL_PIN(25, "trg_spi_cs_b"),
- PINCTRL_PIN(26, "trg_acq_d1"),
- PINCTRL_PIN(27, "trg_irq_b"),
- PINCTRL_PIN(28, "trg_acq_d0"),
- PINCTRL_PIN(29, "trg_acq_clk"),
- PINCTRL_PIN(30, "trg_shutdown_b_out"),
- PINCTRL_PIN(31, "sdio2_clk"),
- PINCTRL_PIN(32, "sdio2_cmd"),
- PINCTRL_PIN(33, "sdio2_dat_0"),
- PINCTRL_PIN(34, "sdio2_dat_1"),
- PINCTRL_PIN(35, "sdio2_dat_2"),
- PINCTRL_PIN(36, "sdio2_dat_3"),
- PINCTRL_PIN(37, "df_ad_7"),
- PINCTRL_PIN(38, "df_ad_6"),
- PINCTRL_PIN(39, "df_ad_5"),
- PINCTRL_PIN(40, "df_ad_4"),
- PINCTRL_PIN(41, "df_ad_3"),
- PINCTRL_PIN(42, "df_ad_2"),
- PINCTRL_PIN(43, "df_ad_1"),
- PINCTRL_PIN(44, "df_ad_0"),
- PINCTRL_PIN(45, "df_dqs"),
- PINCTRL_PIN(46, "df_cle"),
- PINCTRL_PIN(47, "df_ale"),
- PINCTRL_PIN(48, "df_we_b"),
- PINCTRL_PIN(49, "df_re_b"),
- PINCTRL_PIN(50, "df_ry_by"),
- PINCTRL_PIN(51, "df_cs_b_1"),
- PINCTRL_PIN(52, "df_cs_b_0"),
- PINCTRL_PIN(53, "l_pclk"),
- PINCTRL_PIN(54, "l_lck"),
- PINCTRL_PIN(55, "l_fck"),
- PINCTRL_PIN(56, "l_de"),
- PINCTRL_PIN(57, "ldd_0"),
- PINCTRL_PIN(58, "ldd_1"),
- PINCTRL_PIN(59, "ldd_2"),
- PINCTRL_PIN(60, "ldd_3"),
- PINCTRL_PIN(61, "ldd_4"),
- PINCTRL_PIN(62, "ldd_5"),
- PINCTRL_PIN(63, "ldd_6"),
- PINCTRL_PIN(64, "ldd_7"),
- PINCTRL_PIN(65, "ldd_8"),
- PINCTRL_PIN(66, "ldd_9"),
- PINCTRL_PIN(67, "ldd_10"),
- PINCTRL_PIN(68, "ldd_11"),
- PINCTRL_PIN(69, "ldd_12"),
- PINCTRL_PIN(70, "ldd_13"),
- PINCTRL_PIN(71, "ldd_14"),
- PINCTRL_PIN(72, "ldd_15"),
- PINCTRL_PIN(73, "lcd_gpio_20"),
- PINCTRL_PIN(74, "vip_0"),
- PINCTRL_PIN(75, "vip_1"),
- PINCTRL_PIN(76, "vip_2"),
- PINCTRL_PIN(77, "vip_3"),
- PINCTRL_PIN(78, "vip_4"),
- PINCTRL_PIN(79, "vip_5"),
- PINCTRL_PIN(80, "vip_6"),
- PINCTRL_PIN(81, "vip_7"),
- PINCTRL_PIN(82, "vip_pxclk"),
- PINCTRL_PIN(83, "vip_hsync"),
- PINCTRL_PIN(84, "vip_vsync"),
- PINCTRL_PIN(85, "sdio3_clk"),
- PINCTRL_PIN(86, "sdio3_cmd"),
- PINCTRL_PIN(87, "sdio3_dat_0"),
- PINCTRL_PIN(88, "sdio3_dat_1"),
- PINCTRL_PIN(89, "sdio3_dat_2"),
- PINCTRL_PIN(90, "sdio3_dat_3"),
- PINCTRL_PIN(91, "sdio5_clk"),
- PINCTRL_PIN(92, "sdio5_cmd"),
- PINCTRL_PIN(93, "sdio5_dat_0"),
- PINCTRL_PIN(94, "sdio5_dat_1"),
- PINCTRL_PIN(95, "sdio5_dat_2"),
- PINCTRL_PIN(96, "sdio5_dat_3"),
- PINCTRL_PIN(97, "rgmii_txd_0"),
- PINCTRL_PIN(98, "rgmii_txd_1"),
- PINCTRL_PIN(99, "rgmii_txd_2"),
- PINCTRL_PIN(100, "rgmii_txd_3"),
- PINCTRL_PIN(101, "rgmii_txclk"),
- PINCTRL_PIN(102, "rgmii_tx_ctl"),
- PINCTRL_PIN(103, "rgmii_rxd_0"),
- PINCTRL_PIN(104, "rgmii_rxd_1"),
- PINCTRL_PIN(105, "rgmii_rxd_2"),
- PINCTRL_PIN(106, "rgmii_rxd_3"),
- PINCTRL_PIN(107, "rgmii_rx_clk"),
- PINCTRL_PIN(108, "rgmii_rxc_ctl"),
- PINCTRL_PIN(109, "rgmii_mdio"),
- PINCTRL_PIN(110, "rgmii_mdc"),
- PINCTRL_PIN(111, "rgmii_intr_n"),
- PINCTRL_PIN(112, "i2s_mclk"),
- PINCTRL_PIN(113, "i2s_bclk"),
- PINCTRL_PIN(114, "i2s_ws"),
- PINCTRL_PIN(115, "i2s_dout0"),
- PINCTRL_PIN(116, "i2s_dout1"),
- PINCTRL_PIN(117, "i2s_dout2"),
- PINCTRL_PIN(118, "i2s_din"),
- PINCTRL_PIN(119, "gpio_0"),
- PINCTRL_PIN(120, "gpio_1"),
- PINCTRL_PIN(121, "gpio_2"),
- PINCTRL_PIN(122, "gpio_3"),
- PINCTRL_PIN(123, "gpio_4"),
- PINCTRL_PIN(124, "gpio_5"),
- PINCTRL_PIN(125, "gpio_6"),
- PINCTRL_PIN(126, "gpio_7"),
- PINCTRL_PIN(127, "sda_0"),
- PINCTRL_PIN(128, "scl_0"),
- PINCTRL_PIN(129, "coex_pio_0"),
- PINCTRL_PIN(130, "coex_pio_1"),
- PINCTRL_PIN(131, "coex_pio_2"),
- PINCTRL_PIN(132, "coex_pio_3"),
- PINCTRL_PIN(133, "uart0_tx"),
- PINCTRL_PIN(134, "uart0_rx"),
- PINCTRL_PIN(135, "uart1_tx"),
- PINCTRL_PIN(136, "uart1_rx"),
- PINCTRL_PIN(137, "uart3_tx"),
- PINCTRL_PIN(138, "uart3_rx"),
- PINCTRL_PIN(139, "uart4_tx"),
- PINCTRL_PIN(140, "uart4_rx"),
- PINCTRL_PIN(141, "usp0_clk"),
- PINCTRL_PIN(142, "usp0_tx"),
- PINCTRL_PIN(143, "usp0_rx"),
- PINCTRL_PIN(144, "usp0_fs"),
- PINCTRL_PIN(145, "usp1_clk"),
- PINCTRL_PIN(146, "usp1_tx"),
- PINCTRL_PIN(147, "usp1_rx"),
- PINCTRL_PIN(148, "usp1_fs"),
- PINCTRL_PIN(149, "lvds_tx0d4p"),
- PINCTRL_PIN(150, "lvds_tx0d4n"),
- PINCTRL_PIN(151, "lvds_tx0d3p"),
- PINCTRL_PIN(152, "lvds_tx0d3n"),
- PINCTRL_PIN(153, "lvds_tx0d2p"),
- PINCTRL_PIN(154, "lvds_tx0d2n"),
- PINCTRL_PIN(155, "lvds_tx0d1p"),
- PINCTRL_PIN(156, "lvds_tx0d1n"),
- PINCTRL_PIN(157, "lvds_tx0d0p"),
- PINCTRL_PIN(158, "lvds_tx0d0n"),
- PINCTRL_PIN(159, "jtag_tdo"),
- PINCTRL_PIN(160, "jtag_tms"),
- PINCTRL_PIN(161, "jtag_tck"),
- PINCTRL_PIN(162, "jtag_tdi"),
- PINCTRL_PIN(163, "jtag_trstn"),
-};
-
-static struct atlas7_pad_config atlas7_ioc_pad_confs[] = {
- /* The Configuration of IOC_RTC Pads */
- PADCONF(0, 3, 0x0, 0x100, 0x200, -1, 0, 0, 0, 0),
- PADCONF(1, 3, 0x0, 0x100, 0x200, -1, 4, 2, 2, 0),
- PADCONF(2, 3, 0x0, 0x100, 0x200, -1, 8, 4, 4, 0),
- PADCONF(3, 5, 0x0, 0x100, 0x200, -1, 12, 6, 6, 0),
- PADCONF(4, 4, 0x0, 0x100, 0x200, -1, 16, 8, 8, 0),
- PADCONF(5, 4, 0x0, 0x100, 0x200, -1, 20, 10, 10, 0),
- PADCONF(6, 3, 0x0, 0x100, 0x200, -1, 24, 12, 12, 0),
- PADCONF(7, 3, 0x0, 0x100, 0x200, -1, 28, 14, 14, 0),
- PADCONF(8, 3, 0x8, 0x100, 0x200, -1, 0, 16, 16, 0),
- PADCONF(9, 3, 0x8, 0x100, 0x200, -1, 4, 18, 18, 0),
- PADCONF(10, 4, 0x8, 0x100, 0x200, -1, 8, 20, 20, 0),
- PADCONF(11, 4, 0x8, 0x100, 0x200, -1, 12, 22, 22, 0),
- PADCONF(12, 5, 0x8, 0x100, 0x200, -1, 16, 24, 24, 0),
- PADCONF(13, 6, 0x8, 0x100, 0x200, -1, 20, 26, 26, 0),
- PADCONF(14, 5, 0x8, 0x100, 0x200, -1, 24, 28, 28, 0),
- PADCONF(15, 5, 0x8, 0x100, 0x200, -1, 28, 30, 30, 0),
- PADCONF(16, 5, 0x10, 0x108, 0x208, -1, 0, 0, 0, 0),
- PADCONF(17, 5, 0x10, 0x108, 0x208, -1, 4, 2, 2, 0),
- /* The Configuration of IOC_TOP Pads */
- PADCONF(18, 5, 0x80, 0x180, 0x300, -1, 0, 0, 0, 0),
- PADCONF(19, 5, 0x80, 0x180, 0x300, -1, 4, 2, 2, 0),
- PADCONF(20, 5, 0x80, 0x180, 0x300, -1, 8, 4, 4, 0),
- PADCONF(21, 5, 0x80, 0x180, 0x300, -1, 12, 6, 6, 0),
- PADCONF(22, 5, 0x88, 0x188, 0x308, -1, 0, 0, 0, 0),
- PADCONF(23, 5, 0x88, 0x188, 0x308, -1, 4, 2, 2, 0),
- PADCONF(24, 5, 0x88, 0x188, 0x308, -1, 8, 4, 4, 0),
- PADCONF(25, 6, 0x88, 0x188, 0x308, -1, 12, 6, 6, 0),
- PADCONF(26, 5, 0x88, 0x188, 0x308, -1, 16, 8, 8, 0),
- PADCONF(27, 6, 0x88, 0x188, 0x308, -1, 20, 10, 10, 0),
- PADCONF(28, 5, 0x88, 0x188, 0x308, -1, 24, 12, 12, 0),
- PADCONF(29, 5, 0x88, 0x188, 0x308, -1, 28, 14, 14, 0),
- PADCONF(30, 5, 0x90, 0x188, 0x308, -1, 0, 16, 16, 0),
- PADCONF(31, 2, 0x98, 0x190, 0x310, -1, 0, 0, 0, 0),
- PADCONF(32, 1, 0x98, 0x190, 0x310, -1, 4, 2, 4, 0),
- PADCONF(33, 1, 0x98, 0x190, 0x310, -1, 8, 4, 6, 0),
- PADCONF(34, 1, 0x98, 0x190, 0x310, -1, 12, 6, 8, 0),
- PADCONF(35, 1, 0x98, 0x190, 0x310, -1, 16, 8, 10, 0),
- PADCONF(36, 1, 0x98, 0x190, 0x310, -1, 20, 10, 12, 0),
- PADCONF(37, 1, 0xa0, 0x198, 0x318, -1, 0, 0, 0, 0),
- PADCONF(38, 1, 0xa0, 0x198, 0x318, -1, 4, 2, 2, 0),
- PADCONF(39, 1, 0xa0, 0x198, 0x318, -1, 8, 4, 4, 0),
- PADCONF(40, 1, 0xa0, 0x198, 0x318, -1, 12, 6, 6, 0),
- PADCONF(41, 1, 0xa0, 0x198, 0x318, -1, 16, 8, 8, 0),
- PADCONF(42, 1, 0xa0, 0x198, 0x318, -1, 20, 10, 10, 0),
- PADCONF(43, 1, 0xa0, 0x198, 0x318, -1, 24, 12, 12, 0),
- PADCONF(44, 1, 0xa0, 0x198, 0x318, -1, 28, 14, 14, 0),
- PADCONF(45, 0, 0xa8, 0x198, 0x318, -1, 0, 16, 16, 0),
- PADCONF(46, 0, 0xa8, 0x198, 0x318, -1, 4, 18, 18, 0),
- PADCONF(47, 1, 0xa8, 0x198, 0x318, -1, 8, 20, 20, 0),
- PADCONF(48, 1, 0xa8, 0x198, 0x318, -1, 12, 22, 22, 0),
- PADCONF(49, 1, 0xa8, 0x198, 0x318, -1, 16, 24, 24, 0),
- PADCONF(50, 1, 0xa8, 0x198, 0x318, -1, 20, 26, 26, 0),
- PADCONF(51, 1, 0xa8, 0x198, 0x318, -1, 24, 28, 28, 0),
- PADCONF(52, 1, 0xa8, 0x198, 0x318, -1, 28, 30, 30, 0),
- PADCONF(53, 0, 0xb0, 0x1a0, 0x320, -1, 0, 0, 0, 0),
- PADCONF(54, 0, 0xb0, 0x1a0, 0x320, -1, 4, 2, 2, 0),
- PADCONF(55, 0, 0xb0, 0x1a0, 0x320, -1, 8, 4, 4, 0),
- PADCONF(56, 0, 0xb0, 0x1a0, 0x320, -1, 12, 6, 6, 0),
- PADCONF(57, 0, 0xb0, 0x1a0, 0x320, -1, 16, 8, 8, 0),
- PADCONF(58, 0, 0xb0, 0x1a0, 0x320, -1, 20, 10, 10, 0),
- PADCONF(59, 0, 0xb0, 0x1a0, 0x320, -1, 24, 12, 12, 0),
- PADCONF(60, 0, 0xb0, 0x1a0, 0x320, -1, 28, 14, 14, 0),
- PADCONF(61, 0, 0xb8, 0x1a0, 0x320, -1, 0, 16, 16, 0),
- PADCONF(62, 0, 0xb8, 0x1a0, 0x320, -1, 4, 18, 18, 0),
- PADCONF(63, 0, 0xb8, 0x1a0, 0x320, -1, 8, 20, 20, 0),
- PADCONF(64, 0, 0xb8, 0x1a0, 0x320, -1, 12, 22, 22, 0),
- PADCONF(65, 0, 0xb8, 0x1a0, 0x320, -1, 16, 24, 24, 0),
- PADCONF(66, 0, 0xb8, 0x1a0, 0x320, -1, 20, 26, 26, 0),
- PADCONF(67, 0, 0xb8, 0x1a0, 0x320, -1, 24, 28, 28, 0),
- PADCONF(68, 0, 0xb8, 0x1a0, 0x320, -1, 28, 30, 30, 0),
- PADCONF(69, 0, 0xc0, 0x1a8, 0x328, -1, 0, 0, 0, 0),
- PADCONF(70, 0, 0xc0, 0x1a8, 0x328, -1, 4, 2, 2, 0),
- PADCONF(71, 0, 0xc0, 0x1a8, 0x328, -1, 8, 4, 4, 0),
- PADCONF(72, 0, 0xc0, 0x1a8, 0x328, -1, 12, 6, 6, 0),
- PADCONF(73, 0, 0xc0, 0x1a8, 0x328, -1, 16, 8, 8, 0),
- PADCONF(74, 0, 0xc8, 0x1b0, 0x330, -1, 0, 0, 0, 0),
- PADCONF(75, 0, 0xc8, 0x1b0, 0x330, -1, 4, 2, 2, 0),
- PADCONF(76, 0, 0xc8, 0x1b0, 0x330, -1, 8, 4, 4, 0),
- PADCONF(77, 0, 0xc8, 0x1b0, 0x330, -1, 12, 6, 6, 0),
- PADCONF(78, 0, 0xc8, 0x1b0, 0x330, -1, 16, 8, 8, 0),
- PADCONF(79, 0, 0xc8, 0x1b0, 0x330, -1, 20, 10, 10, 0),
- PADCONF(80, 0, 0xc8, 0x1b0, 0x330, -1, 24, 12, 12, 0),
- PADCONF(81, 0, 0xc8, 0x1b0, 0x330, -1, 28, 14, 14, 0),
- PADCONF(82, 0, 0xd0, 0x1b0, 0x330, -1, 0, 16, 16, 0),
- PADCONF(83, 0, 0xd0, 0x1b0, 0x330, -1, 4, 18, 18, 0),
- PADCONF(84, 0, 0xd0, 0x1b0, 0x330, -1, 8, 20, 20, 0),
- PADCONF(85, 2, 0xd8, 0x1b8, 0x338, -1, 0, 0, 0, 0),
- PADCONF(86, 1, 0xd8, 0x1b8, 0x338, -1, 4, 4, 4, 0),
- PADCONF(87, 1, 0xd8, 0x1b8, 0x338, -1, 8, 6, 6, 0),
- PADCONF(88, 1, 0xd8, 0x1b8, 0x338, -1, 12, 8, 8, 0),
- PADCONF(89, 1, 0xd8, 0x1b8, 0x338, -1, 16, 10, 10, 0),
- PADCONF(90, 1, 0xd8, 0x1b8, 0x338, -1, 20, 12, 12, 0),
- PADCONF(91, 2, 0xe0, 0x1c0, 0x340, -1, 0, 0, 0, 0),
- PADCONF(92, 1, 0xe0, 0x1c0, 0x340, -1, 4, 4, 4, 0),
- PADCONF(93, 1, 0xe0, 0x1c0, 0x340, -1, 8, 6, 6, 0),
- PADCONF(94, 1, 0xe0, 0x1c0, 0x340, -1, 12, 8, 8, 0),
- PADCONF(95, 1, 0xe0, 0x1c0, 0x340, -1, 16, 10, 10, 0),
- PADCONF(96, 1, 0xe0, 0x1c0, 0x340, -1, 20, 12, 12, 0),
- PADCONF(97, 0, 0xe8, 0x1c8, 0x348, -1, 0, 0, 0, 0),
- PADCONF(98, 0, 0xe8, 0x1c8, 0x348, -1, 4, 2, 2, 0),
- PADCONF(99, 0, 0xe8, 0x1c8, 0x348, -1, 8, 4, 4, 0),
- PADCONF(100, 0, 0xe8, 0x1c8, 0x348, -1, 12, 6, 6, 0),
- PADCONF(101, 2, 0xe8, 0x1c8, 0x348, -1, 16, 8, 8, 0),
- PADCONF(102, 0, 0xe8, 0x1c8, 0x348, -1, 20, 12, 12, 0),
- PADCONF(103, 0, 0xe8, 0x1c8, 0x348, -1, 24, 14, 14, 0),
- PADCONF(104, 0, 0xe8, 0x1c8, 0x348, -1, 28, 16, 16, 0),
- PADCONF(105, 0, 0xf0, 0x1c8, 0x348, -1, 0, 18, 18, 0),
- PADCONF(106, 0, 0xf0, 0x1c8, 0x348, -1, 4, 20, 20, 0),
- PADCONF(107, 0, 0xf0, 0x1c8, 0x348, -1, 8, 22, 22, 0),
- PADCONF(108, 0, 0xf0, 0x1c8, 0x348, -1, 12, 24, 24, 0),
- PADCONF(109, 1, 0xf0, 0x1c8, 0x348, -1, 16, 26, 26, 0),
- PADCONF(110, 0, 0xf0, 0x1c8, 0x348, -1, 20, 28, 28, 0),
- PADCONF(111, 1, 0xf0, 0x1c8, 0x348, -1, 24, 30, 30, 0),
- PADCONF(112, 5, 0xf8, 0x200, 0x350, -1, 0, 0, 0, 0),
- PADCONF(113, 5, 0xf8, 0x200, 0x350, -1, 4, 2, 2, 0),
- PADCONF(114, 5, 0xf8, 0x200, 0x350, -1, 8, 4, 4, 0),
- PADCONF(115, 5, 0xf8, 0x200, 0x350, -1, 12, 6, 6, 0),
- PADCONF(116, 5, 0xf8, 0x200, 0x350, -1, 16, 8, 8, 0),
- PADCONF(117, 5, 0xf8, 0x200, 0x350, -1, 20, 10, 10, 0),
- PADCONF(118, 5, 0xf8, 0x200, 0x350, -1, 24, 12, 12, 0),
- PADCONF(119, 5, 0x100, 0x250, 0x358, -1, 0, 0, 0, 0),
- PADCONF(120, 5, 0x100, 0x250, 0x358, -1, 4, 2, 2, 0),
- PADCONF(121, 5, 0x100, 0x250, 0x358, -1, 8, 4, 4, 0),
- PADCONF(122, 5, 0x100, 0x250, 0x358, -1, 12, 6, 6, 0),
- PADCONF(123, 6, 0x100, 0x250, 0x358, -1, 16, 8, 8, 0),
- PADCONF(124, 6, 0x100, 0x250, 0x358, -1, 20, 10, 10, 0),
- PADCONF(125, 6, 0x100, 0x250, 0x358, -1, 24, 12, 12, 0),
- PADCONF(126, 6, 0x100, 0x250, 0x358, -1, 28, 14, 14, 0),
- PADCONF(127, 6, 0x108, 0x250, 0x358, -1, 16, 24, 24, 0),
- PADCONF(128, 6, 0x108, 0x250, 0x358, -1, 20, 26, 26, 0),
- PADCONF(129, 0, 0x110, 0x258, 0x360, -1, 0, 0, 0, 0),
- PADCONF(130, 0, 0x110, 0x258, 0x360, -1, 4, 2, 2, 0),
- PADCONF(131, 0, 0x110, 0x258, 0x360, -1, 8, 4, 4, 0),
- PADCONF(132, 0, 0x110, 0x258, 0x360, -1, 12, 6, 6, 0),
- PADCONF(133, 6, 0x118, 0x260, 0x368, -1, 0, 0, 0, 0),
- PADCONF(134, 6, 0x118, 0x260, 0x368, -1, 4, 2, 2, 0),
- PADCONF(135, 6, 0x118, 0x260, 0x368, -1, 16, 8, 8, 0),
- PADCONF(136, 6, 0x118, 0x260, 0x368, -1, 20, 10, 10, 0),
- PADCONF(137, 6, 0x118, 0x260, 0x368, -1, 24, 12, 12, 0),
- PADCONF(138, 6, 0x118, 0x260, 0x368, -1, 28, 14, 14, 0),
- PADCONF(139, 6, 0x120, 0x260, 0x368, -1, 0, 16, 16, 0),
- PADCONF(140, 6, 0x120, 0x260, 0x368, -1, 4, 18, 18, 0),
- PADCONF(141, 5, 0x128, 0x268, 0x378, -1, 0, 0, 0, 0),
- PADCONF(142, 5, 0x128, 0x268, 0x378, -1, 4, 2, 2, 0),
- PADCONF(143, 5, 0x128, 0x268, 0x378, -1, 8, 4, 4, 0),
- PADCONF(144, 5, 0x128, 0x268, 0x378, -1, 12, 6, 6, 0),
- PADCONF(145, 5, 0x128, 0x268, 0x378, -1, 16, 8, 8, 0),
- PADCONF(146, 5, 0x128, 0x268, 0x378, -1, 20, 10, 10, 0),
- PADCONF(147, 5, 0x128, 0x268, 0x378, -1, 24, 12, 12, 0),
- PADCONF(148, 5, 0x128, 0x268, 0x378, -1, 28, 14, 14, 0),
- PADCONF(149, 7, 0x130, 0x270, -1, 0x480, 0, 0, 0, 0),
- PADCONF(150, 7, 0x130, 0x270, -1, 0x480, 4, 2, 0, 1),
- PADCONF(151, 7, 0x130, 0x270, -1, 0x480, 8, 4, 0, 2),
- PADCONF(152, 7, 0x130, 0x270, -1, 0x480, 12, 6, 0, 3),
- PADCONF(153, 7, 0x130, 0x270, -1, 0x480, 16, 8, 0, 4),
- PADCONF(154, 7, 0x130, 0x270, -1, 0x480, 20, 10, 0, 5),
- PADCONF(155, 7, 0x130, 0x270, -1, 0x480, 24, 12, 0, 6),
- PADCONF(156, 7, 0x130, 0x270, -1, 0x480, 28, 14, 0, 7),
- PADCONF(157, 7, 0x138, 0x278, -1, 0x480, 0, 0, 0, 8),
- PADCONF(158, 7, 0x138, 0x278, -1, 0x480, 4, 2, 0, 9),
- PADCONF(159, 5, 0x140, 0x280, 0x380, -1, 0, 0, 0, 0),
- PADCONF(160, 6, 0x140, 0x280, 0x380, -1, 4, 2, 2, 0),
- PADCONF(161, 5, 0x140, 0x280, 0x380, -1, 8, 4, 4, 0),
- PADCONF(162, 6, 0x140, 0x280, 0x380, -1, 12, 6, 6, 0),
- PADCONF(163, 6, 0x140, 0x280, 0x380, -1, 16, 8, 8, 0),
-};
-
-/* pin list of each pin group */
-static const unsigned int gnss_gpio_pins[] = { 119, 120, 121, 122, 123, 124,
- 125, 126, 127, 128, 22, 23, 24, 25, 26, 27, 28, 29, 30, };
-static const unsigned int lcd_vip_gpio_pins[] = { 74, 75, 76, 77, 78, 79, 80,
- 81, 82, 83, 84, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63,
- 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, };
-static const unsigned int sdio_i2s_gpio_pins[] = { 31, 32, 33, 34, 35, 36,
- 85, 86, 87, 88, 89, 90, 129, 130, 131, 132, 91, 92, 93, 94,
- 95, 96, 112, 113, 114, 115, 116, 117, 118, };
-static const unsigned int sp_rgmii_gpio_pins[] = { 97, 98, 99, 100, 101, 102,
- 103, 104, 105, 106, 107, 108, 109, 110, 111, 18, 19, 20, 21,
- 141, 142, 143, 144, 145, 146, 147, 148, };
-static const unsigned int lvds_gpio_pins[] = { 157, 158, 155, 156, 153, 154,
- 151, 152, 149, 150, };
-static const unsigned int jtag_uart_nand_gpio_pins[] = { 44, 43, 42, 41, 40,
- 39, 38, 37, 46, 47, 48, 49, 50, 52, 51, 45, 133, 134, 135,
- 136, 137, 138, 139, 140, 159, 160, 161, 162, 163, };
-static const unsigned int rtc_gpio_pins[] = { 0, 1, 2, 3, 4, 10, 11, 12, 13,
- 14, 15, 16, 17, 9, };
-static const unsigned int audio_ac97_pins[] = { 113, 118, 115, 114, };
-static const unsigned int audio_digmic_pins0[] = { 51, };
-static const unsigned int audio_digmic_pins1[] = { 122, };
-static const unsigned int audio_digmic_pins2[] = { 161, };
-static const unsigned int audio_func_dbg_pins[] = { 141, 144, 44, 43, 42, 41,
- 40, 39, 38, 37, 74, 75, 76, 77, 78, 79, 81, 113, 114, 118,
- 115, 49, 50, 142, 143, 80, };
-static const unsigned int audio_i2s_pins[] = { 118, 115, 116, 117, 112, 113,
- 114, };
-static const unsigned int audio_i2s_2ch_pins[] = { 118, 115, 112, 113, 114, };
-static const unsigned int audio_i2s_extclk_pins[] = { 112, };
-static const unsigned int audio_spdif_out_pins0[] = { 112, };
-static const unsigned int audio_spdif_out_pins1[] = { 116, };
-static const unsigned int audio_spdif_out_pins2[] = { 142, };
-static const unsigned int audio_uart0_basic_pins[] = { 143, 142, 141, 144, };
-static const unsigned int audio_uart0_urfs_pins0[] = { 117, };
-static const unsigned int audio_uart0_urfs_pins1[] = { 139, };
-static const unsigned int audio_uart0_urfs_pins2[] = { 163, };
-static const unsigned int audio_uart0_urfs_pins3[] = { 162, };
-static const unsigned int audio_uart1_basic_pins[] = { 147, 146, 145, 148, };
-static const unsigned int audio_uart1_urfs_pins0[] = { 117, };
-static const unsigned int audio_uart1_urfs_pins1[] = { 140, };
-static const unsigned int audio_uart1_urfs_pins2[] = { 163, };
-static const unsigned int audio_uart2_urfs_pins0[] = { 139, };
-static const unsigned int audio_uart2_urfs_pins1[] = { 163, };
-static const unsigned int audio_uart2_urfs_pins2[] = { 96, };
-static const unsigned int audio_uart2_urxd_pins0[] = { 20, };
-static const unsigned int audio_uart2_urxd_pins1[] = { 109, };
-static const unsigned int audio_uart2_urxd_pins2[] = { 93, };
-static const unsigned int audio_uart2_usclk_pins0[] = { 19, };
-static const unsigned int audio_uart2_usclk_pins1[] = { 101, };
-static const unsigned int audio_uart2_usclk_pins2[] = { 91, };
-static const unsigned int audio_uart2_utfs_pins0[] = { 18, };
-static const unsigned int audio_uart2_utfs_pins1[] = { 111, };
-static const unsigned int audio_uart2_utfs_pins2[] = { 94, };
-static const unsigned int audio_uart2_utxd_pins0[] = { 21, };
-static const unsigned int audio_uart2_utxd_pins1[] = { 110, };
-static const unsigned int audio_uart2_utxd_pins2[] = { 92, };
-static const unsigned int c_can_trnsvr_en_pins0[] = { 2, };
-static const unsigned int c_can_trnsvr_en_pins1[] = { 0, };
-static const unsigned int c_can_trnsvr_intr_pins[] = { 1, };
-static const unsigned int c_can_trnsvr_stb_n_pins[] = { 3, };
-static const unsigned int c0_can_rxd_trnsv0_pins[] = { 11, };
-static const unsigned int c0_can_rxd_trnsv1_pins[] = { 2, };
-static const unsigned int c0_can_txd_trnsv0_pins[] = { 10, };
-static const unsigned int c0_can_txd_trnsv1_pins[] = { 3, };
-static const unsigned int c1_can_rxd_pins0[] = { 138, };
-static const unsigned int c1_can_rxd_pins1[] = { 147, };
-static const unsigned int c1_can_rxd_pins2[] = { 2, };
-static const unsigned int c1_can_rxd_pins3[] = { 162, };
-static const unsigned int c1_can_txd_pins0[] = { 137, };
-static const unsigned int c1_can_txd_pins1[] = { 146, };
-static const unsigned int c1_can_txd_pins2[] = { 3, };
-static const unsigned int c1_can_txd_pins3[] = { 161, };
-static const unsigned int ca_audio_lpc_pins[] = { 62, 63, 64, 65, 66, 67, 68,
- 69, 70, 71, };
-static const unsigned int ca_bt_lpc_pins[] = { 85, 86, 87, 88, 89, 90, };
-static const unsigned int ca_coex_pins[] = { 129, 130, 131, 132, };
-static const unsigned int ca_curator_lpc_pins[] = { 57, 58, 59, 60, };
-static const unsigned int ca_pcm_debug_pins[] = { 91, 93, 94, 92, };
-static const unsigned int ca_pio_pins[] = { 121, 122, 125, 126, 38, 37, 47,
- 49, 50, 54, 55, 56, };
-static const unsigned int ca_sdio_debug_pins[] = { 40, 39, 44, 43, 42, 41, };
-static const unsigned int ca_spi_pins[] = { 82, 79, 80, 81, };
-static const unsigned int ca_trb_pins[] = { 91, 93, 94, 95, 96, 78, 74, 75,
- 76, 77, };
-static const unsigned int ca_uart_debug_pins[] = { 136, 135, 134, 133, };
-static const unsigned int clkc_pins0[] = { 30, 47, };
-static const unsigned int clkc_pins1[] = { 78, 54, };
-static const unsigned int gn_gnss_i2c_pins[] = { 128, 127, };
-static const unsigned int gn_gnss_uart_nopause_pins[] = { 134, 133, };
-static const unsigned int gn_gnss_uart_pins[] = { 134, 133, 136, 135, };
-static const unsigned int gn_trg_spi_pins0[] = { 22, 25, 23, 24, };
-static const unsigned int gn_trg_spi_pins1[] = { 82, 79, 80, 81, };
-static const unsigned int cvbs_dbg_pins[] = { 54, 53, 82, 74, 75, 76, 77, 78,
- 79, 80, 81, 83, 84, 73, 55, 56, };
-static const unsigned int cvbs_dbg_test_pins0[] = { 57, };
-static const unsigned int cvbs_dbg_test_pins1[] = { 58, };
-static const unsigned int cvbs_dbg_test_pins2[] = { 59, };
-static const unsigned int cvbs_dbg_test_pins3[] = { 60, };
-static const unsigned int cvbs_dbg_test_pins4[] = { 61, };
-static const unsigned int cvbs_dbg_test_pins5[] = { 62, };
-static const unsigned int cvbs_dbg_test_pins6[] = { 63, };
-static const unsigned int cvbs_dbg_test_pins7[] = { 64, };
-static const unsigned int cvbs_dbg_test_pins8[] = { 65, };
-static const unsigned int cvbs_dbg_test_pins9[] = { 66, };
-static const unsigned int cvbs_dbg_test_pins10[] = { 67, };
-static const unsigned int cvbs_dbg_test_pins11[] = { 68, };
-static const unsigned int cvbs_dbg_test_pins12[] = { 69, };
-static const unsigned int cvbs_dbg_test_pins13[] = { 70, };
-static const unsigned int cvbs_dbg_test_pins14[] = { 71, };
-static const unsigned int cvbs_dbg_test_pins15[] = { 72, };
-static const unsigned int gn_gnss_power_pins[] = { 123, 124, 121, 122, 125,
- 120, };
-static const unsigned int gn_gnss_sw_status_pins[] = { 57, 58, 59, 60, 61,
- 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 53, 55, 56, 54, };
-static const unsigned int gn_gnss_eclk_pins[] = { 113, };
-static const unsigned int gn_gnss_irq1_pins0[] = { 112, };
-static const unsigned int gn_gnss_irq2_pins0[] = { 118, };
-static const unsigned int gn_gnss_tm_pins[] = { 115, };
-static const unsigned int gn_gnss_tsync_pins[] = { 114, };
-static const unsigned int gn_io_gnsssys_sw_cfg_pins[] = { 44, 43, 42, 41, 40,
- 39, 38, 37, 49, 50, 91, 92, 93, 94, 95, 96, };
-static const unsigned int gn_trg_pins0[] = { 29, 28, 26, 27, };
-static const unsigned int gn_trg_pins1[] = { 77, 76, 74, 75, };
-static const unsigned int gn_trg_shutdown_pins0[] = { 30, };
-static const unsigned int gn_trg_shutdown_pins1[] = { 83, };
-static const unsigned int gn_trg_shutdown_pins2[] = { 117, };
-static const unsigned int gn_trg_shutdown_pins3[] = { 123, };
-static const unsigned int i2c0_pins[] = { 128, 127, };
-static const unsigned int i2c1_pins[] = { 126, 125, };
-static const unsigned int i2s0_pins[] = { 91, 93, 94, 92, };
-static const unsigned int i2s1_basic_pins[] = { 95, 96, };
-static const unsigned int i2s1_rxd0_pins0[] = { 61, };
-static const unsigned int i2s1_rxd0_pins1[] = { 131, };
-static const unsigned int i2s1_rxd0_pins2[] = { 129, };
-static const unsigned int i2s1_rxd0_pins3[] = { 117, };
-static const unsigned int i2s1_rxd0_pins4[] = { 83, };
-static const unsigned int i2s1_rxd1_pins0[] = { 72, };
-static const unsigned int i2s1_rxd1_pins1[] = { 132, };
-static const unsigned int i2s1_rxd1_pins2[] = { 130, };
-static const unsigned int i2s1_rxd1_pins3[] = { 118, };
-static const unsigned int i2s1_rxd1_pins4[] = { 84, };
-static const unsigned int jtag_jt_dbg_nsrst_pins[] = { 125, };
-static const unsigned int jtag_ntrst_pins0[] = { 4, };
-static const unsigned int jtag_ntrst_pins1[] = { 163, };
-static const unsigned int jtag_swdiotms_pins0[] = { 2, };
-static const unsigned int jtag_swdiotms_pins1[] = { 160, };
-static const unsigned int jtag_tck_pins0[] = { 0, };
-static const unsigned int jtag_tck_pins1[] = { 161, };
-static const unsigned int jtag_tdi_pins0[] = { 1, };
-static const unsigned int jtag_tdi_pins1[] = { 162, };
-static const unsigned int jtag_tdo_pins0[] = { 3, };
-static const unsigned int jtag_tdo_pins1[] = { 159, };
-static const unsigned int ks_kas_spi_pins0[] = { 141, 144, 143, 142, };
-static const unsigned int ld_ldd_pins[] = { 57, 58, 59, 60, 61, 62, 63, 64,
- 65, 66, 67, 68, 69, 70, 71, 72, 74, 75, 76, 77, 78, 79, 80,
- 81, 56, 53, };
-static const unsigned int ld_ldd_16bit_pins[] = { 57, 58, 59, 60, 61, 62, 63,
- 64, 65, 66, 67, 68, 69, 70, 71, 72, 56, 53, };
-static const unsigned int ld_ldd_fck_pins[] = { 55, };
-static const unsigned int ld_ldd_lck_pins[] = { 54, };
-static const unsigned int lr_lcdrom_pins[] = { 73, 54, 57, 58, 59, 60, 61,
- 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 56, 53, 55, };
-static const unsigned int lvds_analog_pins[] = { 149, 150, 151, 152, 153, 154,
- 155, 156, 157, 158, };
-static const unsigned int nd_df_basic_pins[] = { 44, 43, 42, 41, 40, 39, 38,
- 37, 47, 46, 52, 45, 49, 50, 48, };
-static const unsigned int nd_df_wp_pins[] = { 124, };
-static const unsigned int nd_df_cs_pins[] = { 51, };
-static const unsigned int ps_pins[] = { 120, 119, 121, };
-static const unsigned int ps_no_dir_pins[] = { 119, };
-static const unsigned int pwc_core_on_pins[] = { 8, };
-static const unsigned int pwc_ext_on_pins[] = { 6, };
-static const unsigned int pwc_gpio3_clk_pins[] = { 3, };
-static const unsigned int pwc_io_on_pins[] = { 9, };
-static const unsigned int pwc_lowbatt_b_pins0[] = { 4, };
-static const unsigned int pwc_mem_on_pins[] = { 7, };
-static const unsigned int pwc_on_key_b_pins0[] = { 5, };
-static const unsigned int pwc_wakeup_src0_pins[] = { 0, };
-static const unsigned int pwc_wakeup_src1_pins[] = { 1, };
-static const unsigned int pwc_wakeup_src2_pins[] = { 2, };
-static const unsigned int pwc_wakeup_src3_pins[] = { 3, };
-static const unsigned int pw_cko0_pins0[] = { 123, };
-static const unsigned int pw_cko0_pins1[] = { 101, };
-static const unsigned int pw_cko0_pins2[] = { 82, };
-static const unsigned int pw_cko0_pins3[] = { 162, };
-static const unsigned int pw_cko1_pins0[] = { 124, };
-static const unsigned int pw_cko1_pins1[] = { 110, };
-static const unsigned int pw_cko1_pins2[] = { 163, };
-static const unsigned int pw_i2s01_clk_pins0[] = { 125, };
-static const unsigned int pw_i2s01_clk_pins1[] = { 117, };
-static const unsigned int pw_i2s01_clk_pins2[] = { 132, };
-static const unsigned int pw_pwm0_pins0[] = { 119, };
-static const unsigned int pw_pwm0_pins1[] = { 159, };
-static const unsigned int pw_pwm1_pins0[] = { 120, };
-static const unsigned int pw_pwm1_pins1[] = { 160, };
-static const unsigned int pw_pwm1_pins2[] = { 131, };
-static const unsigned int pw_pwm2_pins0[] = { 121, };
-static const unsigned int pw_pwm2_pins1[] = { 98, };
-static const unsigned int pw_pwm2_pins2[] = { 161, };
-static const unsigned int pw_pwm3_pins0[] = { 122, };
-static const unsigned int pw_pwm3_pins1[] = { 73, };
-static const unsigned int pw_pwm_cpu_vol_pins0[] = { 121, };
-static const unsigned int pw_pwm_cpu_vol_pins1[] = { 98, };
-static const unsigned int pw_pwm_cpu_vol_pins2[] = { 161, };
-static const unsigned int pw_backlight_pins0[] = { 122, };
-static const unsigned int pw_backlight_pins1[] = { 73, };
-static const unsigned int rg_eth_mac_pins[] = { 108, 103, 104, 105, 106, 107,
- 102, 97, 98, 99, 100, 101, };
-static const unsigned int rg_gmac_phy_intr_n_pins[] = { 111, };
-static const unsigned int rg_rgmii_mac_pins[] = { 109, 110, };
-static const unsigned int rg_rgmii_phy_ref_clk_pins0[] = { 111, };
-static const unsigned int rg_rgmii_phy_ref_clk_pins1[] = { 53, };
-static const unsigned int sd0_pins[] = { 46, 47, 44, 43, 42, 41, 40, 39, 38,
- 37, };
-static const unsigned int sd0_4bit_pins[] = { 46, 47, 44, 43, 42, 41, };
-static const unsigned int sd1_pins[] = { 48, 49, 44, 43, 42, 41, 40, 39, 38,
- 37, };
-static const unsigned int sd1_4bit_pins0[] = { 48, 49, 44, 43, 42, 41, };
-static const unsigned int sd1_4bit_pins1[] = { 48, 49, 40, 39, 38, 37, };
-static const unsigned int sd2_basic_pins[] = { 31, 32, 33, 34, 35, 36, };
-static const unsigned int sd2_cdb_pins0[] = { 124, };
-static const unsigned int sd2_cdb_pins1[] = { 161, };
-static const unsigned int sd2_wpb_pins0[] = { 123, };
-static const unsigned int sd2_wpb_pins1[] = { 163, };
-static const unsigned int sd3_9_pins[] = { 85, 86, 87, 88, 89, 90, };
-static const unsigned int sd5_pins[] = { 91, 92, 93, 94, 95, 96, };
-static const unsigned int sd6_pins0[] = { 79, 78, 74, 75, 76, 77, };
-static const unsigned int sd6_pins1[] = { 101, 99, 100, 110, 109, 111, };
-static const unsigned int sp0_ext_ldo_on_pins[] = { 4, };
-static const unsigned int sp0_qspi_pins[] = { 12, 13, 14, 15, 16, 17, };
-static const unsigned int sp1_spi_pins[] = { 19, 20, 21, 18, };
-static const unsigned int tpiu_trace_pins[] = { 53, 56, 57, 58, 59, 60, 61,
- 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, };
-static const unsigned int uart0_pins[] = { 121, 120, 134, 133, };
-static const unsigned int uart0_nopause_pins[] = { 134, 133, };
-static const unsigned int uart1_pins[] = { 136, 135, };
-static const unsigned int uart2_cts_pins0[] = { 132, };
-static const unsigned int uart2_cts_pins1[] = { 162, };
-static const unsigned int uart2_rts_pins0[] = { 131, };
-static const unsigned int uart2_rts_pins1[] = { 161, };
-static const unsigned int uart2_rxd_pins0[] = { 11, };
-static const unsigned int uart2_rxd_pins1[] = { 160, };
-static const unsigned int uart2_rxd_pins2[] = { 130, };
-static const unsigned int uart2_txd_pins0[] = { 10, };
-static const unsigned int uart2_txd_pins1[] = { 159, };
-static const unsigned int uart2_txd_pins2[] = { 129, };
-static const unsigned int uart3_cts_pins0[] = { 125, };
-static const unsigned int uart3_cts_pins1[] = { 111, };
-static const unsigned int uart3_cts_pins2[] = { 140, };
-static const unsigned int uart3_rts_pins0[] = { 126, };
-static const unsigned int uart3_rts_pins1[] = { 109, };
-static const unsigned int uart3_rts_pins2[] = { 139, };
-static const unsigned int uart3_rxd_pins0[] = { 138, };
-static const unsigned int uart3_rxd_pins1[] = { 84, };
-static const unsigned int uart3_rxd_pins2[] = { 162, };
-static const unsigned int uart3_txd_pins0[] = { 137, };
-static const unsigned int uart3_txd_pins1[] = { 83, };
-static const unsigned int uart3_txd_pins2[] = { 161, };
-static const unsigned int uart4_basic_pins[] = { 140, 139, };
-static const unsigned int uart4_cts_pins0[] = { 122, };
-static const unsigned int uart4_cts_pins1[] = { 100, };
-static const unsigned int uart4_cts_pins2[] = { 117, };
-static const unsigned int uart4_rts_pins0[] = { 123, };
-static const unsigned int uart4_rts_pins1[] = { 99, };
-static const unsigned int uart4_rts_pins2[] = { 116, };
-static const unsigned int usb0_drvvbus_pins0[] = { 51, };
-static const unsigned int usb0_drvvbus_pins1[] = { 162, };
-static const unsigned int usb1_drvvbus_pins0[] = { 134, };
-static const unsigned int usb1_drvvbus_pins1[] = { 163, };
-static const unsigned int visbus_dout_pins[] = { 57, 58, 59, 60, 61, 62, 63,
- 64, 65, 66, 67, 68, 69, 70, 71, 72, 53, 54, 55, 56, 85, 86,
- 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, };
-static const unsigned int vi_vip1_pins[] = { 74, 75, 76, 77, 78, 79, 80, 81,
- 82, 83, 84, 103, 104, 105, 106, 107, 102, 97, 98, };
-static const unsigned int vi_vip1_ext_pins[] = { 74, 75, 76, 77, 78, 79, 80,
- 81, 82, 83, 84, 108, 103, 104, 105, 106, 107, 102, 97, 98,
- 99, 100, };
-static const unsigned int vi_vip1_low8bit_pins[] = { 74, 75, 76, 77, 78, 79,
- 80, 81, 82, 83, 84, };
-static const unsigned int vi_vip1_high8bit_pins[] = { 82, 83, 84, 103, 104,
- 105, 106, 107, 102, 97, 98, };
-
-/* definition of pin group table */
-static struct atlas7_pin_group altas7_pin_groups[] = {
- GROUP("gnss_gpio_grp", gnss_gpio_pins),
- GROUP("lcd_vip_gpio_grp", lcd_vip_gpio_pins),
- GROUP("sdio_i2s_gpio_grp", sdio_i2s_gpio_pins),
- GROUP("sp_rgmii_gpio_grp", sp_rgmii_gpio_pins),
- GROUP("lvds_gpio_grp", lvds_gpio_pins),
- GROUP("jtag_uart_nand_gpio_grp", jtag_uart_nand_gpio_pins),
- GROUP("rtc_gpio_grp", rtc_gpio_pins),
- GROUP("audio_ac97_grp", audio_ac97_pins),
- GROUP("audio_digmic_grp0", audio_digmic_pins0),
- GROUP("audio_digmic_grp1", audio_digmic_pins1),
- GROUP("audio_digmic_grp2", audio_digmic_pins2),
- GROUP("audio_func_dbg_grp", audio_func_dbg_pins),
- GROUP("audio_i2s_grp", audio_i2s_pins),
- GROUP("audio_i2s_2ch_grp", audio_i2s_2ch_pins),
- GROUP("audio_i2s_extclk_grp", audio_i2s_extclk_pins),
- GROUP("audio_spdif_out_grp0", audio_spdif_out_pins0),
- GROUP("audio_spdif_out_grp1", audio_spdif_out_pins1),
- GROUP("audio_spdif_out_grp2", audio_spdif_out_pins2),
- GROUP("audio_uart0_basic_grp", audio_uart0_basic_pins),
- GROUP("audio_uart0_urfs_grp0", audio_uart0_urfs_pins0),
- GROUP("audio_uart0_urfs_grp1", audio_uart0_urfs_pins1),
- GROUP("audio_uart0_urfs_grp2", audio_uart0_urfs_pins2),
- GROUP("audio_uart0_urfs_grp3", audio_uart0_urfs_pins3),
- GROUP("audio_uart1_basic_grp", audio_uart1_basic_pins),
- GROUP("audio_uart1_urfs_grp0", audio_uart1_urfs_pins0),
- GROUP("audio_uart1_urfs_grp1", audio_uart1_urfs_pins1),
- GROUP("audio_uart1_urfs_grp2", audio_uart1_urfs_pins2),
- GROUP("audio_uart2_urfs_grp0", audio_uart2_urfs_pins0),
- GROUP("audio_uart2_urfs_grp1", audio_uart2_urfs_pins1),
- GROUP("audio_uart2_urfs_grp2", audio_uart2_urfs_pins2),
- GROUP("audio_uart2_urxd_grp0", audio_uart2_urxd_pins0),
- GROUP("audio_uart2_urxd_grp1", audio_uart2_urxd_pins1),
- GROUP("audio_uart2_urxd_grp2", audio_uart2_urxd_pins2),
- GROUP("audio_uart2_usclk_grp0", audio_uart2_usclk_pins0),
- GROUP("audio_uart2_usclk_grp1", audio_uart2_usclk_pins1),
- GROUP("audio_uart2_usclk_grp2", audio_uart2_usclk_pins2),
- GROUP("audio_uart2_utfs_grp0", audio_uart2_utfs_pins0),
- GROUP("audio_uart2_utfs_grp1", audio_uart2_utfs_pins1),
- GROUP("audio_uart2_utfs_grp2", audio_uart2_utfs_pins2),
- GROUP("audio_uart2_utxd_grp0", audio_uart2_utxd_pins0),
- GROUP("audio_uart2_utxd_grp1", audio_uart2_utxd_pins1),
- GROUP("audio_uart2_utxd_grp2", audio_uart2_utxd_pins2),
- GROUP("c_can_trnsvr_en_grp0", c_can_trnsvr_en_pins0),
- GROUP("c_can_trnsvr_en_grp1", c_can_trnsvr_en_pins1),
- GROUP("c_can_trnsvr_intr_grp", c_can_trnsvr_intr_pins),
- GROUP("c_can_trnsvr_stb_n_grp", c_can_trnsvr_stb_n_pins),
- GROUP("c0_can_rxd_trnsv0_grp", c0_can_rxd_trnsv0_pins),
- GROUP("c0_can_rxd_trnsv1_grp", c0_can_rxd_trnsv1_pins),
- GROUP("c0_can_txd_trnsv0_grp", c0_can_txd_trnsv0_pins),
- GROUP("c0_can_txd_trnsv1_grp", c0_can_txd_trnsv1_pins),
- GROUP("c1_can_rxd_grp0", c1_can_rxd_pins0),
- GROUP("c1_can_rxd_grp1", c1_can_rxd_pins1),
- GROUP("c1_can_rxd_grp2", c1_can_rxd_pins2),
- GROUP("c1_can_rxd_grp3", c1_can_rxd_pins3),
- GROUP("c1_can_txd_grp0", c1_can_txd_pins0),
- GROUP("c1_can_txd_grp1", c1_can_txd_pins1),
- GROUP("c1_can_txd_grp2", c1_can_txd_pins2),
- GROUP("c1_can_txd_grp3", c1_can_txd_pins3),
- GROUP("ca_audio_lpc_grp", ca_audio_lpc_pins),
- GROUP("ca_bt_lpc_grp", ca_bt_lpc_pins),
- GROUP("ca_coex_grp", ca_coex_pins),
- GROUP("ca_curator_lpc_grp", ca_curator_lpc_pins),
- GROUP("ca_pcm_debug_grp", ca_pcm_debug_pins),
- GROUP("ca_pio_grp", ca_pio_pins),
- GROUP("ca_sdio_debug_grp", ca_sdio_debug_pins),
- GROUP("ca_spi_grp", ca_spi_pins),
- GROUP("ca_trb_grp", ca_trb_pins),
- GROUP("ca_uart_debug_grp", ca_uart_debug_pins),
- GROUP("clkc_grp0", clkc_pins0),
- GROUP("clkc_grp1", clkc_pins1),
- GROUP("gn_gnss_i2c_grp", gn_gnss_i2c_pins),
- GROUP("gn_gnss_uart_nopause_grp", gn_gnss_uart_nopause_pins),
- GROUP("gn_gnss_uart_grp", gn_gnss_uart_pins),
- GROUP("gn_trg_spi_grp0", gn_trg_spi_pins0),
- GROUP("gn_trg_spi_grp1", gn_trg_spi_pins1),
- GROUP("cvbs_dbg_grp", cvbs_dbg_pins),
- GROUP("cvbs_dbg_test_grp0", cvbs_dbg_test_pins0),
- GROUP("cvbs_dbg_test_grp1", cvbs_dbg_test_pins1),
- GROUP("cvbs_dbg_test_grp2", cvbs_dbg_test_pins2),
- GROUP("cvbs_dbg_test_grp3", cvbs_dbg_test_pins3),
- GROUP("cvbs_dbg_test_grp4", cvbs_dbg_test_pins4),
- GROUP("cvbs_dbg_test_grp5", cvbs_dbg_test_pins5),
- GROUP("cvbs_dbg_test_grp6", cvbs_dbg_test_pins6),
- GROUP("cvbs_dbg_test_grp7", cvbs_dbg_test_pins7),
- GROUP("cvbs_dbg_test_grp8", cvbs_dbg_test_pins8),
- GROUP("cvbs_dbg_test_grp9", cvbs_dbg_test_pins9),
- GROUP("cvbs_dbg_test_grp10", cvbs_dbg_test_pins10),
- GROUP("cvbs_dbg_test_grp11", cvbs_dbg_test_pins11),
- GROUP("cvbs_dbg_test_grp12", cvbs_dbg_test_pins12),
- GROUP("cvbs_dbg_test_grp13", cvbs_dbg_test_pins13),
- GROUP("cvbs_dbg_test_grp14", cvbs_dbg_test_pins14),
- GROUP("cvbs_dbg_test_grp15", cvbs_dbg_test_pins15),
- GROUP("gn_gnss_power_grp", gn_gnss_power_pins),
- GROUP("gn_gnss_sw_status_grp", gn_gnss_sw_status_pins),
- GROUP("gn_gnss_eclk_grp", gn_gnss_eclk_pins),
- GROUP("gn_gnss_irq1_grp0", gn_gnss_irq1_pins0),
- GROUP("gn_gnss_irq2_grp0", gn_gnss_irq2_pins0),
- GROUP("gn_gnss_tm_grp", gn_gnss_tm_pins),
- GROUP("gn_gnss_tsync_grp", gn_gnss_tsync_pins),
- GROUP("gn_io_gnsssys_sw_cfg_grp", gn_io_gnsssys_sw_cfg_pins),
- GROUP("gn_trg_grp0", gn_trg_pins0),
- GROUP("gn_trg_grp1", gn_trg_pins1),
- GROUP("gn_trg_shutdown_grp0", gn_trg_shutdown_pins0),
- GROUP("gn_trg_shutdown_grp1", gn_trg_shutdown_pins1),
- GROUP("gn_trg_shutdown_grp2", gn_trg_shutdown_pins2),
- GROUP("gn_trg_shutdown_grp3", gn_trg_shutdown_pins3),
- GROUP("i2c0_grp", i2c0_pins),
- GROUP("i2c1_grp", i2c1_pins),
- GROUP("i2s0_grp", i2s0_pins),
- GROUP("i2s1_basic_grp", i2s1_basic_pins),
- GROUP("i2s1_rxd0_grp0", i2s1_rxd0_pins0),
- GROUP("i2s1_rxd0_grp1", i2s1_rxd0_pins1),
- GROUP("i2s1_rxd0_grp2", i2s1_rxd0_pins2),
- GROUP("i2s1_rxd0_grp3", i2s1_rxd0_pins3),
- GROUP("i2s1_rxd0_grp4", i2s1_rxd0_pins4),
- GROUP("i2s1_rxd1_grp0", i2s1_rxd1_pins0),
- GROUP("i2s1_rxd1_grp1", i2s1_rxd1_pins1),
- GROUP("i2s1_rxd1_grp2", i2s1_rxd1_pins2),
- GROUP("i2s1_rxd1_grp3", i2s1_rxd1_pins3),
- GROUP("i2s1_rxd1_grp4", i2s1_rxd1_pins4),
- GROUP("jtag_jt_dbg_nsrst_grp", jtag_jt_dbg_nsrst_pins),
- GROUP("jtag_ntrst_grp0", jtag_ntrst_pins0),
- GROUP("jtag_ntrst_grp1", jtag_ntrst_pins1),
- GROUP("jtag_swdiotms_grp0", jtag_swdiotms_pins0),
- GROUP("jtag_swdiotms_grp1", jtag_swdiotms_pins1),
- GROUP("jtag_tck_grp0", jtag_tck_pins0),
- GROUP("jtag_tck_grp1", jtag_tck_pins1),
- GROUP("jtag_tdi_grp0", jtag_tdi_pins0),
- GROUP("jtag_tdi_grp1", jtag_tdi_pins1),
- GROUP("jtag_tdo_grp0", jtag_tdo_pins0),
- GROUP("jtag_tdo_grp1", jtag_tdo_pins1),
- GROUP("ks_kas_spi_grp0", ks_kas_spi_pins0),
- GROUP("ld_ldd_grp", ld_ldd_pins),
- GROUP("ld_ldd_16bit_grp", ld_ldd_16bit_pins),
- GROUP("ld_ldd_fck_grp", ld_ldd_fck_pins),
- GROUP("ld_ldd_lck_grp", ld_ldd_lck_pins),
- GROUP("lr_lcdrom_grp", lr_lcdrom_pins),
- GROUP("lvds_analog_grp", lvds_analog_pins),
- GROUP("nd_df_basic_grp", nd_df_basic_pins),
- GROUP("nd_df_wp_grp", nd_df_wp_pins),
- GROUP("nd_df_cs_grp", nd_df_cs_pins),
- GROUP("ps_grp", ps_pins),
- GROUP("ps_no_dir_grp", ps_no_dir_pins),
- GROUP("pwc_core_on_grp", pwc_core_on_pins),
- GROUP("pwc_ext_on_grp", pwc_ext_on_pins),
- GROUP("pwc_gpio3_clk_grp", pwc_gpio3_clk_pins),
- GROUP("pwc_io_on_grp", pwc_io_on_pins),
- GROUP("pwc_lowbatt_b_grp0", pwc_lowbatt_b_pins0),
- GROUP("pwc_mem_on_grp", pwc_mem_on_pins),
- GROUP("pwc_on_key_b_grp0", pwc_on_key_b_pins0),
- GROUP("pwc_wakeup_src0_grp", pwc_wakeup_src0_pins),
- GROUP("pwc_wakeup_src1_grp", pwc_wakeup_src1_pins),
- GROUP("pwc_wakeup_src2_grp", pwc_wakeup_src2_pins),
- GROUP("pwc_wakeup_src3_grp", pwc_wakeup_src3_pins),
- GROUP("pw_cko0_grp0", pw_cko0_pins0),
- GROUP("pw_cko0_grp1", pw_cko0_pins1),
- GROUP("pw_cko0_grp2", pw_cko0_pins2),
- GROUP("pw_cko0_grp3", pw_cko0_pins3),
- GROUP("pw_cko1_grp0", pw_cko1_pins0),
- GROUP("pw_cko1_grp1", pw_cko1_pins1),
- GROUP("pw_cko1_grp2", pw_cko1_pins2),
- GROUP("pw_i2s01_clk_grp0", pw_i2s01_clk_pins0),
- GROUP("pw_i2s01_clk_grp1", pw_i2s01_clk_pins1),
- GROUP("pw_i2s01_clk_grp2", pw_i2s01_clk_pins2),
- GROUP("pw_pwm0_grp0", pw_pwm0_pins0),
- GROUP("pw_pwm0_grp1", pw_pwm0_pins1),
- GROUP("pw_pwm1_grp0", pw_pwm1_pins0),
- GROUP("pw_pwm1_grp1", pw_pwm1_pins1),
- GROUP("pw_pwm1_grp2", pw_pwm1_pins2),
- GROUP("pw_pwm2_grp0", pw_pwm2_pins0),
- GROUP("pw_pwm2_grp1", pw_pwm2_pins1),
- GROUP("pw_pwm2_grp2", pw_pwm2_pins2),
- GROUP("pw_pwm3_grp0", pw_pwm3_pins0),
- GROUP("pw_pwm3_grp1", pw_pwm3_pins1),
- GROUP("pw_pwm_cpu_vol_grp0", pw_pwm_cpu_vol_pins0),
- GROUP("pw_pwm_cpu_vol_grp1", pw_pwm_cpu_vol_pins1),
- GROUP("pw_pwm_cpu_vol_grp2", pw_pwm_cpu_vol_pins2),
- GROUP("pw_backlight_grp0", pw_backlight_pins0),
- GROUP("pw_backlight_grp1", pw_backlight_pins1),
- GROUP("rg_eth_mac_grp", rg_eth_mac_pins),
- GROUP("rg_gmac_phy_intr_n_grp", rg_gmac_phy_intr_n_pins),
- GROUP("rg_rgmii_mac_grp", rg_rgmii_mac_pins),
- GROUP("rg_rgmii_phy_ref_clk_grp0", rg_rgmii_phy_ref_clk_pins0),
- GROUP("rg_rgmii_phy_ref_clk_grp1", rg_rgmii_phy_ref_clk_pins1),
- GROUP("sd0_grp", sd0_pins),
- GROUP("sd0_4bit_grp", sd0_4bit_pins),
- GROUP("sd1_grp", sd1_pins),
- GROUP("sd1_4bit_grp0", sd1_4bit_pins0),
- GROUP("sd1_4bit_grp1", sd1_4bit_pins1),
- GROUP("sd2_basic_grp", sd2_basic_pins),
- GROUP("sd2_cdb_grp0", sd2_cdb_pins0),
- GROUP("sd2_cdb_grp1", sd2_cdb_pins1),
- GROUP("sd2_wpb_grp0", sd2_wpb_pins0),
- GROUP("sd2_wpb_grp1", sd2_wpb_pins1),
- GROUP("sd3_9_grp", sd3_9_pins),
- GROUP("sd5_grp", sd5_pins),
- GROUP("sd6_grp0", sd6_pins0),
- GROUP("sd6_grp1", sd6_pins1),
- GROUP("sp0_ext_ldo_on_grp", sp0_ext_ldo_on_pins),
- GROUP("sp0_qspi_grp", sp0_qspi_pins),
- GROUP("sp1_spi_grp", sp1_spi_pins),
- GROUP("tpiu_trace_grp", tpiu_trace_pins),
- GROUP("uart0_grp", uart0_pins),
- GROUP("uart0_nopause_grp", uart0_nopause_pins),
- GROUP("uart1_grp", uart1_pins),
- GROUP("uart2_cts_grp0", uart2_cts_pins0),
- GROUP("uart2_cts_grp1", uart2_cts_pins1),
- GROUP("uart2_rts_grp0", uart2_rts_pins0),
- GROUP("uart2_rts_grp1", uart2_rts_pins1),
- GROUP("uart2_rxd_grp0", uart2_rxd_pins0),
- GROUP("uart2_rxd_grp1", uart2_rxd_pins1),
- GROUP("uart2_rxd_grp2", uart2_rxd_pins2),
- GROUP("uart2_txd_grp0", uart2_txd_pins0),
- GROUP("uart2_txd_grp1", uart2_txd_pins1),
- GROUP("uart2_txd_grp2", uart2_txd_pins2),
- GROUP("uart3_cts_grp0", uart3_cts_pins0),
- GROUP("uart3_cts_grp1", uart3_cts_pins1),
- GROUP("uart3_cts_grp2", uart3_cts_pins2),
- GROUP("uart3_rts_grp0", uart3_rts_pins0),
- GROUP("uart3_rts_grp1", uart3_rts_pins1),
- GROUP("uart3_rts_grp2", uart3_rts_pins2),
- GROUP("uart3_rxd_grp0", uart3_rxd_pins0),
- GROUP("uart3_rxd_grp1", uart3_rxd_pins1),
- GROUP("uart3_rxd_grp2", uart3_rxd_pins2),
- GROUP("uart3_txd_grp0", uart3_txd_pins0),
- GROUP("uart3_txd_grp1", uart3_txd_pins1),
- GROUP("uart3_txd_grp2", uart3_txd_pins2),
- GROUP("uart4_basic_grp", uart4_basic_pins),
- GROUP("uart4_cts_grp0", uart4_cts_pins0),
- GROUP("uart4_cts_grp1", uart4_cts_pins1),
- GROUP("uart4_cts_grp2", uart4_cts_pins2),
- GROUP("uart4_rts_grp0", uart4_rts_pins0),
- GROUP("uart4_rts_grp1", uart4_rts_pins1),
- GROUP("uart4_rts_grp2", uart4_rts_pins2),
- GROUP("usb0_drvvbus_grp0", usb0_drvvbus_pins0),
- GROUP("usb0_drvvbus_grp1", usb0_drvvbus_pins1),
- GROUP("usb1_drvvbus_grp0", usb1_drvvbus_pins0),
- GROUP("usb1_drvvbus_grp1", usb1_drvvbus_pins1),
- GROUP("visbus_dout_grp", visbus_dout_pins),
- GROUP("vi_vip1_grp", vi_vip1_pins),
- GROUP("vi_vip1_ext_grp", vi_vip1_ext_pins),
- GROUP("vi_vip1_low8bit_grp", vi_vip1_low8bit_pins),
- GROUP("vi_vip1_high8bit_grp", vi_vip1_high8bit_pins),
-};
-
-/* How many groups that a function can use */
-static const char * const gnss_gpio_grp[] = { "gnss_gpio_grp", };
-static const char * const lcd_vip_gpio_grp[] = { "lcd_vip_gpio_grp", };
-static const char * const sdio_i2s_gpio_grp[] = { "sdio_i2s_gpio_grp", };
-static const char * const sp_rgmii_gpio_grp[] = { "sp_rgmii_gpio_grp", };
-static const char * const lvds_gpio_grp[] = { "lvds_gpio_grp", };
-static const char * const jtag_uart_nand_gpio_grp[] = {
- "jtag_uart_nand_gpio_grp", };
-static const char * const rtc_gpio_grp[] = { "rtc_gpio_grp", };
-static const char * const audio_ac97_grp[] = { "audio_ac97_grp", };
-static const char * const audio_digmic_grp0[] = { "audio_digmic_grp0", };
-static const char * const audio_digmic_grp1[] = { "audio_digmic_grp1", };
-static const char * const audio_digmic_grp2[] = { "audio_digmic_grp2", };
-static const char * const audio_func_dbg_grp[] = { "audio_func_dbg_grp", };
-static const char * const audio_i2s_grp[] = { "audio_i2s_grp", };
-static const char * const audio_i2s_2ch_grp[] = { "audio_i2s_2ch_grp", };
-static const char * const audio_i2s_extclk_grp[] = { "audio_i2s_extclk_grp", };
-static const char * const audio_spdif_out_grp0[] = { "audio_spdif_out_grp0", };
-static const char * const audio_spdif_out_grp1[] = { "audio_spdif_out_grp1", };
-static const char * const audio_spdif_out_grp2[] = { "audio_spdif_out_grp2", };
-static const char * const audio_uart0_basic_grp[] = {
- "audio_uart0_basic_grp", };
-static const char * const audio_uart0_urfs_grp0[] = {
- "audio_uart0_urfs_grp0", };
-static const char * const audio_uart0_urfs_grp1[] = {
- "audio_uart0_urfs_grp1", };
-static const char * const audio_uart0_urfs_grp2[] = {
- "audio_uart0_urfs_grp2", };
-static const char * const audio_uart0_urfs_grp3[] = {
- "audio_uart0_urfs_grp3", };
-static const char * const audio_uart1_basic_grp[] = {
- "audio_uart1_basic_grp", };
-static const char * const audio_uart1_urfs_grp0[] = {
- "audio_uart1_urfs_grp0", };
-static const char * const audio_uart1_urfs_grp1[] = {
- "audio_uart1_urfs_grp1", };
-static const char * const audio_uart1_urfs_grp2[] = {
- "audio_uart1_urfs_grp2", };
-static const char * const audio_uart2_urfs_grp0[] = {
- "audio_uart2_urfs_grp0", };
-static const char * const audio_uart2_urfs_grp1[] = {
- "audio_uart2_urfs_grp1", };
-static const char * const audio_uart2_urfs_grp2[] = {
- "audio_uart2_urfs_grp2", };
-static const char * const audio_uart2_urxd_grp0[] = {
- "audio_uart2_urxd_grp0", };
-static const char * const audio_uart2_urxd_grp1[] = {
- "audio_uart2_urxd_grp1", };
-static const char * const audio_uart2_urxd_grp2[] = {
- "audio_uart2_urxd_grp2", };
-static const char * const audio_uart2_usclk_grp0[] = {
- "audio_uart2_usclk_grp0", };
-static const char * const audio_uart2_usclk_grp1[] = {
- "audio_uart2_usclk_grp1", };
-static const char * const audio_uart2_usclk_grp2[] = {
- "audio_uart2_usclk_grp2", };
-static const char * const audio_uart2_utfs_grp0[] = {
- "audio_uart2_utfs_grp0", };
-static const char * const audio_uart2_utfs_grp1[] = {
- "audio_uart2_utfs_grp1", };
-static const char * const audio_uart2_utfs_grp2[] = {
- "audio_uart2_utfs_grp2", };
-static const char * const audio_uart2_utxd_grp0[] = {
- "audio_uart2_utxd_grp0", };
-static const char * const audio_uart2_utxd_grp1[] = {
- "audio_uart2_utxd_grp1", };
-static const char * const audio_uart2_utxd_grp2[] = {
- "audio_uart2_utxd_grp2", };
-static const char * const c_can_trnsvr_en_grp0[] = { "c_can_trnsvr_en_grp0", };
-static const char * const c_can_trnsvr_en_grp1[] = { "c_can_trnsvr_en_grp1", };
-static const char * const c_can_trnsvr_intr_grp[] = {
- "c_can_trnsvr_intr_grp", };
-static const char * const c_can_trnsvr_stb_n_grp[] = {
- "c_can_trnsvr_stb_n_grp", };
-static const char * const c0_can_rxd_trnsv0_grp[] = {
- "c0_can_rxd_trnsv0_grp", };
-static const char * const c0_can_rxd_trnsv1_grp[] = {
- "c0_can_rxd_trnsv1_grp", };
-static const char * const c0_can_txd_trnsv0_grp[] = {
- "c0_can_txd_trnsv0_grp", };
-static const char * const c0_can_txd_trnsv1_grp[] = {
- "c0_can_txd_trnsv1_grp", };
-static const char * const c1_can_rxd_grp0[] = { "c1_can_rxd_grp0", };
-static const char * const c1_can_rxd_grp1[] = { "c1_can_rxd_grp1", };
-static const char * const c1_can_rxd_grp2[] = { "c1_can_rxd_grp2", };
-static const char * const c1_can_rxd_grp3[] = { "c1_can_rxd_grp3", };
-static const char * const c1_can_txd_grp0[] = { "c1_can_txd_grp0", };
-static const char * const c1_can_txd_grp1[] = { "c1_can_txd_grp1", };
-static const char * const c1_can_txd_grp2[] = { "c1_can_txd_grp2", };
-static const char * const c1_can_txd_grp3[] = { "c1_can_txd_grp3", };
-static const char * const ca_audio_lpc_grp[] = { "ca_audio_lpc_grp", };
-static const char * const ca_bt_lpc_grp[] = { "ca_bt_lpc_grp", };
-static const char * const ca_coex_grp[] = { "ca_coex_grp", };
-static const char * const ca_curator_lpc_grp[] = { "ca_curator_lpc_grp", };
-static const char * const ca_pcm_debug_grp[] = { "ca_pcm_debug_grp", };
-static const char * const ca_pio_grp[] = { "ca_pio_grp", };
-static const char * const ca_sdio_debug_grp[] = { "ca_sdio_debug_grp", };
-static const char * const ca_spi_grp[] = { "ca_spi_grp", };
-static const char * const ca_trb_grp[] = { "ca_trb_grp", };
-static const char * const ca_uart_debug_grp[] = { "ca_uart_debug_grp", };
-static const char * const clkc_grp0[] = { "clkc_grp0", };
-static const char * const clkc_grp1[] = { "clkc_grp1", };
-static const char * const gn_gnss_i2c_grp[] = { "gn_gnss_i2c_grp", };
-static const char * const gn_gnss_uart_nopause_grp[] = {
- "gn_gnss_uart_nopause_grp", };
-static const char * const gn_gnss_uart_grp[] = { "gn_gnss_uart_grp", };
-static const char * const gn_trg_spi_grp0[] = { "gn_trg_spi_grp0", };
-static const char * const gn_trg_spi_grp1[] = { "gn_trg_spi_grp1", };
-static const char * const cvbs_dbg_grp[] = { "cvbs_dbg_grp", };
-static const char * const cvbs_dbg_test_grp0[] = { "cvbs_dbg_test_grp0", };
-static const char * const cvbs_dbg_test_grp1[] = { "cvbs_dbg_test_grp1", };
-static const char * const cvbs_dbg_test_grp2[] = { "cvbs_dbg_test_grp2", };
-static const char * const cvbs_dbg_test_grp3[] = { "cvbs_dbg_test_grp3", };
-static const char * const cvbs_dbg_test_grp4[] = { "cvbs_dbg_test_grp4", };
-static const char * const cvbs_dbg_test_grp5[] = { "cvbs_dbg_test_grp5", };
-static const char * const cvbs_dbg_test_grp6[] = { "cvbs_dbg_test_grp6", };
-static const char * const cvbs_dbg_test_grp7[] = { "cvbs_dbg_test_grp7", };
-static const char * const cvbs_dbg_test_grp8[] = { "cvbs_dbg_test_grp8", };
-static const char * const cvbs_dbg_test_grp9[] = { "cvbs_dbg_test_grp9", };
-static const char * const cvbs_dbg_test_grp10[] = { "cvbs_dbg_test_grp10", };
-static const char * const cvbs_dbg_test_grp11[] = { "cvbs_dbg_test_grp11", };
-static const char * const cvbs_dbg_test_grp12[] = { "cvbs_dbg_test_grp12", };
-static const char * const cvbs_dbg_test_grp13[] = { "cvbs_dbg_test_grp13", };
-static const char * const cvbs_dbg_test_grp14[] = { "cvbs_dbg_test_grp14", };
-static const char * const cvbs_dbg_test_grp15[] = { "cvbs_dbg_test_grp15", };
-static const char * const gn_gnss_power_grp[] = { "gn_gnss_power_grp", };
-static const char * const gn_gnss_sw_status_grp[] = {
- "gn_gnss_sw_status_grp", };
-static const char * const gn_gnss_eclk_grp[] = { "gn_gnss_eclk_grp", };
-static const char * const gn_gnss_irq1_grp0[] = { "gn_gnss_irq1_grp0", };
-static const char * const gn_gnss_irq2_grp0[] = { "gn_gnss_irq2_grp0", };
-static const char * const gn_gnss_tm_grp[] = { "gn_gnss_tm_grp", };
-static const char * const gn_gnss_tsync_grp[] = { "gn_gnss_tsync_grp", };
-static const char * const gn_io_gnsssys_sw_cfg_grp[] = {
- "gn_io_gnsssys_sw_cfg_grp", };
-static const char * const gn_trg_grp0[] = { "gn_trg_grp0", };
-static const char * const gn_trg_grp1[] = { "gn_trg_grp1", };
-static const char * const gn_trg_shutdown_grp0[] = { "gn_trg_shutdown_grp0", };
-static const char * const gn_trg_shutdown_grp1[] = { "gn_trg_shutdown_grp1", };
-static const char * const gn_trg_shutdown_grp2[] = { "gn_trg_shutdown_grp2", };
-static const char * const gn_trg_shutdown_grp3[] = { "gn_trg_shutdown_grp3", };
-static const char * const i2c0_grp[] = { "i2c0_grp", };
-static const char * const i2c1_grp[] = { "i2c1_grp", };
-static const char * const i2s0_grp[] = { "i2s0_grp", };
-static const char * const i2s1_basic_grp[] = { "i2s1_basic_grp", };
-static const char * const i2s1_rxd0_grp0[] = { "i2s1_rxd0_grp0", };
-static const char * const i2s1_rxd0_grp1[] = { "i2s1_rxd0_grp1", };
-static const char * const i2s1_rxd0_grp2[] = { "i2s1_rxd0_grp2", };
-static const char * const i2s1_rxd0_grp3[] = { "i2s1_rxd0_grp3", };
-static const char * const i2s1_rxd0_grp4[] = { "i2s1_rxd0_grp4", };
-static const char * const i2s1_rxd1_grp0[] = { "i2s1_rxd1_grp0", };
-static const char * const i2s1_rxd1_grp1[] = { "i2s1_rxd1_grp1", };
-static const char * const i2s1_rxd1_grp2[] = { "i2s1_rxd1_grp2", };
-static const char * const i2s1_rxd1_grp3[] = { "i2s1_rxd1_grp3", };
-static const char * const i2s1_rxd1_grp4[] = { "i2s1_rxd1_grp4", };
-static const char * const jtag_jt_dbg_nsrst_grp[] = {
- "jtag_jt_dbg_nsrst_grp", };
-static const char * const jtag_ntrst_grp0[] = { "jtag_ntrst_grp0", };
-static const char * const jtag_ntrst_grp1[] = { "jtag_ntrst_grp1", };
-static const char * const jtag_swdiotms_grp0[] = { "jtag_swdiotms_grp0", };
-static const char * const jtag_swdiotms_grp1[] = { "jtag_swdiotms_grp1", };
-static const char * const jtag_tck_grp0[] = { "jtag_tck_grp0", };
-static const char * const jtag_tck_grp1[] = { "jtag_tck_grp1", };
-static const char * const jtag_tdi_grp0[] = { "jtag_tdi_grp0", };
-static const char * const jtag_tdi_grp1[] = { "jtag_tdi_grp1", };
-static const char * const jtag_tdo_grp0[] = { "jtag_tdo_grp0", };
-static const char * const jtag_tdo_grp1[] = { "jtag_tdo_grp1", };
-static const char * const ks_kas_spi_grp0[] = { "ks_kas_spi_grp0", };
-static const char * const ld_ldd_grp[] = { "ld_ldd_grp", };
-static const char * const ld_ldd_16bit_grp[] = { "ld_ldd_16bit_grp", };
-static const char * const ld_ldd_fck_grp[] = { "ld_ldd_fck_grp", };
-static const char * const ld_ldd_lck_grp[] = { "ld_ldd_lck_grp", };
-static const char * const lr_lcdrom_grp[] = { "lr_lcdrom_grp", };
-static const char * const lvds_analog_grp[] = { "lvds_analog_grp", };
-static const char * const nd_df_basic_grp[] = { "nd_df_basic_grp", };
-static const char * const nd_df_wp_grp[] = { "nd_df_wp_grp", };
-static const char * const nd_df_cs_grp[] = { "nd_df_cs_grp", };
-static const char * const ps_grp[] = { "ps_grp", };
-static const char * const ps_no_dir_grp[] = { "ps_no_dir_grp", };
-static const char * const pwc_core_on_grp[] = { "pwc_core_on_grp", };
-static const char * const pwc_ext_on_grp[] = { "pwc_ext_on_grp", };
-static const char * const pwc_gpio3_clk_grp[] = { "pwc_gpio3_clk_grp", };
-static const char * const pwc_io_on_grp[] = { "pwc_io_on_grp", };
-static const char * const pwc_lowbatt_b_grp0[] = { "pwc_lowbatt_b_grp0", };
-static const char * const pwc_mem_on_grp[] = { "pwc_mem_on_grp", };
-static const char * const pwc_on_key_b_grp0[] = { "pwc_on_key_b_grp0", };
-static const char * const pwc_wakeup_src0_grp[] = { "pwc_wakeup_src0_grp", };
-static const char * const pwc_wakeup_src1_grp[] = { "pwc_wakeup_src1_grp", };
-static const char * const pwc_wakeup_src2_grp[] = { "pwc_wakeup_src2_grp", };
-static const char * const pwc_wakeup_src3_grp[] = { "pwc_wakeup_src3_grp", };
-static const char * const pw_cko0_grp0[] = { "pw_cko0_grp0", };
-static const char * const pw_cko0_grp1[] = { "pw_cko0_grp1", };
-static const char * const pw_cko0_grp2[] = { "pw_cko0_grp2", };
-static const char * const pw_cko0_grp3[] = { "pw_cko0_grp3", };
-static const char * const pw_cko1_grp0[] = { "pw_cko1_grp0", };
-static const char * const pw_cko1_grp1[] = { "pw_cko1_grp1", };
-static const char * const pw_cko1_grp2[] = { "pw_cko1_grp2", };
-static const char * const pw_i2s01_clk_grp0[] = { "pw_i2s01_clk_grp0", };
-static const char * const pw_i2s01_clk_grp1[] = { "pw_i2s01_clk_grp1", };
-static const char * const pw_i2s01_clk_grp2[] = { "pw_i2s01_clk_grp2", };
-static const char * const pw_pwm0_grp0[] = { "pw_pwm0_grp0", };
-static const char * const pw_pwm0_grp1[] = { "pw_pwm0_grp1", };
-static const char * const pw_pwm1_grp0[] = { "pw_pwm1_grp0", };
-static const char * const pw_pwm1_grp1[] = { "pw_pwm1_grp1", };
-static const char * const pw_pwm1_grp2[] = { "pw_pwm1_grp2", };
-static const char * const pw_pwm2_grp0[] = { "pw_pwm2_grp0", };
-static const char * const pw_pwm2_grp1[] = { "pw_pwm2_grp1", };
-static const char * const pw_pwm2_grp2[] = { "pw_pwm2_grp2", };
-static const char * const pw_pwm3_grp0[] = { "pw_pwm3_grp0", };
-static const char * const pw_pwm3_grp1[] = { "pw_pwm3_grp1", };
-static const char * const pw_pwm_cpu_vol_grp0[] = { "pw_pwm_cpu_vol_grp0", };
-static const char * const pw_pwm_cpu_vol_grp1[] = { "pw_pwm_cpu_vol_grp1", };
-static const char * const pw_pwm_cpu_vol_grp2[] = { "pw_pwm_cpu_vol_grp2", };
-static const char * const pw_backlight_grp0[] = { "pw_backlight_grp0", };
-static const char * const pw_backlight_grp1[] = { "pw_backlight_grp1", };
-static const char * const rg_eth_mac_grp[] = { "rg_eth_mac_grp", };
-static const char * const rg_gmac_phy_intr_n_grp[] = {
- "rg_gmac_phy_intr_n_grp", };
-static const char * const rg_rgmii_mac_grp[] = { "rg_rgmii_mac_grp", };
-static const char * const rg_rgmii_phy_ref_clk_grp0[] = {
- "rg_rgmii_phy_ref_clk_grp0", };
-static const char * const rg_rgmii_phy_ref_clk_grp1[] = {
- "rg_rgmii_phy_ref_clk_grp1", };
-static const char * const sd0_grp[] = { "sd0_grp", };
-static const char * const sd0_4bit_grp[] = { "sd0_4bit_grp", };
-static const char * const sd1_grp[] = { "sd1_grp", };
-static const char * const sd1_4bit_grp0[] = { "sd1_4bit_grp0", };
-static const char * const sd1_4bit_grp1[] = { "sd1_4bit_grp1", };
-static const char * const sd2_basic_grp[] = { "sd2_basic_grp", };
-static const char * const sd2_cdb_grp0[] = { "sd2_cdb_grp0", };
-static const char * const sd2_cdb_grp1[] = { "sd2_cdb_grp1", };
-static const char * const sd2_wpb_grp0[] = { "sd2_wpb_grp0", };
-static const char * const sd2_wpb_grp1[] = { "sd2_wpb_grp1", };
-static const char * const sd3_9_grp[] = { "sd3_9_grp", };
-static const char * const sd5_grp[] = { "sd5_grp", };
-static const char * const sd6_grp0[] = { "sd6_grp0", };
-static const char * const sd6_grp1[] = { "sd6_grp1", };
-static const char * const sp0_ext_ldo_on_grp[] = { "sp0_ext_ldo_on_grp", };
-static const char * const sp0_qspi_grp[] = { "sp0_qspi_grp", };
-static const char * const sp1_spi_grp[] = { "sp1_spi_grp", };
-static const char * const tpiu_trace_grp[] = { "tpiu_trace_grp", };
-static const char * const uart0_grp[] = { "uart0_grp", };
-static const char * const uart0_nopause_grp[] = { "uart0_nopause_grp", };
-static const char * const uart1_grp[] = { "uart1_grp", };
-static const char * const uart2_cts_grp0[] = { "uart2_cts_grp0", };
-static const char * const uart2_cts_grp1[] = { "uart2_cts_grp1", };
-static const char * const uart2_rts_grp0[] = { "uart2_rts_grp0", };
-static const char * const uart2_rts_grp1[] = { "uart2_rts_grp1", };
-static const char * const uart2_rxd_grp0[] = { "uart2_rxd_grp0", };
-static const char * const uart2_rxd_grp1[] = { "uart2_rxd_grp1", };
-static const char * const uart2_rxd_grp2[] = { "uart2_rxd_grp2", };
-static const char * const uart2_txd_grp0[] = { "uart2_txd_grp0", };
-static const char * const uart2_txd_grp1[] = { "uart2_txd_grp1", };
-static const char * const uart2_txd_grp2[] = { "uart2_txd_grp2", };
-static const char * const uart3_cts_grp0[] = { "uart3_cts_grp0", };
-static const char * const uart3_cts_grp1[] = { "uart3_cts_grp1", };
-static const char * const uart3_cts_grp2[] = { "uart3_cts_grp2", };
-static const char * const uart3_rts_grp0[] = { "uart3_rts_grp0", };
-static const char * const uart3_rts_grp1[] = { "uart3_rts_grp1", };
-static const char * const uart3_rts_grp2[] = { "uart3_rts_grp2", };
-static const char * const uart3_rxd_grp0[] = { "uart3_rxd_grp0", };
-static const char * const uart3_rxd_grp1[] = { "uart3_rxd_grp1", };
-static const char * const uart3_rxd_grp2[] = { "uart3_rxd_grp2", };
-static const char * const uart3_txd_grp0[] = { "uart3_txd_grp0", };
-static const char * const uart3_txd_grp1[] = { "uart3_txd_grp1", };
-static const char * const uart3_txd_grp2[] = { "uart3_txd_grp2", };
-static const char * const uart4_basic_grp[] = { "uart4_basic_grp", };
-static const char * const uart4_cts_grp0[] = { "uart4_cts_grp0", };
-static const char * const uart4_cts_grp1[] = { "uart4_cts_grp1", };
-static const char * const uart4_cts_grp2[] = { "uart4_cts_grp2", };
-static const char * const uart4_rts_grp0[] = { "uart4_rts_grp0", };
-static const char * const uart4_rts_grp1[] = { "uart4_rts_grp1", };
-static const char * const uart4_rts_grp2[] = { "uart4_rts_grp2", };
-static const char * const usb0_drvvbus_grp0[] = { "usb0_drvvbus_grp0", };
-static const char * const usb0_drvvbus_grp1[] = { "usb0_drvvbus_grp1", };
-static const char * const usb1_drvvbus_grp0[] = { "usb1_drvvbus_grp0", };
-static const char * const usb1_drvvbus_grp1[] = { "usb1_drvvbus_grp1", };
-static const char * const visbus_dout_grp[] = { "visbus_dout_grp", };
-static const char * const vi_vip1_grp[] = { "vi_vip1_grp", };
-static const char * const vi_vip1_ext_grp[] = { "vi_vip1_ext_grp", };
-static const char * const vi_vip1_low8bit_grp[] = { "vi_vip1_low8bit_grp", };
-static const char * const vi_vip1_high8bit_grp[] = { "vi_vip1_high8bit_grp", };
-
-static struct atlas7_pad_mux gnss_gpio_grp_pad_mux[] = {
- MUX(1, 119, 0, N, N, N, N),
- MUX(1, 120, 0, N, N, N, N),
- MUX(1, 121, 0, N, N, N, N),
- MUX(1, 122, 0, N, N, N, N),
- MUX(1, 123, 0, N, N, N, N),
- MUX(1, 124, 0, N, N, N, N),
- MUX(1, 125, 0, N, N, N, N),
- MUX(1, 126, 0, N, N, N, N),
- MUX(1, 127, 0, N, N, N, N),
- MUX(1, 128, 0, N, N, N, N),
- MUX(1, 22, 0, N, N, N, N),
- MUX(1, 23, 0, N, N, N, N),
- MUX(1, 24, 0, N, N, N, N),
- MUX(1, 25, 0, N, N, N, N),
- MUX(1, 26, 0, N, N, N, N),
- MUX(1, 27, 0, N, N, N, N),
- MUX(1, 28, 0, N, N, N, N),
- MUX(1, 29, 0, N, N, N, N),
- MUX(1, 30, 0, N, N, N, N),
-};
-
-static struct atlas7_grp_mux gnss_gpio_grp_mux = {
- .pad_mux_count = ARRAY_SIZE(gnss_gpio_grp_pad_mux),
- .pad_mux_list = gnss_gpio_grp_pad_mux,
-};
-
-static struct atlas7_pad_mux lcd_vip_gpio_grp_pad_mux[] = {
- MUX(1, 74, 0, N, N, N, N),
- MUX(1, 75, 0, N, N, N, N),
- MUX(1, 76, 0, N, N, N, N),
- MUX(1, 77, 0, N, N, N, N),
- MUX(1, 78, 0, N, N, N, N),
- MUX(1, 79, 0, N, N, N, N),
- MUX(1, 80, 0, N, N, N, N),
- MUX(1, 81, 0, N, N, N, N),
- MUX(1, 82, 0, N, N, N, N),
- MUX(1, 83, 0, N, N, N, N),
- MUX(1, 84, 0, N, N, N, N),
- MUX(1, 53, 0, N, N, N, N),
- MUX(1, 54, 0, N, N, N, N),
- MUX(1, 55, 0, N, N, N, N),
- MUX(1, 56, 0, N, N, N, N),
- MUX(1, 57, 0, N, N, N, N),
- MUX(1, 58, 0, N, N, N, N),
- MUX(1, 59, 0, N, N, N, N),
- MUX(1, 60, 0, N, N, N, N),
- MUX(1, 61, 0, N, N, N, N),
- MUX(1, 62, 0, N, N, N, N),
- MUX(1, 63, 0, N, N, N, N),
- MUX(1, 64, 0, N, N, N, N),
- MUX(1, 65, 0, N, N, N, N),
- MUX(1, 66, 0, N, N, N, N),
- MUX(1, 67, 0, N, N, N, N),
- MUX(1, 68, 0, N, N, N, N),
- MUX(1, 69, 0, N, N, N, N),
- MUX(1, 70, 0, N, N, N, N),
- MUX(1, 71, 0, N, N, N, N),
- MUX(1, 72, 0, N, N, N, N),
- MUX(1, 73, 0, N, N, N, N),
-};
-
-static struct atlas7_grp_mux lcd_vip_gpio_grp_mux = {
- .pad_mux_count = ARRAY_SIZE(lcd_vip_gpio_grp_pad_mux),
- .pad_mux_list = lcd_vip_gpio_grp_pad_mux,
-};
-
-static struct atlas7_pad_mux sdio_i2s_gpio_grp_pad_mux[] = {
- MUX(1, 31, 0, N, N, N, N),
- MUX(1, 32, 0, N, N, N, N),
- MUX(1, 33, 0, N, N, N, N),
- MUX(1, 34, 0, N, N, N, N),
- MUX(1, 35, 0, N, N, N, N),
- MUX(1, 36, 0, N, N, N, N),
- MUX(1, 85, 0, N, N, N, N),
- MUX(1, 86, 0, N, N, N, N),
- MUX(1, 87, 0, N, N, N, N),
- MUX(1, 88, 0, N, N, N, N),
- MUX(1, 89, 0, N, N, N, N),
- MUX(1, 90, 0, N, N, N, N),
- MUX(1, 129, 0, N, N, N, N),
- MUX(1, 130, 0, N, N, N, N),
- MUX(1, 131, 0, N, N, N, N),
- MUX(1, 132, 0, N, N, N, N),
- MUX(1, 91, 0, N, N, N, N),
- MUX(1, 92, 0, N, N, N, N),
- MUX(1, 93, 0, N, N, N, N),
- MUX(1, 94, 0, N, N, N, N),
- MUX(1, 95, 0, N, N, N, N),
- MUX(1, 96, 0, N, N, N, N),
- MUX(1, 112, 0, N, N, N, N),
- MUX(1, 113, 0, N, N, N, N),
- MUX(1, 114, 0, N, N, N, N),
- MUX(1, 115, 0, N, N, N, N),
- MUX(1, 116, 0, N, N, N, N),
- MUX(1, 117, 0, N, N, N, N),
- MUX(1, 118, 0, N, N, N, N),
-};
-
-static struct atlas7_grp_mux sdio_i2s_gpio_grp_mux = {
- .pad_mux_count = ARRAY_SIZE(sdio_i2s_gpio_grp_pad_mux),
- .pad_mux_list = sdio_i2s_gpio_grp_pad_mux,
-};
-
-static struct atlas7_pad_mux sp_rgmii_gpio_grp_pad_mux[] = {
- MUX(1, 97, 0, N, N, N, N),
- MUX(1, 98, 0, N, N, N, N),
- MUX(1, 99, 0, N, N, N, N),
- MUX(1, 100, 0, N, N, N, N),
- MUX(1, 101, 0, N, N, N, N),
- MUX(1, 102, 0, N, N, N, N),
- MUX(1, 103, 0, N, N, N, N),
- MUX(1, 104, 0, N, N, N, N),
- MUX(1, 105, 0, N, N, N, N),
- MUX(1, 106, 0, N, N, N, N),
- MUX(1, 107, 0, N, N, N, N),
- MUX(1, 108, 0, N, N, N, N),
- MUX(1, 109, 0, N, N, N, N),
- MUX(1, 110, 0, N, N, N, N),
- MUX(1, 111, 0, N, N, N, N),
- MUX(1, 18, 0, N, N, N, N),
- MUX(1, 19, 0, N, N, N, N),
- MUX(1, 20, 0, N, N, N, N),
- MUX(1, 21, 0, N, N, N, N),
- MUX(1, 141, 0, N, N, N, N),
- MUX(1, 142, 0, N, N, N, N),
- MUX(1, 143, 0, N, N, N, N),
- MUX(1, 144, 0, N, N, N, N),
- MUX(1, 145, 0, N, N, N, N),
- MUX(1, 146, 0, N, N, N, N),
- MUX(1, 147, 0, N, N, N, N),
- MUX(1, 148, 0, N, N, N, N),
-};
-
-static struct atlas7_grp_mux sp_rgmii_gpio_grp_mux = {
- .pad_mux_count = ARRAY_SIZE(sp_rgmii_gpio_grp_pad_mux),
- .pad_mux_list = sp_rgmii_gpio_grp_pad_mux,
-};
-
-static struct atlas7_pad_mux lvds_gpio_grp_pad_mux[] = {
- MUX(1, 157, 0, N, N, N, N),
- MUX(1, 158, 0, N, N, N, N),
- MUX(1, 155, 0, N, N, N, N),
- MUX(1, 156, 0, N, N, N, N),
- MUX(1, 153, 0, N, N, N, N),
- MUX(1, 154, 0, N, N, N, N),
- MUX(1, 151, 0, N, N, N, N),
- MUX(1, 152, 0, N, N, N, N),
- MUX(1, 149, 0, N, N, N, N),
- MUX(1, 150, 0, N, N, N, N),
-};
-
-static struct atlas7_grp_mux lvds_gpio_grp_mux = {
- .pad_mux_count = ARRAY_SIZE(lvds_gpio_grp_pad_mux),
- .pad_mux_list = lvds_gpio_grp_pad_mux,
-};
-
-static struct atlas7_pad_mux jtag_uart_nand_gpio_grp_pad_mux[] = {
- MUX(1, 44, 0, N, N, N, N),
- MUX(1, 43, 0, N, N, N, N),
- MUX(1, 42, 0, N, N, N, N),
- MUX(1, 41, 0, N, N, N, N),
- MUX(1, 40, 0, N, N, N, N),
- MUX(1, 39, 0, N, N, N, N),
- MUX(1, 38, 0, N, N, N, N),
- MUX(1, 37, 0, N, N, N, N),
- MUX(1, 46, 0, N, N, N, N),
- MUX(1, 47, 0, N, N, N, N),
- MUX(1, 48, 0, N, N, N, N),
- MUX(1, 49, 0, N, N, N, N),
- MUX(1, 50, 0, N, N, N, N),
- MUX(1, 52, 0, N, N, N, N),
- MUX(1, 51, 0, N, N, N, N),
- MUX(1, 45, 0, N, N, N, N),
- MUX(1, 133, 0, N, N, N, N),
- MUX(1, 134, 0, N, N, N, N),
- MUX(1, 135, 0, N, N, N, N),
- MUX(1, 136, 0, N, N, N, N),
- MUX(1, 137, 0, N, N, N, N),
- MUX(1, 138, 0, N, N, N, N),
- MUX(1, 139, 0, N, N, N, N),
- MUX(1, 140, 0, N, N, N, N),
- MUX(1, 159, 0, N, N, N, N),
- MUX(1, 160, 0, N, N, N, N),
- MUX(1, 161, 0, N, N, N, N),
- MUX(1, 162, 0, N, N, N, N),
- MUX(1, 163, 0, N, N, N, N),
-};
-
-static struct atlas7_grp_mux jtag_uart_nand_gpio_grp_mux = {
- .pad_mux_count = ARRAY_SIZE(jtag_uart_nand_gpio_grp_pad_mux),
- .pad_mux_list = jtag_uart_nand_gpio_grp_pad_mux,
-};
-
-static struct atlas7_pad_mux rtc_gpio_grp_pad_mux[] = {
- MUX(0, 0, 0, N, N, N, N),
- MUX(0, 1, 0, N, N, N, N),
- MUX(0, 2, 0, N, N, N, N),
- MUX(0, 3, 0, N, N, N, N),
- MUX(0, 4, 0, N, N, N, N),
- MUX(0, 10, 0, N, N, N, N),
- MUX(0, 11, 0, N, N, N, N),
- MUX(0, 12, 0, N, N, N, N),
- MUX(0, 13, 0, N, N, N, N),
- MUX(0, 14, 0, N, N, N, N),
- MUX(0, 15, 0, N, N, N, N),
- MUX(0, 16, 0, N, N, N, N),
- MUX(0, 17, 0, N, N, N, N),
- MUX(0, 9, 0, N, N, N, N),
-};
-
-static struct atlas7_grp_mux rtc_gpio_grp_mux = {
- .pad_mux_count = ARRAY_SIZE(rtc_gpio_grp_pad_mux),
- .pad_mux_list = rtc_gpio_grp_pad_mux,
-};
-
-static struct atlas7_pad_mux audio_ac97_grp_pad_mux[] = {
- MUX(1, 113, 2, N, N, N, N),
- MUX(1, 118, 2, N, N, N, N),
- MUX(1, 115, 2, N, N, N, N),
- MUX(1, 114, 2, N, N, N, N),
-};
-
-static struct atlas7_grp_mux audio_ac97_grp_mux = {
- .pad_mux_count = ARRAY_SIZE(audio_ac97_grp_pad_mux),
- .pad_mux_list = audio_ac97_grp_pad_mux,
-};
-
-static struct atlas7_pad_mux audio_digmic_grp0_pad_mux[] = {
- MUX(1, 51, 3, 0xa10, 20, 0xa90, 20),
-};
-
-static struct atlas7_grp_mux audio_digmic_grp0_mux = {
- .pad_mux_count = ARRAY_SIZE(audio_digmic_grp0_pad_mux),
- .pad_mux_list = audio_digmic_grp0_pad_mux,
-};
-
-static struct atlas7_pad_mux audio_digmic_grp1_pad_mux[] = {
- MUX(1, 122, 5, 0xa10, 20, 0xa90, 20),
-};
-
-static struct atlas7_grp_mux audio_digmic_grp1_mux = {
- .pad_mux_count = ARRAY_SIZE(audio_digmic_grp1_pad_mux),
- .pad_mux_list = audio_digmic_grp1_pad_mux,
-};
-
-static struct atlas7_pad_mux audio_digmic_grp2_pad_mux[] = {
- MUX(1, 161, 7, 0xa10, 20, 0xa90, 20),
-};
-
-static struct atlas7_grp_mux audio_digmic_grp2_mux = {
- .pad_mux_count = ARRAY_SIZE(audio_digmic_grp2_pad_mux),
- .pad_mux_list = audio_digmic_grp2_pad_mux,
-};
-
-static struct atlas7_pad_mux audio_func_dbg_grp_pad_mux[] = {
- MUX(1, 141, 4, N, N, N, N),
- MUX(1, 144, 4, N, N, N, N),
- MUX(1, 44, 6, N, N, N, N),
- MUX(1, 43, 6, N, N, N, N),
- MUX(1, 42, 6, N, N, N, N),
- MUX(1, 41, 6, N, N, N, N),
- MUX(1, 40, 6, N, N, N, N),
- MUX(1, 39, 6, N, N, N, N),
- MUX(1, 38, 6, N, N, N, N),
- MUX(1, 37, 6, N, N, N, N),
- MUX(1, 74, 6, N, N, N, N),
- MUX(1, 75, 6, N, N, N, N),
- MUX(1, 76, 6, N, N, N, N),
- MUX(1, 77, 6, N, N, N, N),
- MUX(1, 78, 6, N, N, N, N),
- MUX(1, 79, 6, N, N, N, N),
- MUX(1, 81, 6, N, N, N, N),
- MUX(1, 113, 6, N, N, N, N),
- MUX(1, 114, 6, N, N, N, N),
- MUX(1, 118, 6, N, N, N, N),
- MUX(1, 115, 6, N, N, N, N),
- MUX(1, 49, 6, N, N, N, N),
- MUX(1, 50, 6, N, N, N, N),
- MUX(1, 142, 4, N, N, N, N),
- MUX(1, 143, 4, N, N, N, N),
- MUX(1, 80, 6, N, N, N, N),
-};
-
-static struct atlas7_grp_mux audio_func_dbg_grp_mux = {
- .pad_mux_count = ARRAY_SIZE(audio_func_dbg_grp_pad_mux),
- .pad_mux_list = audio_func_dbg_grp_pad_mux,
-};
-
-static struct atlas7_pad_mux audio_i2s_grp_pad_mux[] = {
- MUX(1, 118, 1, N, N, N, N),
- MUX(1, 115, 1, N, N, N, N),
- MUX(1, 116, 1, N, N, N, N),
- MUX(1, 117, 1, N, N, N, N),
- MUX(1, 112, 1, N, N, N, N),
- MUX(1, 113, 1, N, N, N, N),
- MUX(1, 114, 1, N, N, N, N),
-};
-
-static struct atlas7_grp_mux audio_i2s_grp_mux = {
- .pad_mux_count = ARRAY_SIZE(audio_i2s_grp_pad_mux),
- .pad_mux_list = audio_i2s_grp_pad_mux,
-};
-
-static struct atlas7_pad_mux audio_i2s_2ch_grp_pad_mux[] = {
- MUX(1, 118, 1, N, N, N, N),
- MUX(1, 115, 1, N, N, N, N),
- MUX(1, 112, 1, N, N, N, N),
- MUX(1, 113, 1, N, N, N, N),
- MUX(1, 114, 1, N, N, N, N),
-};
-
-static struct atlas7_grp_mux audio_i2s_2ch_grp_mux = {
- .pad_mux_count = ARRAY_SIZE(audio_i2s_2ch_grp_pad_mux),
- .pad_mux_list = audio_i2s_2ch_grp_pad_mux,
-};
-
-static struct atlas7_pad_mux audio_i2s_extclk_grp_pad_mux[] = {
- MUX(1, 112, 2, N, N, N, N),
-};
-
-static struct atlas7_grp_mux audio_i2s_extclk_grp_mux = {
- .pad_mux_count = ARRAY_SIZE(audio_i2s_extclk_grp_pad_mux),
- .pad_mux_list = audio_i2s_extclk_grp_pad_mux,
-};
-
-static struct atlas7_pad_mux audio_spdif_out_grp0_pad_mux[] = {
- MUX(1, 112, 3, N, N, N, N),
-};
-
-static struct atlas7_grp_mux audio_spdif_out_grp0_mux = {
- .pad_mux_count = ARRAY_SIZE(audio_spdif_out_grp0_pad_mux),
- .pad_mux_list = audio_spdif_out_grp0_pad_mux,
-};
-
-static struct atlas7_pad_mux audio_spdif_out_grp1_pad_mux[] = {
- MUX(1, 116, 3, N, N, N, N),
-};
-
-static struct atlas7_grp_mux audio_spdif_out_grp1_mux = {
- .pad_mux_count = ARRAY_SIZE(audio_spdif_out_grp1_pad_mux),
- .pad_mux_list = audio_spdif_out_grp1_pad_mux,
-};
-
-static struct atlas7_pad_mux audio_spdif_out_grp2_pad_mux[] = {
- MUX(1, 142, 3, N, N, N, N),
-};
-
-static struct atlas7_grp_mux audio_spdif_out_grp2_mux = {
- .pad_mux_count = ARRAY_SIZE(audio_spdif_out_grp2_pad_mux),
- .pad_mux_list = audio_spdif_out_grp2_pad_mux,
-};
-
-static struct atlas7_pad_mux audio_uart0_basic_grp_pad_mux[] = {
- MUX(1, 143, 1, N, N, N, N),
- MUX(1, 142, 1, N, N, N, N),
- MUX(1, 141, 1, N, N, N, N),
- MUX(1, 144, 1, N, N, N, N),
-};
-
-static struct atlas7_grp_mux audio_uart0_basic_grp_mux = {
- .pad_mux_count = ARRAY_SIZE(audio_uart0_basic_grp_pad_mux),
- .pad_mux_list = audio_uart0_basic_grp_pad_mux,
-};
-
-static struct atlas7_pad_mux audio_uart0_urfs_grp0_pad_mux[] = {
- MUX(1, 117, 5, 0xa10, 28, 0xa90, 28),
-};
-
-static struct atlas7_grp_mux audio_uart0_urfs_grp0_mux = {
- .pad_mux_count = ARRAY_SIZE(audio_uart0_urfs_grp0_pad_mux),
- .pad_mux_list = audio_uart0_urfs_grp0_pad_mux,
-};
-
-static struct atlas7_pad_mux audio_uart0_urfs_grp1_pad_mux[] = {
- MUX(1, 139, 3, 0xa10, 28, 0xa90, 28),
-};
-
-static struct atlas7_grp_mux audio_uart0_urfs_grp1_mux = {
- .pad_mux_count = ARRAY_SIZE(audio_uart0_urfs_grp1_pad_mux),
- .pad_mux_list = audio_uart0_urfs_grp1_pad_mux,
-};
-
-static struct atlas7_pad_mux audio_uart0_urfs_grp2_pad_mux[] = {
- MUX(1, 163, 3, 0xa10, 28, 0xa90, 28),
-};
-
-static struct atlas7_grp_mux audio_uart0_urfs_grp2_mux = {
- .pad_mux_count = ARRAY_SIZE(audio_uart0_urfs_grp2_pad_mux),
- .pad_mux_list = audio_uart0_urfs_grp2_pad_mux,
-};
-
-static struct atlas7_pad_mux audio_uart0_urfs_grp3_pad_mux[] = {
- MUX(1, 162, 6, 0xa10, 28, 0xa90, 28),
-};
-
-static struct atlas7_grp_mux audio_uart0_urfs_grp3_mux = {
- .pad_mux_count = ARRAY_SIZE(audio_uart0_urfs_grp3_pad_mux),
- .pad_mux_list = audio_uart0_urfs_grp3_pad_mux,
-};
-
-static struct atlas7_pad_mux audio_uart1_basic_grp_pad_mux[] = {
- MUX(1, 147, 1, 0xa10, 24, 0xa90, 24),
- MUX(1, 146, 1, 0xa10, 25, 0xa90, 25),
- MUX(1, 145, 1, 0xa10, 23, 0xa90, 23),
- MUX(1, 148, 1, 0xa10, 22, 0xa90, 22),
-};
-
-static struct atlas7_grp_mux audio_uart1_basic_grp_mux = {
- .pad_mux_count = ARRAY_SIZE(audio_uart1_basic_grp_pad_mux),
- .pad_mux_list = audio_uart1_basic_grp_pad_mux,
-};
-
-static struct atlas7_pad_mux audio_uart1_urfs_grp0_pad_mux[] = {
- MUX(1, 117, 6, 0xa10, 29, 0xa90, 29),
-};
-
-static struct atlas7_grp_mux audio_uart1_urfs_grp0_mux = {
- .pad_mux_count = ARRAY_SIZE(audio_uart1_urfs_grp0_pad_mux),
- .pad_mux_list = audio_uart1_urfs_grp0_pad_mux,
-};
-
-static struct atlas7_pad_mux audio_uart1_urfs_grp1_pad_mux[] = {
- MUX(1, 140, 3, 0xa10, 29, 0xa90, 29),
-};
-
-static struct atlas7_grp_mux audio_uart1_urfs_grp1_mux = {
- .pad_mux_count = ARRAY_SIZE(audio_uart1_urfs_grp1_pad_mux),
- .pad_mux_list = audio_uart1_urfs_grp1_pad_mux,
-};
-
-static struct atlas7_pad_mux audio_uart1_urfs_grp2_pad_mux[] = {
- MUX(1, 163, 4, 0xa10, 29, 0xa90, 29),
-};
-
-static struct atlas7_grp_mux audio_uart1_urfs_grp2_mux = {
- .pad_mux_count = ARRAY_SIZE(audio_uart1_urfs_grp2_pad_mux),
- .pad_mux_list = audio_uart1_urfs_grp2_pad_mux,
-};
-
-static struct atlas7_pad_mux audio_uart2_urfs_grp0_pad_mux[] = {
- MUX(1, 139, 4, 0xa10, 30, 0xa90, 30),
-};
-
-static struct atlas7_grp_mux audio_uart2_urfs_grp0_mux = {
- .pad_mux_count = ARRAY_SIZE(audio_uart2_urfs_grp0_pad_mux),
- .pad_mux_list = audio_uart2_urfs_grp0_pad_mux,
-};
-
-static struct atlas7_pad_mux audio_uart2_urfs_grp1_pad_mux[] = {
- MUX(1, 163, 6, 0xa10, 30, 0xa90, 30),
-};
-
-static struct atlas7_grp_mux audio_uart2_urfs_grp1_mux = {
- .pad_mux_count = ARRAY_SIZE(audio_uart2_urfs_grp1_pad_mux),
- .pad_mux_list = audio_uart2_urfs_grp1_pad_mux,
-};
-
-static struct atlas7_pad_mux audio_uart2_urfs_grp2_pad_mux[] = {
- MUX(1, 96, 3, 0xa10, 30, 0xa90, 30),
-};
-
-static struct atlas7_grp_mux audio_uart2_urfs_grp2_mux = {
- .pad_mux_count = ARRAY_SIZE(audio_uart2_urfs_grp2_pad_mux),
- .pad_mux_list = audio_uart2_urfs_grp2_pad_mux,
-};
-
-static struct atlas7_pad_mux audio_uart2_urxd_grp0_pad_mux[] = {
- MUX(1, 20, 2, 0xa00, 24, 0xa80, 24),
-};
-
-static struct atlas7_grp_mux audio_uart2_urxd_grp0_mux = {
- .pad_mux_count = ARRAY_SIZE(audio_uart2_urxd_grp0_pad_mux),
- .pad_mux_list = audio_uart2_urxd_grp0_pad_mux,
-};
-
-static struct atlas7_pad_mux audio_uart2_urxd_grp1_pad_mux[] = {
- MUX(1, 109, 2, 0xa00, 24, 0xa80, 24),
-};
-
-static struct atlas7_grp_mux audio_uart2_urxd_grp1_mux = {
- .pad_mux_count = ARRAY_SIZE(audio_uart2_urxd_grp1_pad_mux),
- .pad_mux_list = audio_uart2_urxd_grp1_pad_mux,
-};
-
-static struct atlas7_pad_mux audio_uart2_urxd_grp2_pad_mux[] = {
- MUX(1, 93, 3, 0xa00, 24, 0xa80, 24),
-};
-
-static struct atlas7_grp_mux audio_uart2_urxd_grp2_mux = {
- .pad_mux_count = ARRAY_SIZE(audio_uart2_urxd_grp2_pad_mux),
- .pad_mux_list = audio_uart2_urxd_grp2_pad_mux,
-};
-
-static struct atlas7_pad_mux audio_uart2_usclk_grp0_pad_mux[] = {
- MUX(1, 19, 2, 0xa00, 23, 0xa80, 23),
-};
-
-static struct atlas7_grp_mux audio_uart2_usclk_grp0_mux = {
- .pad_mux_count = ARRAY_SIZE(audio_uart2_usclk_grp0_pad_mux),
- .pad_mux_list = audio_uart2_usclk_grp0_pad_mux,
-};
-
-static struct atlas7_pad_mux audio_uart2_usclk_grp1_pad_mux[] = {
- MUX(1, 101, 2, 0xa00, 23, 0xa80, 23),
-};
-
-static struct atlas7_grp_mux audio_uart2_usclk_grp1_mux = {
- .pad_mux_count = ARRAY_SIZE(audio_uart2_usclk_grp1_pad_mux),
- .pad_mux_list = audio_uart2_usclk_grp1_pad_mux,
-};
-
-static struct atlas7_pad_mux audio_uart2_usclk_grp2_pad_mux[] = {
- MUX(1, 91, 3, 0xa00, 23, 0xa80, 23),
-};
-
-static struct atlas7_grp_mux audio_uart2_usclk_grp2_mux = {
- .pad_mux_count = ARRAY_SIZE(audio_uart2_usclk_grp2_pad_mux),
- .pad_mux_list = audio_uart2_usclk_grp2_pad_mux,
-};
-
-static struct atlas7_pad_mux audio_uart2_utfs_grp0_pad_mux[] = {
- MUX(1, 18, 2, 0xa00, 22, 0xa80, 22),
-};
-
-static struct atlas7_grp_mux audio_uart2_utfs_grp0_mux = {
- .pad_mux_count = ARRAY_SIZE(audio_uart2_utfs_grp0_pad_mux),
- .pad_mux_list = audio_uart2_utfs_grp0_pad_mux,
-};
-
-static struct atlas7_pad_mux audio_uart2_utfs_grp1_pad_mux[] = {
- MUX(1, 111, 2, 0xa00, 22, 0xa80, 22),
-};
-
-static struct atlas7_grp_mux audio_uart2_utfs_grp1_mux = {
- .pad_mux_count = ARRAY_SIZE(audio_uart2_utfs_grp1_pad_mux),
- .pad_mux_list = audio_uart2_utfs_grp1_pad_mux,
-};
-
-static struct atlas7_pad_mux audio_uart2_utfs_grp2_pad_mux[] = {
- MUX(1, 94, 3, 0xa00, 22, 0xa80, 22),
-};
-
-static struct atlas7_grp_mux audio_uart2_utfs_grp2_mux = {
- .pad_mux_count = ARRAY_SIZE(audio_uart2_utfs_grp2_pad_mux),
- .pad_mux_list = audio_uart2_utfs_grp2_pad_mux,
-};
-
-static struct atlas7_pad_mux audio_uart2_utxd_grp0_pad_mux[] = {
- MUX(1, 21, 2, 0xa00, 25, 0xa80, 25),
-};
-
-static struct atlas7_grp_mux audio_uart2_utxd_grp0_mux = {
- .pad_mux_count = ARRAY_SIZE(audio_uart2_utxd_grp0_pad_mux),
- .pad_mux_list = audio_uart2_utxd_grp0_pad_mux,
-};
-
-static struct atlas7_pad_mux audio_uart2_utxd_grp1_pad_mux[] = {
- MUX(1, 110, 2, 0xa00, 25, 0xa80, 25),
-};
-
-static struct atlas7_grp_mux audio_uart2_utxd_grp1_mux = {
- .pad_mux_count = ARRAY_SIZE(audio_uart2_utxd_grp1_pad_mux),
- .pad_mux_list = audio_uart2_utxd_grp1_pad_mux,
-};
-
-static struct atlas7_pad_mux audio_uart2_utxd_grp2_pad_mux[] = {
- MUX(1, 92, 3, 0xa00, 25, 0xa80, 25),
-};
-
-static struct atlas7_grp_mux audio_uart2_utxd_grp2_mux = {
- .pad_mux_count = ARRAY_SIZE(audio_uart2_utxd_grp2_pad_mux),
- .pad_mux_list = audio_uart2_utxd_grp2_pad_mux,
-};
-
-static struct atlas7_pad_mux c_can_trnsvr_en_grp0_pad_mux[] = {
- MUX(0, 2, 6, N, N, N, N),
-};
-
-static struct atlas7_grp_mux c_can_trnsvr_en_grp0_mux = {
- .pad_mux_count = ARRAY_SIZE(c_can_trnsvr_en_grp0_pad_mux),
- .pad_mux_list = c_can_trnsvr_en_grp0_pad_mux,
-};
-
-static struct atlas7_pad_mux c_can_trnsvr_en_grp1_pad_mux[] = {
- MUX(0, 0, 2, N, N, N, N),
-};
-
-static struct atlas7_grp_mux c_can_trnsvr_en_grp1_mux = {
- .pad_mux_count = ARRAY_SIZE(c_can_trnsvr_en_grp1_pad_mux),
- .pad_mux_list = c_can_trnsvr_en_grp1_pad_mux,
-};
-
-static struct atlas7_pad_mux c_can_trnsvr_intr_grp_pad_mux[] = {
- MUX(0, 1, 2, N, N, N, N),
-};
-
-static struct atlas7_grp_mux c_can_trnsvr_intr_grp_mux = {
- .pad_mux_count = ARRAY_SIZE(c_can_trnsvr_intr_grp_pad_mux),
- .pad_mux_list = c_can_trnsvr_intr_grp_pad_mux,
-};
-
-static struct atlas7_pad_mux c_can_trnsvr_stb_n_grp_pad_mux[] = {
- MUX(0, 3, 6, N, N, N, N),
-};
-
-static struct atlas7_grp_mux c_can_trnsvr_stb_n_grp_mux = {
- .pad_mux_count = ARRAY_SIZE(c_can_trnsvr_stb_n_grp_pad_mux),
- .pad_mux_list = c_can_trnsvr_stb_n_grp_pad_mux,
-};
-
-static struct atlas7_pad_mux c0_can_rxd_trnsv0_grp_pad_mux[] = {
- MUX(0, 11, 1, 0xa08, 9, 0xa88, 9),
-};
-
-static struct atlas7_grp_mux c0_can_rxd_trnsv0_grp_mux = {
- .pad_mux_count = ARRAY_SIZE(c0_can_rxd_trnsv0_grp_pad_mux),
- .pad_mux_list = c0_can_rxd_trnsv0_grp_pad_mux,
-};
-
-static struct atlas7_pad_mux c0_can_rxd_trnsv1_grp_pad_mux[] = {
- MUX(0, 2, 5, 0xa10, 9, 0xa90, 9),
-};
-
-static struct atlas7_grp_mux c0_can_rxd_trnsv1_grp_mux = {
- .pad_mux_count = ARRAY_SIZE(c0_can_rxd_trnsv1_grp_pad_mux),
- .pad_mux_list = c0_can_rxd_trnsv1_grp_pad_mux,
-};
-
-static struct atlas7_pad_mux c0_can_txd_trnsv0_grp_pad_mux[] = {
- MUX(0, 10, 1, N, N, N, N),
-};
-
-static struct atlas7_grp_mux c0_can_txd_trnsv0_grp_mux = {
- .pad_mux_count = ARRAY_SIZE(c0_can_txd_trnsv0_grp_pad_mux),
- .pad_mux_list = c0_can_txd_trnsv0_grp_pad_mux,
-};
-
-static struct atlas7_pad_mux c0_can_txd_trnsv1_grp_pad_mux[] = {
- MUX(0, 3, 5, N, N, N, N),
-};
-
-static struct atlas7_grp_mux c0_can_txd_trnsv1_grp_mux = {
- .pad_mux_count = ARRAY_SIZE(c0_can_txd_trnsv1_grp_pad_mux),
- .pad_mux_list = c0_can_txd_trnsv1_grp_pad_mux,
-};
-
-static struct atlas7_pad_mux c1_can_rxd_grp0_pad_mux[] = {
- MUX(1, 138, 2, 0xa00, 4, 0xa80, 4),
-};
-
-static struct atlas7_grp_mux c1_can_rxd_grp0_mux = {
- .pad_mux_count = ARRAY_SIZE(c1_can_rxd_grp0_pad_mux),
- .pad_mux_list = c1_can_rxd_grp0_pad_mux,
-};
-
-static struct atlas7_pad_mux c1_can_rxd_grp1_pad_mux[] = {
- MUX(1, 147, 2, 0xa00, 4, 0xa80, 4),
-};
-
-static struct atlas7_grp_mux c1_can_rxd_grp1_mux = {
- .pad_mux_count = ARRAY_SIZE(c1_can_rxd_grp1_pad_mux),
- .pad_mux_list = c1_can_rxd_grp1_pad_mux,
-};
-
-static struct atlas7_pad_mux c1_can_rxd_grp2_pad_mux[] = {
- MUX(0, 2, 2, 0xa00, 4, 0xa80, 4),
-};
-
-static struct atlas7_grp_mux c1_can_rxd_grp2_mux = {
- .pad_mux_count = ARRAY_SIZE(c1_can_rxd_grp2_pad_mux),
- .pad_mux_list = c1_can_rxd_grp2_pad_mux,
-};
-
-static struct atlas7_pad_mux c1_can_rxd_grp3_pad_mux[] = {
- MUX(1, 162, 4, 0xa00, 4, 0xa80, 4),
-};
-
-static struct atlas7_grp_mux c1_can_rxd_grp3_mux = {
- .pad_mux_count = ARRAY_SIZE(c1_can_rxd_grp3_pad_mux),
- .pad_mux_list = c1_can_rxd_grp3_pad_mux,
-};
-
-static struct atlas7_pad_mux c1_can_txd_grp0_pad_mux[] = {
- MUX(1, 137, 2, N, N, N, N),
-};
-
-static struct atlas7_grp_mux c1_can_txd_grp0_mux = {
- .pad_mux_count = ARRAY_SIZE(c1_can_txd_grp0_pad_mux),
- .pad_mux_list = c1_can_txd_grp0_pad_mux,
-};
-
-static struct atlas7_pad_mux c1_can_txd_grp1_pad_mux[] = {
- MUX(1, 146, 2, N, N, N, N),
-};
-
-static struct atlas7_grp_mux c1_can_txd_grp1_mux = {
- .pad_mux_count = ARRAY_SIZE(c1_can_txd_grp1_pad_mux),
- .pad_mux_list = c1_can_txd_grp1_pad_mux,
-};
-
-static struct atlas7_pad_mux c1_can_txd_grp2_pad_mux[] = {
- MUX(0, 3, 2, N, N, N, N),
-};
-
-static struct atlas7_grp_mux c1_can_txd_grp2_mux = {
- .pad_mux_count = ARRAY_SIZE(c1_can_txd_grp2_pad_mux),
- .pad_mux_list = c1_can_txd_grp2_pad_mux,
-};
-
-static struct atlas7_pad_mux c1_can_txd_grp3_pad_mux[] = {
- MUX(1, 161, 4, N, N, N, N),
-};
-
-static struct atlas7_grp_mux c1_can_txd_grp3_mux = {
- .pad_mux_count = ARRAY_SIZE(c1_can_txd_grp3_pad_mux),
- .pad_mux_list = c1_can_txd_grp3_pad_mux,
-};
-
-static struct atlas7_pad_mux ca_audio_lpc_grp_pad_mux[] = {
- MUX(1, 62, 4, N, N, N, N),
- MUX(1, 63, 4, N, N, N, N),
- MUX(1, 64, 4, N, N, N, N),
- MUX(1, 65, 4, N, N, N, N),
- MUX(1, 66, 4, N, N, N, N),
- MUX(1, 67, 4, N, N, N, N),
- MUX(1, 68, 4, N, N, N, N),
- MUX(1, 69, 4, N, N, N, N),
- MUX(1, 70, 4, N, N, N, N),
- MUX(1, 71, 4, N, N, N, N),
-};
-
-static struct atlas7_grp_mux ca_audio_lpc_grp_mux = {
- .pad_mux_count = ARRAY_SIZE(ca_audio_lpc_grp_pad_mux),
- .pad_mux_list = ca_audio_lpc_grp_pad_mux,
-};
-
-static struct atlas7_pad_mux ca_bt_lpc_grp_pad_mux[] = {
- MUX(1, 85, 5, N, N, N, N),
- MUX(1, 86, 5, N, N, N, N),
- MUX(1, 87, 5, N, N, N, N),
- MUX(1, 88, 5, N, N, N, N),
- MUX(1, 89, 5, N, N, N, N),
- MUX(1, 90, 5, N, N, N, N),
-};
-
-static struct atlas7_grp_mux ca_bt_lpc_grp_mux = {
- .pad_mux_count = ARRAY_SIZE(ca_bt_lpc_grp_pad_mux),
- .pad_mux_list = ca_bt_lpc_grp_pad_mux,
-};
-
-static struct atlas7_pad_mux ca_coex_grp_pad_mux[] = {
- MUX(1, 129, 1, N, N, N, N),
- MUX(1, 130, 1, N, N, N, N),
- MUX(1, 131, 1, N, N, N, N),
- MUX(1, 132, 1, N, N, N, N),
-};
-
-static struct atlas7_grp_mux ca_coex_grp_mux = {
- .pad_mux_count = ARRAY_SIZE(ca_coex_grp_pad_mux),
- .pad_mux_list = ca_coex_grp_pad_mux,
-};
-
-static struct atlas7_pad_mux ca_curator_lpc_grp_pad_mux[] = {
- MUX(1, 57, 4, N, N, N, N),
- MUX(1, 58, 4, N, N, N, N),
- MUX(1, 59, 4, N, N, N, N),
- MUX(1, 60, 4, N, N, N, N),
-};
-
-static struct atlas7_grp_mux ca_curator_lpc_grp_mux = {
- .pad_mux_count = ARRAY_SIZE(ca_curator_lpc_grp_pad_mux),
- .pad_mux_list = ca_curator_lpc_grp_pad_mux,
-};
-
-static struct atlas7_pad_mux ca_pcm_debug_grp_pad_mux[] = {
- MUX(1, 91, 5, N, N, N, N),
- MUX(1, 93, 5, N, N, N, N),
- MUX(1, 94, 5, N, N, N, N),
- MUX(1, 92, 5, N, N, N, N),
-};
-
-static struct atlas7_grp_mux ca_pcm_debug_grp_mux = {
- .pad_mux_count = ARRAY_SIZE(ca_pcm_debug_grp_pad_mux),
- .pad_mux_list = ca_pcm_debug_grp_pad_mux,
-};
-
-static struct atlas7_pad_mux ca_pio_grp_pad_mux[] = {
- MUX(1, 121, 2, N, N, N, N),
- MUX(1, 122, 2, N, N, N, N),
- MUX(1, 125, 6, N, N, N, N),
- MUX(1, 126, 6, N, N, N, N),
- MUX(1, 38, 5, N, N, N, N),
- MUX(1, 37, 5, N, N, N, N),
- MUX(1, 47, 5, N, N, N, N),
- MUX(1, 49, 5, N, N, N, N),
- MUX(1, 50, 5, N, N, N, N),
- MUX(1, 54, 4, N, N, N, N),
- MUX(1, 55, 4, N, N, N, N),
- MUX(1, 56, 4, N, N, N, N),
-};
-
-static struct atlas7_grp_mux ca_pio_grp_mux = {
- .pad_mux_count = ARRAY_SIZE(ca_pio_grp_pad_mux),
- .pad_mux_list = ca_pio_grp_pad_mux,
-};
-
-static struct atlas7_pad_mux ca_sdio_debug_grp_pad_mux[] = {
- MUX(1, 40, 5, N, N, N, N),
- MUX(1, 39, 5, N, N, N, N),
- MUX(1, 44, 5, N, N, N, N),
- MUX(1, 43, 5, N, N, N, N),
- MUX(1, 42, 5, N, N, N, N),
- MUX(1, 41, 5, N, N, N, N),
-};
-
-static struct atlas7_grp_mux ca_sdio_debug_grp_mux = {
- .pad_mux_count = ARRAY_SIZE(ca_sdio_debug_grp_pad_mux),
- .pad_mux_list = ca_sdio_debug_grp_pad_mux,
-};
-
-static struct atlas7_pad_mux ca_spi_grp_pad_mux[] = {
- MUX(1, 82, 5, N, N, N, N),
- MUX(1, 79, 5, 0xa08, 6, 0xa88, 6),
- MUX(1, 80, 5, N, N, N, N),
- MUX(1, 81, 5, N, N, N, N),
-};
-
-static struct atlas7_grp_mux ca_spi_grp_mux = {
- .pad_mux_count = ARRAY_SIZE(ca_spi_grp_pad_mux),
- .pad_mux_list = ca_spi_grp_pad_mux,
-};
-
-static struct atlas7_pad_mux ca_trb_grp_pad_mux[] = {
- MUX(1, 91, 4, N, N, N, N),
- MUX(1, 93, 4, N, N, N, N),
- MUX(1, 94, 4, N, N, N, N),
- MUX(1, 95, 4, N, N, N, N),
- MUX(1, 96, 4, N, N, N, N),
- MUX(1, 78, 5, N, N, N, N),
- MUX(1, 74, 5, N, N, N, N),
- MUX(1, 75, 5, N, N, N, N),
- MUX(1, 76, 5, N, N, N, N),
- MUX(1, 77, 5, N, N, N, N),
-};
-
-static struct atlas7_grp_mux ca_trb_grp_mux = {
- .pad_mux_count = ARRAY_SIZE(ca_trb_grp_pad_mux),
- .pad_mux_list = ca_trb_grp_pad_mux,
-};
-
-static struct atlas7_pad_mux ca_uart_debug_grp_pad_mux[] = {
- MUX(1, 136, 3, N, N, N, N),
- MUX(1, 135, 3, N, N, N, N),
- MUX(1, 134, 3, N, N, N, N),
- MUX(1, 133, 3, N, N, N, N),
-};
-
-static struct atlas7_grp_mux ca_uart_debug_grp_mux = {
- .pad_mux_count = ARRAY_SIZE(ca_uart_debug_grp_pad_mux),
- .pad_mux_list = ca_uart_debug_grp_pad_mux,
-};
-
-static struct atlas7_pad_mux clkc_grp0_pad_mux[] = {
- MUX(1, 30, 2, 0xa08, 14, 0xa88, 14),
- MUX(1, 47, 6, N, N, N, N),
-};
-
-static struct atlas7_grp_mux clkc_grp0_mux = {
- .pad_mux_count = ARRAY_SIZE(clkc_grp0_pad_mux),
- .pad_mux_list = clkc_grp0_pad_mux,
-};
-
-static struct atlas7_pad_mux clkc_grp1_pad_mux[] = {
- MUX(1, 78, 3, 0xa08, 14, 0xa88, 14),
- MUX(1, 54, 5, N, N, N, N),
-};
-
-static struct atlas7_grp_mux clkc_grp1_mux = {
- .pad_mux_count = ARRAY_SIZE(clkc_grp1_pad_mux),
- .pad_mux_list = clkc_grp1_pad_mux,
-};
-
-static struct atlas7_pad_mux gn_gnss_i2c_grp_pad_mux[] = {
- MUX(1, 128, 2, N, N, N, N),
- MUX(1, 127, 2, N, N, N, N),
-};
-
-static struct atlas7_grp_mux gn_gnss_i2c_grp_mux = {
- .pad_mux_count = ARRAY_SIZE(gn_gnss_i2c_grp_pad_mux),
- .pad_mux_list = gn_gnss_i2c_grp_pad_mux,
-};
-
-static struct atlas7_pad_mux gn_gnss_uart_nopause_grp_pad_mux[] = {
- MUX(1, 134, 4, N, N, N, N),
- MUX(1, 133, 4, N, N, N, N),
-};
-
-static struct atlas7_grp_mux gn_gnss_uart_nopause_grp_mux = {
- .pad_mux_count = ARRAY_SIZE(gn_gnss_uart_nopause_grp_pad_mux),
- .pad_mux_list = gn_gnss_uart_nopause_grp_pad_mux,
-};
-
-static struct atlas7_pad_mux gn_gnss_uart_grp_pad_mux[] = {
- MUX(1, 134, 4, N, N, N, N),
- MUX(1, 133, 4, N, N, N, N),
- MUX(1, 136, 4, N, N, N, N),
- MUX(1, 135, 4, N, N, N, N),
-};
-
-static struct atlas7_grp_mux gn_gnss_uart_grp_mux = {
- .pad_mux_count = ARRAY_SIZE(gn_gnss_uart_grp_pad_mux),
- .pad_mux_list = gn_gnss_uart_grp_pad_mux,
-};
-
-static struct atlas7_pad_mux gn_trg_spi_grp0_pad_mux[] = {
- MUX(1, 22, 1, N, N, N, N),
- MUX(1, 25, 1, N, N, N, N),
- MUX(1, 23, 1, 0xa00, 10, 0xa80, 10),
- MUX(1, 24, 1, N, N, N, N),
-};
-
-static struct atlas7_grp_mux gn_trg_spi_grp0_mux = {
- .pad_mux_count = ARRAY_SIZE(gn_trg_spi_grp0_pad_mux),
- .pad_mux_list = gn_trg_spi_grp0_pad_mux,
-};
-
-static struct atlas7_pad_mux gn_trg_spi_grp1_pad_mux[] = {
- MUX(1, 82, 3, N, N, N, N),
- MUX(1, 79, 3, N, N, N, N),
- MUX(1, 80, 3, 0xa00, 10, 0xa80, 10),
- MUX(1, 81, 3, N, N, N, N),
-};
-
-static struct atlas7_grp_mux gn_trg_spi_grp1_mux = {
- .pad_mux_count = ARRAY_SIZE(gn_trg_spi_grp1_pad_mux),
- .pad_mux_list = gn_trg_spi_grp1_pad_mux,
-};
-
-static struct atlas7_pad_mux cvbs_dbg_grp_pad_mux[] = {
- MUX(1, 54, 3, N, N, N, N),
- MUX(1, 53, 3, N, N, N, N),
- MUX(1, 82, 7, N, N, N, N),
- MUX(1, 74, 7, N, N, N, N),
- MUX(1, 75, 7, N, N, N, N),
- MUX(1, 76, 7, N, N, N, N),
- MUX(1, 77, 7, N, N, N, N),
- MUX(1, 78, 7, N, N, N, N),
- MUX(1, 79, 7, N, N, N, N),
- MUX(1, 80, 7, N, N, N, N),
- MUX(1, 81, 7, N, N, N, N),
- MUX(1, 83, 7, N, N, N, N),
- MUX(1, 84, 7, N, N, N, N),
- MUX(1, 73, 3, N, N, N, N),
- MUX(1, 55, 3, N, N, N, N),
- MUX(1, 56, 3, N, N, N, N),
-};
-
-static struct atlas7_grp_mux cvbs_dbg_grp_mux = {
- .pad_mux_count = ARRAY_SIZE(cvbs_dbg_grp_pad_mux),
- .pad_mux_list = cvbs_dbg_grp_pad_mux,
-};
-
-static struct atlas7_pad_mux cvbs_dbg_test_grp0_pad_mux[] = {
- MUX(1, 57, 3, N, N, N, N),
-};
-
-static struct atlas7_grp_mux cvbs_dbg_test_grp0_mux = {
- .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp0_pad_mux),
- .pad_mux_list = cvbs_dbg_test_grp0_pad_mux,
-};
-
-static struct atlas7_pad_mux cvbs_dbg_test_grp1_pad_mux[] = {
- MUX(1, 58, 3, N, N, N, N),
-};
-
-static struct atlas7_grp_mux cvbs_dbg_test_grp1_mux = {
- .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp1_pad_mux),
- .pad_mux_list = cvbs_dbg_test_grp1_pad_mux,
-};
-
-static struct atlas7_pad_mux cvbs_dbg_test_grp2_pad_mux[] = {
- MUX(1, 59, 3, N, N, N, N),
-};
-
-static struct atlas7_grp_mux cvbs_dbg_test_grp2_mux = {
- .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp2_pad_mux),
- .pad_mux_list = cvbs_dbg_test_grp2_pad_mux,
-};
-
-static struct atlas7_pad_mux cvbs_dbg_test_grp3_pad_mux[] = {
- MUX(1, 60, 3, N, N, N, N),
-};
-
-static struct atlas7_grp_mux cvbs_dbg_test_grp3_mux = {
- .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp3_pad_mux),
- .pad_mux_list = cvbs_dbg_test_grp3_pad_mux,
-};
-
-static struct atlas7_pad_mux cvbs_dbg_test_grp4_pad_mux[] = {
- MUX(1, 61, 3, N, N, N, N),
-};
-
-static struct atlas7_grp_mux cvbs_dbg_test_grp4_mux = {
- .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp4_pad_mux),
- .pad_mux_list = cvbs_dbg_test_grp4_pad_mux,
-};
-
-static struct atlas7_pad_mux cvbs_dbg_test_grp5_pad_mux[] = {
- MUX(1, 62, 3, N, N, N, N),
-};
-
-static struct atlas7_grp_mux cvbs_dbg_test_grp5_mux = {
- .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp5_pad_mux),
- .pad_mux_list = cvbs_dbg_test_grp5_pad_mux,
-};
-
-static struct atlas7_pad_mux cvbs_dbg_test_grp6_pad_mux[] = {
- MUX(1, 63, 3, N, N, N, N),
-};
-
-static struct atlas7_grp_mux cvbs_dbg_test_grp6_mux = {
- .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp6_pad_mux),
- .pad_mux_list = cvbs_dbg_test_grp6_pad_mux,
-};
-
-static struct atlas7_pad_mux cvbs_dbg_test_grp7_pad_mux[] = {
- MUX(1, 64, 3, N, N, N, N),
-};
-
-static struct atlas7_grp_mux cvbs_dbg_test_grp7_mux = {
- .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp7_pad_mux),
- .pad_mux_list = cvbs_dbg_test_grp7_pad_mux,
-};
-
-static struct atlas7_pad_mux cvbs_dbg_test_grp8_pad_mux[] = {
- MUX(1, 65, 3, N, N, N, N),
-};
-
-static struct atlas7_grp_mux cvbs_dbg_test_grp8_mux = {
- .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp8_pad_mux),
- .pad_mux_list = cvbs_dbg_test_grp8_pad_mux,
-};
-
-static struct atlas7_pad_mux cvbs_dbg_test_grp9_pad_mux[] = {
- MUX(1, 66, 3, N, N, N, N),
-};
-
-static struct atlas7_grp_mux cvbs_dbg_test_grp9_mux = {
- .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp9_pad_mux),
- .pad_mux_list = cvbs_dbg_test_grp9_pad_mux,
-};
-
-static struct atlas7_pad_mux cvbs_dbg_test_grp10_pad_mux[] = {
- MUX(1, 67, 3, N, N, N, N),
-};
-
-static struct atlas7_grp_mux cvbs_dbg_test_grp10_mux = {
- .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp10_pad_mux),
- .pad_mux_list = cvbs_dbg_test_grp10_pad_mux,
-};
-
-static struct atlas7_pad_mux cvbs_dbg_test_grp11_pad_mux[] = {
- MUX(1, 68, 3, N, N, N, N),
-};
-
-static struct atlas7_grp_mux cvbs_dbg_test_grp11_mux = {
- .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp11_pad_mux),
- .pad_mux_list = cvbs_dbg_test_grp11_pad_mux,
-};
-
-static struct atlas7_pad_mux cvbs_dbg_test_grp12_pad_mux[] = {
- MUX(1, 69, 3, N, N, N, N),
-};
-
-static struct atlas7_grp_mux cvbs_dbg_test_grp12_mux = {
- .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp12_pad_mux),
- .pad_mux_list = cvbs_dbg_test_grp12_pad_mux,
-};
-
-static struct atlas7_pad_mux cvbs_dbg_test_grp13_pad_mux[] = {
- MUX(1, 70, 3, N, N, N, N),
-};
-
-static struct atlas7_grp_mux cvbs_dbg_test_grp13_mux = {
- .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp13_pad_mux),
- .pad_mux_list = cvbs_dbg_test_grp13_pad_mux,
-};
-
-static struct atlas7_pad_mux cvbs_dbg_test_grp14_pad_mux[] = {
- MUX(1, 71, 3, N, N, N, N),
-};
-
-static struct atlas7_grp_mux cvbs_dbg_test_grp14_mux = {
- .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp14_pad_mux),
- .pad_mux_list = cvbs_dbg_test_grp14_pad_mux,
-};
-
-static struct atlas7_pad_mux cvbs_dbg_test_grp15_pad_mux[] = {
- MUX(1, 72, 3, N, N, N, N),
-};
-
-static struct atlas7_grp_mux cvbs_dbg_test_grp15_mux = {
- .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp15_pad_mux),
- .pad_mux_list = cvbs_dbg_test_grp15_pad_mux,
-};
-
-static struct atlas7_pad_mux gn_gnss_power_grp_pad_mux[] = {
- MUX(1, 123, 7, N, N, N, N),
- MUX(1, 124, 7, N, N, N, N),
- MUX(1, 121, 7, N, N, N, N),
- MUX(1, 122, 7, N, N, N, N),
- MUX(1, 125, 7, N, N, N, N),
- MUX(1, 120, 7, N, N, N, N),
-};
-
-static struct atlas7_grp_mux gn_gnss_power_grp_mux = {
- .pad_mux_count = ARRAY_SIZE(gn_gnss_power_grp_pad_mux),
- .pad_mux_list = gn_gnss_power_grp_pad_mux,
-};
-
-static struct atlas7_pad_mux gn_gnss_sw_status_grp_pad_mux[] = {
- MUX(1, 57, 7, N, N, N, N),
- MUX(1, 58, 7, N, N, N, N),
- MUX(1, 59, 7, N, N, N, N),
- MUX(1, 60, 7, N, N, N, N),
- MUX(1, 61, 7, N, N, N, N),
- MUX(1, 62, 7, N, N, N, N),
- MUX(1, 63, 7, N, N, N, N),
- MUX(1, 64, 7, N, N, N, N),
- MUX(1, 65, 7, N, N, N, N),
- MUX(1, 66, 7, N, N, N, N),
- MUX(1, 67, 7, N, N, N, N),
- MUX(1, 68, 7, N, N, N, N),
- MUX(1, 69, 7, N, N, N, N),
- MUX(1, 70, 7, N, N, N, N),
- MUX(1, 71, 7, N, N, N, N),
- MUX(1, 72, 7, N, N, N, N),
- MUX(1, 53, 7, N, N, N, N),
- MUX(1, 55, 7, N, N, N, N),
- MUX(1, 56, 7, 0xa08, 12, 0xa88, 12),
- MUX(1, 54, 7, N, N, N, N),
-};
-
-static struct atlas7_grp_mux gn_gnss_sw_status_grp_mux = {
- .pad_mux_count = ARRAY_SIZE(gn_gnss_sw_status_grp_pad_mux),
- .pad_mux_list = gn_gnss_sw_status_grp_pad_mux,
-};
-
-static struct atlas7_pad_mux gn_gnss_eclk_grp_pad_mux[] = {
- MUX(1, 113, 4, N, N, N, N),
-};
-
-static struct atlas7_grp_mux gn_gnss_eclk_grp_mux = {
- .pad_mux_count = ARRAY_SIZE(gn_gnss_eclk_grp_pad_mux),
- .pad_mux_list = gn_gnss_eclk_grp_pad_mux,
-};
-
-static struct atlas7_pad_mux gn_gnss_irq1_grp0_pad_mux[] = {
- MUX(1, 112, 4, 0xa08, 10, 0xa88, 10),
-};
-
-static struct atlas7_grp_mux gn_gnss_irq1_grp0_mux = {
- .pad_mux_count = ARRAY_SIZE(gn_gnss_irq1_grp0_pad_mux),
- .pad_mux_list = gn_gnss_irq1_grp0_pad_mux,
-};
-
-static struct atlas7_pad_mux gn_gnss_irq2_grp0_pad_mux[] = {
- MUX(1, 118, 4, 0xa08, 11, 0xa88, 11),
-};
-
-static struct atlas7_grp_mux gn_gnss_irq2_grp0_mux = {
- .pad_mux_count = ARRAY_SIZE(gn_gnss_irq2_grp0_pad_mux),
- .pad_mux_list = gn_gnss_irq2_grp0_pad_mux,
-};
-
-static struct atlas7_pad_mux gn_gnss_tm_grp_pad_mux[] = {
- MUX(1, 115, 4, N, N, N, N),
-};
-
-static struct atlas7_grp_mux gn_gnss_tm_grp_mux = {
- .pad_mux_count = ARRAY_SIZE(gn_gnss_tm_grp_pad_mux),
- .pad_mux_list = gn_gnss_tm_grp_pad_mux,
-};
-
-static struct atlas7_pad_mux gn_gnss_tsync_grp_pad_mux[] = {
- MUX(1, 114, 4, N, N, N, N),
-};
-
-static struct atlas7_grp_mux gn_gnss_tsync_grp_mux = {
- .pad_mux_count = ARRAY_SIZE(gn_gnss_tsync_grp_pad_mux),
- .pad_mux_list = gn_gnss_tsync_grp_pad_mux,
-};
-
-static struct atlas7_pad_mux gn_io_gnsssys_sw_cfg_grp_pad_mux[] = {
- MUX(1, 44, 7, N, N, N, N),
- MUX(1, 43, 7, N, N, N, N),
- MUX(1, 42, 7, N, N, N, N),
- MUX(1, 41, 7, N, N, N, N),
- MUX(1, 40, 7, N, N, N, N),
- MUX(1, 39, 7, N, N, N, N),
- MUX(1, 38, 7, N, N, N, N),
- MUX(1, 37, 7, N, N, N, N),
- MUX(1, 49, 7, N, N, N, N),
- MUX(1, 50, 7, N, N, N, N),
- MUX(1, 91, 7, N, N, N, N),
- MUX(1, 92, 7, N, N, N, N),
- MUX(1, 93, 7, N, N, N, N),
- MUX(1, 94, 7, N, N, N, N),
- MUX(1, 95, 7, N, N, N, N),
- MUX(1, 96, 7, N, N, N, N),
-};
-
-static struct atlas7_grp_mux gn_io_gnsssys_sw_cfg_grp_mux = {
- .pad_mux_count = ARRAY_SIZE(gn_io_gnsssys_sw_cfg_grp_pad_mux),
- .pad_mux_list = gn_io_gnsssys_sw_cfg_grp_pad_mux,
-};
-
-static struct atlas7_pad_mux gn_trg_grp0_pad_mux[] = {
- MUX(1, 29, 1, 0xa00, 6, 0xa80, 6),
- MUX(1, 28, 1, 0xa00, 7, 0xa80, 7),
- MUX(1, 26, 1, 0xa00, 8, 0xa80, 8),
- MUX(1, 27, 1, 0xa00, 9, 0xa80, 9),
-};
-
-static struct atlas7_grp_mux gn_trg_grp0_mux = {
- .pad_mux_count = ARRAY_SIZE(gn_trg_grp0_pad_mux),
- .pad_mux_list = gn_trg_grp0_pad_mux,
-};
-
-static struct atlas7_pad_mux gn_trg_grp1_pad_mux[] = {
- MUX(1, 77, 3, 0xa00, 6, 0xa80, 6),
- MUX(1, 76, 3, 0xa00, 7, 0xa80, 7),
- MUX(1, 74, 3, 0xa00, 8, 0xa80, 8),
- MUX(1, 75, 3, 0xa00, 9, 0xa80, 9),
-};
-
-static struct atlas7_grp_mux gn_trg_grp1_mux = {
- .pad_mux_count = ARRAY_SIZE(gn_trg_grp1_pad_mux),
- .pad_mux_list = gn_trg_grp1_pad_mux,
-};
-
-static struct atlas7_pad_mux gn_trg_shutdown_grp0_pad_mux[] = {
- MUX(1, 30, 1, N, N, N, N),
-};
-
-static struct atlas7_grp_mux gn_trg_shutdown_grp0_mux = {
- .pad_mux_count = ARRAY_SIZE(gn_trg_shutdown_grp0_pad_mux),
- .pad_mux_list = gn_trg_shutdown_grp0_pad_mux,
-};
-
-static struct atlas7_pad_mux gn_trg_shutdown_grp1_pad_mux[] = {
- MUX(1, 83, 3, N, N, N, N),
-};
-
-static struct atlas7_grp_mux gn_trg_shutdown_grp1_mux = {
- .pad_mux_count = ARRAY_SIZE(gn_trg_shutdown_grp1_pad_mux),
- .pad_mux_list = gn_trg_shutdown_grp1_pad_mux,
-};
-
-static struct atlas7_pad_mux gn_trg_shutdown_grp2_pad_mux[] = {
- MUX(1, 117, 4, N, N, N, N),
-};
-
-static struct atlas7_grp_mux gn_trg_shutdown_grp2_mux = {
- .pad_mux_count = ARRAY_SIZE(gn_trg_shutdown_grp2_pad_mux),
- .pad_mux_list = gn_trg_shutdown_grp2_pad_mux,
-};
-
-static struct atlas7_pad_mux gn_trg_shutdown_grp3_pad_mux[] = {
- MUX(1, 123, 5, N, N, N, N),
-};
-
-static struct atlas7_grp_mux gn_trg_shutdown_grp3_mux = {
- .pad_mux_count = ARRAY_SIZE(gn_trg_shutdown_grp3_pad_mux),
- .pad_mux_list = gn_trg_shutdown_grp3_pad_mux,
-};
-
-static struct atlas7_pad_mux i2c0_grp_pad_mux[] = {
- MUX(1, 128, 1, N, N, N, N),
- MUX(1, 127, 1, N, N, N, N),
-};
-
-static struct atlas7_grp_mux i2c0_grp_mux = {
- .pad_mux_count = ARRAY_SIZE(i2c0_grp_pad_mux),
- .pad_mux_list = i2c0_grp_pad_mux,
-};
-
-static struct atlas7_pad_mux i2c1_grp_pad_mux[] = {
- MUX(1, 126, 4, N, N, N, N),
- MUX(1, 125, 4, N, N, N, N),
-};
-
-static struct atlas7_grp_mux i2c1_grp_mux = {
- .pad_mux_count = ARRAY_SIZE(i2c1_grp_pad_mux),
- .pad_mux_list = i2c1_grp_pad_mux,
-};
-
-static struct atlas7_pad_mux i2s0_grp_pad_mux[] = {
- MUX(1, 91, 2, 0xa10, 12, 0xa90, 12),
- MUX(1, 93, 2, 0xa10, 13, 0xa90, 13),
- MUX(1, 94, 2, 0xa10, 14, 0xa90, 14),
- MUX(1, 92, 2, 0xa10, 15, 0xa90, 15),
-};
-
-static struct atlas7_grp_mux i2s0_grp_mux = {
- .pad_mux_count = ARRAY_SIZE(i2s0_grp_pad_mux),
- .pad_mux_list = i2s0_grp_pad_mux,
-};
-
-static struct atlas7_pad_mux i2s1_basic_grp_pad_mux[] = {
- MUX(1, 95, 2, 0xa10, 16, 0xa90, 16),
- MUX(1, 96, 2, 0xa10, 19, 0xa90, 19),
-};
-
-static struct atlas7_grp_mux i2s1_basic_grp_mux = {
- .pad_mux_count = ARRAY_SIZE(i2s1_basic_grp_pad_mux),
- .pad_mux_list = i2s1_basic_grp_pad_mux,
-};
-
-static struct atlas7_pad_mux i2s1_rxd0_grp0_pad_mux[] = {
- MUX(1, 61, 4, 0xa10, 17, 0xa90, 17),
-};
-
-static struct atlas7_grp_mux i2s1_rxd0_grp0_mux = {
- .pad_mux_count = ARRAY_SIZE(i2s1_rxd0_grp0_pad_mux),
- .pad_mux_list = i2s1_rxd0_grp0_pad_mux,
-};
-
-static struct atlas7_pad_mux i2s1_rxd0_grp1_pad_mux[] = {
- MUX(1, 131, 4, 0xa10, 17, 0xa90, 17),
-};
-
-static struct atlas7_grp_mux i2s1_rxd0_grp1_mux = {
- .pad_mux_count = ARRAY_SIZE(i2s1_rxd0_grp1_pad_mux),
- .pad_mux_list = i2s1_rxd0_grp1_pad_mux,
-};
-
-static struct atlas7_pad_mux i2s1_rxd0_grp2_pad_mux[] = {
- MUX(1, 129, 2, 0xa10, 17, 0xa90, 17),
-};
-
-static struct atlas7_grp_mux i2s1_rxd0_grp2_mux = {
- .pad_mux_count = ARRAY_SIZE(i2s1_rxd0_grp2_pad_mux),
- .pad_mux_list = i2s1_rxd0_grp2_pad_mux,
-};
-
-static struct atlas7_pad_mux i2s1_rxd0_grp3_pad_mux[] = {
- MUX(1, 117, 7, 0xa10, 17, 0xa90, 17),
-};
-
-static struct atlas7_grp_mux i2s1_rxd0_grp3_mux = {
- .pad_mux_count = ARRAY_SIZE(i2s1_rxd0_grp3_pad_mux),
- .pad_mux_list = i2s1_rxd0_grp3_pad_mux,
-};
-
-static struct atlas7_pad_mux i2s1_rxd0_grp4_pad_mux[] = {
- MUX(1, 83, 4, 0xa10, 17, 0xa90, 17),
-};
-
-static struct atlas7_grp_mux i2s1_rxd0_grp4_mux = {
- .pad_mux_count = ARRAY_SIZE(i2s1_rxd0_grp4_pad_mux),
- .pad_mux_list = i2s1_rxd0_grp4_pad_mux,
-};
-
-static struct atlas7_pad_mux i2s1_rxd1_grp0_pad_mux[] = {
- MUX(1, 72, 4, 0xa10, 18, 0xa90, 18),
-};
-
-static struct atlas7_grp_mux i2s1_rxd1_grp0_mux = {
- .pad_mux_count = ARRAY_SIZE(i2s1_rxd1_grp0_pad_mux),
- .pad_mux_list = i2s1_rxd1_grp0_pad_mux,
-};
-
-static struct atlas7_pad_mux i2s1_rxd1_grp1_pad_mux[] = {
- MUX(1, 132, 4, 0xa10, 18, 0xa90, 18),
-};
-
-static struct atlas7_grp_mux i2s1_rxd1_grp1_mux = {
- .pad_mux_count = ARRAY_SIZE(i2s1_rxd1_grp1_pad_mux),
- .pad_mux_list = i2s1_rxd1_grp1_pad_mux,
-};
-
-static struct atlas7_pad_mux i2s1_rxd1_grp2_pad_mux[] = {
- MUX(1, 130, 2, 0xa10, 18, 0xa90, 18),
-};
-
-static struct atlas7_grp_mux i2s1_rxd1_grp2_mux = {
- .pad_mux_count = ARRAY_SIZE(i2s1_rxd1_grp2_pad_mux),
- .pad_mux_list = i2s1_rxd1_grp2_pad_mux,
-};
-
-static struct atlas7_pad_mux i2s1_rxd1_grp3_pad_mux[] = {
- MUX(1, 118, 7, 0xa10, 18, 0xa90, 18),
-};
-
-static struct atlas7_grp_mux i2s1_rxd1_grp3_mux = {
- .pad_mux_count = ARRAY_SIZE(i2s1_rxd1_grp3_pad_mux),
- .pad_mux_list = i2s1_rxd1_grp3_pad_mux,
-};
-
-static struct atlas7_pad_mux i2s1_rxd1_grp4_pad_mux[] = {
- MUX(1, 84, 4, 0xa10, 18, 0xa90, 18),
-};
-
-static struct atlas7_grp_mux i2s1_rxd1_grp4_mux = {
- .pad_mux_count = ARRAY_SIZE(i2s1_rxd1_grp4_pad_mux),
- .pad_mux_list = i2s1_rxd1_grp4_pad_mux,
-};
-
-static struct atlas7_pad_mux jtag_jt_dbg_nsrst_grp_pad_mux[] = {
- MUX(1, 125, 5, 0xa08, 2, 0xa88, 2),
-};
-
-static struct atlas7_grp_mux jtag_jt_dbg_nsrst_grp_mux = {
- .pad_mux_count = ARRAY_SIZE(jtag_jt_dbg_nsrst_grp_pad_mux),
- .pad_mux_list = jtag_jt_dbg_nsrst_grp_pad_mux,
-};
-
-static struct atlas7_pad_mux jtag_ntrst_grp0_pad_mux[] = {
- MUX(0, 4, 3, 0xa08, 3, 0xa88, 3),
-};
-
-static struct atlas7_grp_mux jtag_ntrst_grp0_mux = {
- .pad_mux_count = ARRAY_SIZE(jtag_ntrst_grp0_pad_mux),
- .pad_mux_list = jtag_ntrst_grp0_pad_mux,
-};
-
-static struct atlas7_pad_mux jtag_ntrst_grp1_pad_mux[] = {
- MUX(1, 163, 1, 0xa08, 3, 0xa88, 3),
-};
-
-static struct atlas7_grp_mux jtag_ntrst_grp1_mux = {
- .pad_mux_count = ARRAY_SIZE(jtag_ntrst_grp1_pad_mux),
- .pad_mux_list = jtag_ntrst_grp1_pad_mux,
-};
-
-static struct atlas7_pad_mux jtag_swdiotms_grp0_pad_mux[] = {
- MUX(0, 2, 3, 0xa10, 10, 0xa90, 10),
-};
-
-static struct atlas7_grp_mux jtag_swdiotms_grp0_mux = {
- .pad_mux_count = ARRAY_SIZE(jtag_swdiotms_grp0_pad_mux),
- .pad_mux_list = jtag_swdiotms_grp0_pad_mux,
-};
-
-static struct atlas7_pad_mux jtag_swdiotms_grp1_pad_mux[] = {
- MUX(1, 160, 1, 0xa10, 10, 0xa90, 10),
-};
-
-static struct atlas7_grp_mux jtag_swdiotms_grp1_mux = {
- .pad_mux_count = ARRAY_SIZE(jtag_swdiotms_grp1_pad_mux),
- .pad_mux_list = jtag_swdiotms_grp1_pad_mux,
-};
-
-static struct atlas7_pad_mux jtag_tck_grp0_pad_mux[] = {
- MUX(0, 0, 3, 0xa10, 11, 0xa90, 11),
-};
-
-static struct atlas7_grp_mux jtag_tck_grp0_mux = {
- .pad_mux_count = ARRAY_SIZE(jtag_tck_grp0_pad_mux),
- .pad_mux_list = jtag_tck_grp0_pad_mux,
-};
-
-static struct atlas7_pad_mux jtag_tck_grp1_pad_mux[] = {
- MUX(1, 161, 1, 0xa10, 11, 0xa90, 11),
-};
-
-static struct atlas7_grp_mux jtag_tck_grp1_mux = {
- .pad_mux_count = ARRAY_SIZE(jtag_tck_grp1_pad_mux),
- .pad_mux_list = jtag_tck_grp1_pad_mux,
-};
-
-static struct atlas7_pad_mux jtag_tdi_grp0_pad_mux[] = {
- MUX(0, 1, 3, 0xa10, 31, 0xa90, 31),
-};
-
-static struct atlas7_grp_mux jtag_tdi_grp0_mux = {
- .pad_mux_count = ARRAY_SIZE(jtag_tdi_grp0_pad_mux),
- .pad_mux_list = jtag_tdi_grp0_pad_mux,
-};
-
-static struct atlas7_pad_mux jtag_tdi_grp1_pad_mux[] = {
- MUX(1, 162, 1, 0xa10, 31, 0xa90, 31),
-};
-
-static struct atlas7_grp_mux jtag_tdi_grp1_mux = {
- .pad_mux_count = ARRAY_SIZE(jtag_tdi_grp1_pad_mux),
- .pad_mux_list = jtag_tdi_grp1_pad_mux,
-};
-
-static struct atlas7_pad_mux jtag_tdo_grp0_pad_mux[] = {
- MUX(0, 3, 3, N, N, N, N),
-};
-
-static struct atlas7_grp_mux jtag_tdo_grp0_mux = {
- .pad_mux_count = ARRAY_SIZE(jtag_tdo_grp0_pad_mux),
- .pad_mux_list = jtag_tdo_grp0_pad_mux,
-};
-
-static struct atlas7_pad_mux jtag_tdo_grp1_pad_mux[] = {
- MUX(1, 159, 1, N, N, N, N),
-};
-
-static struct atlas7_grp_mux jtag_tdo_grp1_mux = {
- .pad_mux_count = ARRAY_SIZE(jtag_tdo_grp1_pad_mux),
- .pad_mux_list = jtag_tdo_grp1_pad_mux,
-};
-
-static struct atlas7_pad_mux ks_kas_spi_grp0_pad_mux[] = {
- MUX(1, 141, 2, N, N, N, N),
- MUX(1, 144, 2, 0xa08, 8, 0xa88, 8),
- MUX(1, 143, 2, N, N, N, N),
- MUX(1, 142, 2, N, N, N, N),
-};
-
-static struct atlas7_grp_mux ks_kas_spi_grp0_mux = {
- .pad_mux_count = ARRAY_SIZE(ks_kas_spi_grp0_pad_mux),
- .pad_mux_list = ks_kas_spi_grp0_pad_mux,
-};
-
-static struct atlas7_pad_mux ld_ldd_grp_pad_mux[] = {
- MUX(1, 57, 1, N, N, N, N),
- MUX(1, 58, 1, N, N, N, N),
- MUX(1, 59, 1, N, N, N, N),
- MUX(1, 60, 1, N, N, N, N),
- MUX(1, 61, 1, N, N, N, N),
- MUX(1, 62, 1, N, N, N, N),
- MUX(1, 63, 1, N, N, N, N),
- MUX(1, 64, 1, N, N, N, N),
- MUX(1, 65, 1, N, N, N, N),
- MUX(1, 66, 1, N, N, N, N),
- MUX(1, 67, 1, N, N, N, N),
- MUX(1, 68, 1, N, N, N, N),
- MUX(1, 69, 1, N, N, N, N),
- MUX(1, 70, 1, N, N, N, N),
- MUX(1, 71, 1, N, N, N, N),
- MUX(1, 72, 1, N, N, N, N),
- MUX(1, 74, 2, N, N, N, N),
- MUX(1, 75, 2, N, N, N, N),
- MUX(1, 76, 2, N, N, N, N),
- MUX(1, 77, 2, N, N, N, N),
- MUX(1, 78, 2, N, N, N, N),
- MUX(1, 79, 2, N, N, N, N),
- MUX(1, 80, 2, N, N, N, N),
- MUX(1, 81, 2, N, N, N, N),
- MUX(1, 56, 1, N, N, N, N),
- MUX(1, 53, 1, N, N, N, N),
-};
-
-static struct atlas7_grp_mux ld_ldd_grp_mux = {
- .pad_mux_count = ARRAY_SIZE(ld_ldd_grp_pad_mux),
- .pad_mux_list = ld_ldd_grp_pad_mux,
-};
-
-static struct atlas7_pad_mux ld_ldd_16bit_grp_pad_mux[] = {
- MUX(1, 57, 1, N, N, N, N),
- MUX(1, 58, 1, N, N, N, N),
- MUX(1, 59, 1, N, N, N, N),
- MUX(1, 60, 1, N, N, N, N),
- MUX(1, 61, 1, N, N, N, N),
- MUX(1, 62, 1, N, N, N, N),
- MUX(1, 63, 1, N, N, N, N),
- MUX(1, 64, 1, N, N, N, N),
- MUX(1, 65, 1, N, N, N, N),
- MUX(1, 66, 1, N, N, N, N),
- MUX(1, 67, 1, N, N, N, N),
- MUX(1, 68, 1, N, N, N, N),
- MUX(1, 69, 1, N, N, N, N),
- MUX(1, 70, 1, N, N, N, N),
- MUX(1, 71, 1, N, N, N, N),
- MUX(1, 72, 1, N, N, N, N),
- MUX(1, 56, 1, N, N, N, N),
- MUX(1, 53, 1, N, N, N, N),
-};
-
-static struct atlas7_grp_mux ld_ldd_16bit_grp_mux = {
- .pad_mux_count = ARRAY_SIZE(ld_ldd_16bit_grp_pad_mux),
- .pad_mux_list = ld_ldd_16bit_grp_pad_mux,
-};
-
-static struct atlas7_pad_mux ld_ldd_fck_grp_pad_mux[] = {
- MUX(1, 55, 1, N, N, N, N),
-};
-
-static struct atlas7_grp_mux ld_ldd_fck_grp_mux = {
- .pad_mux_count = ARRAY_SIZE(ld_ldd_fck_grp_pad_mux),
- .pad_mux_list = ld_ldd_fck_grp_pad_mux,
-};
-
-static struct atlas7_pad_mux ld_ldd_lck_grp_pad_mux[] = {
- MUX(1, 54, 1, N, N, N, N),
-};
-
-static struct atlas7_grp_mux ld_ldd_lck_grp_mux = {
- .pad_mux_count = ARRAY_SIZE(ld_ldd_lck_grp_pad_mux),
- .pad_mux_list = ld_ldd_lck_grp_pad_mux,
-};
-
-static struct atlas7_pad_mux lr_lcdrom_grp_pad_mux[] = {
- MUX(1, 73, 2, N, N, N, N),
- MUX(1, 54, 2, N, N, N, N),
- MUX(1, 57, 2, N, N, N, N),
- MUX(1, 58, 2, N, N, N, N),
- MUX(1, 59, 2, N, N, N, N),
- MUX(1, 60, 2, N, N, N, N),
- MUX(1, 61, 2, N, N, N, N),
- MUX(1, 62, 2, N, N, N, N),
- MUX(1, 63, 2, N, N, N, N),
- MUX(1, 64, 2, N, N, N, N),
- MUX(1, 65, 2, N, N, N, N),
- MUX(1, 66, 2, N, N, N, N),
- MUX(1, 67, 2, N, N, N, N),
- MUX(1, 68, 2, N, N, N, N),
- MUX(1, 69, 2, N, N, N, N),
- MUX(1, 70, 2, N, N, N, N),
- MUX(1, 71, 2, N, N, N, N),
- MUX(1, 72, 2, N, N, N, N),
- MUX(1, 56, 2, N, N, N, N),
- MUX(1, 53, 2, N, N, N, N),
- MUX(1, 55, 2, N, N, N, N),
-};
-
-static struct atlas7_grp_mux lr_lcdrom_grp_mux = {
- .pad_mux_count = ARRAY_SIZE(lr_lcdrom_grp_pad_mux),
- .pad_mux_list = lr_lcdrom_grp_pad_mux,
-};
-
-static struct atlas7_pad_mux lvds_analog_grp_pad_mux[] = {
- MUX(1, 149, 8, N, N, N, N),
- MUX(1, 150, 8, N, N, N, N),
- MUX(1, 151, 8, N, N, N, N),
- MUX(1, 152, 8, N, N, N, N),
- MUX(1, 153, 8, N, N, N, N),
- MUX(1, 154, 8, N, N, N, N),
- MUX(1, 155, 8, N, N, N, N),
- MUX(1, 156, 8, N, N, N, N),
- MUX(1, 157, 8, N, N, N, N),
- MUX(1, 158, 8, N, N, N, N),
-};
-
-static struct atlas7_grp_mux lvds_analog_grp_mux = {
- .pad_mux_count = ARRAY_SIZE(lvds_analog_grp_pad_mux),
- .pad_mux_list = lvds_analog_grp_pad_mux,
-};
-
-static struct atlas7_pad_mux nd_df_basic_grp_pad_mux[] = {
- MUX(1, 44, 1, N, N, N, N),
- MUX(1, 43, 1, N, N, N, N),
- MUX(1, 42, 1, N, N, N, N),
- MUX(1, 41, 1, N, N, N, N),
- MUX(1, 40, 1, N, N, N, N),
- MUX(1, 39, 1, N, N, N, N),
- MUX(1, 38, 1, N, N, N, N),
- MUX(1, 37, 1, N, N, N, N),
- MUX(1, 47, 1, N, N, N, N),
- MUX(1, 46, 1, N, N, N, N),
- MUX(1, 52, 1, N, N, N, N),
- MUX(1, 45, 1, N, N, N, N),
- MUX(1, 49, 1, N, N, N, N),
- MUX(1, 50, 1, N, N, N, N),
- MUX(1, 48, 1, N, N, N, N),
-};
-
-static struct atlas7_grp_mux nd_df_basic_grp_mux = {
- .pad_mux_count = ARRAY_SIZE(nd_df_basic_grp_pad_mux),
- .pad_mux_list = nd_df_basic_grp_pad_mux,
-};
-
-static struct atlas7_pad_mux nd_df_wp_grp_pad_mux[] = {
- MUX(1, 124, 4, N, N, N, N),
-};
-
-static struct atlas7_grp_mux nd_df_wp_grp_mux = {
- .pad_mux_count = ARRAY_SIZE(nd_df_wp_grp_pad_mux),
- .pad_mux_list = nd_df_wp_grp_pad_mux,
-};
-
-static struct atlas7_pad_mux nd_df_cs_grp_pad_mux[] = {
- MUX(1, 51, 1, N, N, N, N),
-};
-
-static struct atlas7_grp_mux nd_df_cs_grp_mux = {
- .pad_mux_count = ARRAY_SIZE(nd_df_cs_grp_pad_mux),
- .pad_mux_list = nd_df_cs_grp_pad_mux,
-};
-
-static struct atlas7_pad_mux ps_grp_pad_mux[] = {
- MUX(1, 120, 2, N, N, N, N),
- MUX(1, 119, 2, N, N, N, N),
- MUX(1, 121, 5, N, N, N, N),
-};
-
-static struct atlas7_grp_mux ps_grp_mux = {
- .pad_mux_count = ARRAY_SIZE(ps_grp_pad_mux),
- .pad_mux_list = ps_grp_pad_mux,
-};
-
-static struct atlas7_pad_mux ps_no_dir_grp_pad_mux[] = {
- MUX(1, 119, 2, N, N, N, N),
-};
-
-static struct atlas7_grp_mux ps_no_dir_grp_mux = {
- .pad_mux_count = ARRAY_SIZE(ps_no_dir_grp_pad_mux),
- .pad_mux_list = ps_no_dir_grp_pad_mux,
-};
-
-static struct atlas7_pad_mux pwc_core_on_grp_pad_mux[] = {
- MUX(0, 8, 1, N, N, N, N),
-};
-
-static struct atlas7_grp_mux pwc_core_on_grp_mux = {
- .pad_mux_count = ARRAY_SIZE(pwc_core_on_grp_pad_mux),
- .pad_mux_list = pwc_core_on_grp_pad_mux,
-};
-
-static struct atlas7_pad_mux pwc_ext_on_grp_pad_mux[] = {
- MUX(0, 6, 1, N, N, N, N),
-};
-
-static struct atlas7_grp_mux pwc_ext_on_grp_mux = {
- .pad_mux_count = ARRAY_SIZE(pwc_ext_on_grp_pad_mux),
- .pad_mux_list = pwc_ext_on_grp_pad_mux,
-};
-
-static struct atlas7_pad_mux pwc_gpio3_clk_grp_pad_mux[] = {
- MUX(0, 3, 4, N, N, N, N),
-};
-
-static struct atlas7_grp_mux pwc_gpio3_clk_grp_mux = {
- .pad_mux_count = ARRAY_SIZE(pwc_gpio3_clk_grp_pad_mux),
- .pad_mux_list = pwc_gpio3_clk_grp_pad_mux,
-};
-
-static struct atlas7_pad_mux pwc_io_on_grp_pad_mux[] = {
- MUX(0, 9, 1, N, N, N, N),
-};
-
-static struct atlas7_grp_mux pwc_io_on_grp_mux = {
- .pad_mux_count = ARRAY_SIZE(pwc_io_on_grp_pad_mux),
- .pad_mux_list = pwc_io_on_grp_pad_mux,
-};
-
-static struct atlas7_pad_mux pwc_lowbatt_b_grp0_pad_mux[] = {
- MUX(0, 4, 1, 0xa08, 4, 0xa88, 4),
-};
-
-static struct atlas7_grp_mux pwc_lowbatt_b_grp0_mux = {
- .pad_mux_count = ARRAY_SIZE(pwc_lowbatt_b_grp0_pad_mux),
- .pad_mux_list = pwc_lowbatt_b_grp0_pad_mux,
-};
-
-static struct atlas7_pad_mux pwc_mem_on_grp_pad_mux[] = {
- MUX(0, 7, 1, N, N, N, N),
-};
-
-static struct atlas7_grp_mux pwc_mem_on_grp_mux = {
- .pad_mux_count = ARRAY_SIZE(pwc_mem_on_grp_pad_mux),
- .pad_mux_list = pwc_mem_on_grp_pad_mux,
-};
-
-static struct atlas7_pad_mux pwc_on_key_b_grp0_pad_mux[] = {
- MUX(0, 5, 1, 0xa08, 5, 0xa88, 5),
-};
-
-static struct atlas7_grp_mux pwc_on_key_b_grp0_mux = {
- .pad_mux_count = ARRAY_SIZE(pwc_on_key_b_grp0_pad_mux),
- .pad_mux_list = pwc_on_key_b_grp0_pad_mux,
-};
-
-static struct atlas7_pad_mux pwc_wakeup_src0_grp_pad_mux[] = {
- MUX(0, 0, 1, N, N, N, N),
-};
-
-static struct atlas7_grp_mux pwc_wakeup_src0_grp_mux = {
- .pad_mux_count = ARRAY_SIZE(pwc_wakeup_src0_grp_pad_mux),
- .pad_mux_list = pwc_wakeup_src0_grp_pad_mux,
-};
-
-static struct atlas7_pad_mux pwc_wakeup_src1_grp_pad_mux[] = {
- MUX(0, 1, 1, N, N, N, N),
-};
-
-static struct atlas7_grp_mux pwc_wakeup_src1_grp_mux = {
- .pad_mux_count = ARRAY_SIZE(pwc_wakeup_src1_grp_pad_mux),
- .pad_mux_list = pwc_wakeup_src1_grp_pad_mux,
-};
-
-static struct atlas7_pad_mux pwc_wakeup_src2_grp_pad_mux[] = {
- MUX(0, 2, 1, N, N, N, N),
-};
-
-static struct atlas7_grp_mux pwc_wakeup_src2_grp_mux = {
- .pad_mux_count = ARRAY_SIZE(pwc_wakeup_src2_grp_pad_mux),
- .pad_mux_list = pwc_wakeup_src2_grp_pad_mux,
-};
-
-static struct atlas7_pad_mux pwc_wakeup_src3_grp_pad_mux[] = {
- MUX(0, 3, 1, N, N, N, N),
-};
-
-static struct atlas7_grp_mux pwc_wakeup_src3_grp_mux = {
- .pad_mux_count = ARRAY_SIZE(pwc_wakeup_src3_grp_pad_mux),
- .pad_mux_list = pwc_wakeup_src3_grp_pad_mux,
-};
-
-static struct atlas7_pad_mux pw_cko0_grp0_pad_mux[] = {
- MUX(1, 123, 3, N, N, N, N),
-};
-
-static struct atlas7_grp_mux pw_cko0_grp0_mux = {
- .pad_mux_count = ARRAY_SIZE(pw_cko0_grp0_pad_mux),
- .pad_mux_list = pw_cko0_grp0_pad_mux,
-};
-
-static struct atlas7_pad_mux pw_cko0_grp1_pad_mux[] = {
- MUX(1, 101, 4, N, N, N, N),
-};
-
-static struct atlas7_grp_mux pw_cko0_grp1_mux = {
- .pad_mux_count = ARRAY_SIZE(pw_cko0_grp1_pad_mux),
- .pad_mux_list = pw_cko0_grp1_pad_mux,
-};
-
-static struct atlas7_pad_mux pw_cko0_grp2_pad_mux[] = {
- MUX(1, 82, 2, N, N, N, N),
-};
-
-static struct atlas7_grp_mux pw_cko0_grp2_mux = {
- .pad_mux_count = ARRAY_SIZE(pw_cko0_grp2_pad_mux),
- .pad_mux_list = pw_cko0_grp2_pad_mux,
-};
-
-static struct atlas7_pad_mux pw_cko0_grp3_pad_mux[] = {
- MUX(1, 162, 5, N, N, N, N),
-};
-
-static struct atlas7_grp_mux pw_cko0_grp3_mux = {
- .pad_mux_count = ARRAY_SIZE(pw_cko0_grp3_pad_mux),
- .pad_mux_list = pw_cko0_grp3_pad_mux,
-};
-
-static struct atlas7_pad_mux pw_cko1_grp0_pad_mux[] = {
- MUX(1, 124, 3, N, N, N, N),
-};
-
-static struct atlas7_grp_mux pw_cko1_grp0_mux = {
- .pad_mux_count = ARRAY_SIZE(pw_cko1_grp0_pad_mux),
- .pad_mux_list = pw_cko1_grp0_pad_mux,
-};
-
-static struct atlas7_pad_mux pw_cko1_grp1_pad_mux[] = {
- MUX(1, 110, 4, N, N, N, N),
-};
-
-static struct atlas7_grp_mux pw_cko1_grp1_mux = {
- .pad_mux_count = ARRAY_SIZE(pw_cko1_grp1_pad_mux),
- .pad_mux_list = pw_cko1_grp1_pad_mux,
-};
-
-static struct atlas7_pad_mux pw_cko1_grp2_pad_mux[] = {
- MUX(1, 163, 5, N, N, N, N),
-};
-
-static struct atlas7_grp_mux pw_cko1_grp2_mux = {
- .pad_mux_count = ARRAY_SIZE(pw_cko1_grp2_pad_mux),
- .pad_mux_list = pw_cko1_grp2_pad_mux,
-};
-
-static struct atlas7_pad_mux pw_i2s01_clk_grp0_pad_mux[] = {
- MUX(1, 125, 3, N, N, N, N),
-};
-
-static struct atlas7_grp_mux pw_i2s01_clk_grp0_mux = {
- .pad_mux_count = ARRAY_SIZE(pw_i2s01_clk_grp0_pad_mux),
- .pad_mux_list = pw_i2s01_clk_grp0_pad_mux,
-};
-
-static struct atlas7_pad_mux pw_i2s01_clk_grp1_pad_mux[] = {
- MUX(1, 117, 3, N, N, N, N),
-};
-
-static struct atlas7_grp_mux pw_i2s01_clk_grp1_mux = {
- .pad_mux_count = ARRAY_SIZE(pw_i2s01_clk_grp1_pad_mux),
- .pad_mux_list = pw_i2s01_clk_grp1_pad_mux,
-};
-
-static struct atlas7_pad_mux pw_i2s01_clk_grp2_pad_mux[] = {
- MUX(1, 132, 2, N, N, N, N),
-};
-
-static struct atlas7_grp_mux pw_i2s01_clk_grp2_mux = {
- .pad_mux_count = ARRAY_SIZE(pw_i2s01_clk_grp2_pad_mux),
- .pad_mux_list = pw_i2s01_clk_grp2_pad_mux,
-};
-
-static struct atlas7_pad_mux pw_pwm0_grp0_pad_mux[] = {
- MUX(1, 119, 3, N, N, N, N),
-};
-
-static struct atlas7_grp_mux pw_pwm0_grp0_mux = {
- .pad_mux_count = ARRAY_SIZE(pw_pwm0_grp0_pad_mux),
- .pad_mux_list = pw_pwm0_grp0_pad_mux,
-};
-
-static struct atlas7_pad_mux pw_pwm0_grp1_pad_mux[] = {
- MUX(1, 159, 5, N, N, N, N),
-};
-
-static struct atlas7_grp_mux pw_pwm0_grp1_mux = {
- .pad_mux_count = ARRAY_SIZE(pw_pwm0_grp1_pad_mux),
- .pad_mux_list = pw_pwm0_grp1_pad_mux,
-};
-
-static struct atlas7_pad_mux pw_pwm1_grp0_pad_mux[] = {
- MUX(1, 120, 3, N, N, N, N),
-};
-
-static struct atlas7_grp_mux pw_pwm1_grp0_mux = {
- .pad_mux_count = ARRAY_SIZE(pw_pwm1_grp0_pad_mux),
- .pad_mux_list = pw_pwm1_grp0_pad_mux,
-};
-
-static struct atlas7_pad_mux pw_pwm1_grp1_pad_mux[] = {
- MUX(1, 160, 5, N, N, N, N),
-};
-
-static struct atlas7_grp_mux pw_pwm1_grp1_mux = {
- .pad_mux_count = ARRAY_SIZE(pw_pwm1_grp1_pad_mux),
- .pad_mux_list = pw_pwm1_grp1_pad_mux,
-};
-
-static struct atlas7_pad_mux pw_pwm1_grp2_pad_mux[] = {
- MUX(1, 131, 2, N, N, N, N),
-};
-
-static struct atlas7_grp_mux pw_pwm1_grp2_mux = {
- .pad_mux_count = ARRAY_SIZE(pw_pwm1_grp2_pad_mux),
- .pad_mux_list = pw_pwm1_grp2_pad_mux,
-};
-
-static struct atlas7_pad_mux pw_pwm2_grp0_pad_mux[] = {
- MUX(1, 121, 3, N, N, N, N),
-};
-
-static struct atlas7_grp_mux pw_pwm2_grp0_mux = {
- .pad_mux_count = ARRAY_SIZE(pw_pwm2_grp0_pad_mux),
- .pad_mux_list = pw_pwm2_grp0_pad_mux,
-};
-
-static struct atlas7_pad_mux pw_pwm2_grp1_pad_mux[] = {
- MUX(1, 98, 3, N, N, N, N),
-};
-
-static struct atlas7_grp_mux pw_pwm2_grp1_mux = {
- .pad_mux_count = ARRAY_SIZE(pw_pwm2_grp1_pad_mux),
- .pad_mux_list = pw_pwm2_grp1_pad_mux,
-};
-
-static struct atlas7_pad_mux pw_pwm2_grp2_pad_mux[] = {
- MUX(1, 161, 5, N, N, N, N),
-};
-
-static struct atlas7_grp_mux pw_pwm2_grp2_mux = {
- .pad_mux_count = ARRAY_SIZE(pw_pwm2_grp2_pad_mux),
- .pad_mux_list = pw_pwm2_grp2_pad_mux,
-};
-
-static struct atlas7_pad_mux pw_pwm3_grp0_pad_mux[] = {
- MUX(1, 122, 3, N, N, N, N),
-};
-
-static struct atlas7_grp_mux pw_pwm3_grp0_mux = {
- .pad_mux_count = ARRAY_SIZE(pw_pwm3_grp0_pad_mux),
- .pad_mux_list = pw_pwm3_grp0_pad_mux,
-};
-
-static struct atlas7_pad_mux pw_pwm3_grp1_pad_mux[] = {
- MUX(1, 73, 4, N, N, N, N),
-};
-
-static struct atlas7_grp_mux pw_pwm3_grp1_mux = {
- .pad_mux_count = ARRAY_SIZE(pw_pwm3_grp1_pad_mux),
- .pad_mux_list = pw_pwm3_grp1_pad_mux,
-};
-
-static struct atlas7_pad_mux pw_pwm_cpu_vol_grp0_pad_mux[] = {
- MUX(1, 121, 3, N, N, N, N),
-};
-
-static struct atlas7_grp_mux pw_pwm_cpu_vol_grp0_mux = {
- .pad_mux_count = ARRAY_SIZE(pw_pwm_cpu_vol_grp0_pad_mux),
- .pad_mux_list = pw_pwm_cpu_vol_grp0_pad_mux,
-};
-
-static struct atlas7_pad_mux pw_pwm_cpu_vol_grp1_pad_mux[] = {
- MUX(1, 98, 3, N, N, N, N),
-};
-
-static struct atlas7_grp_mux pw_pwm_cpu_vol_grp1_mux = {
- .pad_mux_count = ARRAY_SIZE(pw_pwm_cpu_vol_grp1_pad_mux),
- .pad_mux_list = pw_pwm_cpu_vol_grp1_pad_mux,
-};
-
-static struct atlas7_pad_mux pw_pwm_cpu_vol_grp2_pad_mux[] = {
- MUX(1, 161, 5, N, N, N, N),
-};
-
-static struct atlas7_grp_mux pw_pwm_cpu_vol_grp2_mux = {
- .pad_mux_count = ARRAY_SIZE(pw_pwm_cpu_vol_grp2_pad_mux),
- .pad_mux_list = pw_pwm_cpu_vol_grp2_pad_mux,
-};
-
-static struct atlas7_pad_mux pw_backlight_grp0_pad_mux[] = {
- MUX(1, 122, 3, N, N, N, N),
-};
-
-static struct atlas7_grp_mux pw_backlight_grp0_mux = {
- .pad_mux_count = ARRAY_SIZE(pw_backlight_grp0_pad_mux),
- .pad_mux_list = pw_backlight_grp0_pad_mux,
-};
-
-static struct atlas7_pad_mux pw_backlight_grp1_pad_mux[] = {
- MUX(1, 73, 4, N, N, N, N),
-};
-
-static struct atlas7_grp_mux pw_backlight_grp1_mux = {
- .pad_mux_count = ARRAY_SIZE(pw_backlight_grp1_pad_mux),
- .pad_mux_list = pw_backlight_grp1_pad_mux,
-};
-
-static struct atlas7_pad_mux rg_eth_mac_grp_pad_mux[] = {
- MUX(1, 108, 1, N, N, N, N),
- MUX(1, 103, 1, N, N, N, N),
- MUX(1, 104, 1, N, N, N, N),
- MUX(1, 105, 1, N, N, N, N),
- MUX(1, 106, 1, N, N, N, N),
- MUX(1, 107, 1, N, N, N, N),
- MUX(1, 102, 1, N, N, N, N),
- MUX(1, 97, 1, N, N, N, N),
- MUX(1, 98, 1, N, N, N, N),
- MUX(1, 99, 1, N, N, N, N),
- MUX(1, 100, 1, N, N, N, N),
- MUX(1, 101, 1, N, N, N, N),
-};
-
-static struct atlas7_grp_mux rg_eth_mac_grp_mux = {
- .pad_mux_count = ARRAY_SIZE(rg_eth_mac_grp_pad_mux),
- .pad_mux_list = rg_eth_mac_grp_pad_mux,
-};
-
-static struct atlas7_pad_mux rg_gmac_phy_intr_n_grp_pad_mux[] = {
- MUX(1, 111, 1, 0xa08, 13, 0xa88, 13),
-};
-
-static struct atlas7_grp_mux rg_gmac_phy_intr_n_grp_mux = {
- .pad_mux_count = ARRAY_SIZE(rg_gmac_phy_intr_n_grp_pad_mux),
- .pad_mux_list = rg_gmac_phy_intr_n_grp_pad_mux,
-};
-
-static struct atlas7_pad_mux rg_rgmii_mac_grp_pad_mux[] = {
- MUX(1, 109, 1, N, N, N, N),
- MUX(1, 110, 1, N, N, N, N),
-};
-
-static struct atlas7_grp_mux rg_rgmii_mac_grp_mux = {
- .pad_mux_count = ARRAY_SIZE(rg_rgmii_mac_grp_pad_mux),
- .pad_mux_list = rg_rgmii_mac_grp_pad_mux,
-};
-
-static struct atlas7_pad_mux rg_rgmii_phy_ref_clk_grp0_pad_mux[] = {
- MUX(1, 111, 5, N, N, N, N),
-};
-
-static struct atlas7_grp_mux rg_rgmii_phy_ref_clk_grp0_mux = {
- .pad_mux_count = ARRAY_SIZE(rg_rgmii_phy_ref_clk_grp0_pad_mux),
- .pad_mux_list = rg_rgmii_phy_ref_clk_grp0_pad_mux,
-};
-
-static struct atlas7_pad_mux rg_rgmii_phy_ref_clk_grp1_pad_mux[] = {
- MUX(1, 53, 4, N, N, N, N),
-};
-
-static struct atlas7_grp_mux rg_rgmii_phy_ref_clk_grp1_mux = {
- .pad_mux_count = ARRAY_SIZE(rg_rgmii_phy_ref_clk_grp1_pad_mux),
- .pad_mux_list = rg_rgmii_phy_ref_clk_grp1_pad_mux,
-};
-
-static struct atlas7_pad_mux sd0_grp_pad_mux[] = {
- MUX(1, 46, 2, N, N, N, N),
- MUX(1, 47, 2, N, N, N, N),
- MUX(1, 44, 2, N, N, N, N),
- MUX(1, 43, 2, N, N, N, N),
- MUX(1, 42, 2, N, N, N, N),
- MUX(1, 41, 2, N, N, N, N),
- MUX(1, 40, 2, N, N, N, N),
- MUX(1, 39, 2, N, N, N, N),
- MUX(1, 38, 2, N, N, N, N),
- MUX(1, 37, 2, N, N, N, N),
-};
-
-static struct atlas7_grp_mux sd0_grp_mux = {
- .pad_mux_count = ARRAY_SIZE(sd0_grp_pad_mux),
- .pad_mux_list = sd0_grp_pad_mux,
-};
-
-static struct atlas7_pad_mux sd0_4bit_grp_pad_mux[] = {
- MUX(1, 46, 2, N, N, N, N),
- MUX(1, 47, 2, N, N, N, N),
- MUX(1, 44, 2, N, N, N, N),
- MUX(1, 43, 2, N, N, N, N),
- MUX(1, 42, 2, N, N, N, N),
- MUX(1, 41, 2, N, N, N, N),
-};
-
-static struct atlas7_grp_mux sd0_4bit_grp_mux = {
- .pad_mux_count = ARRAY_SIZE(sd0_4bit_grp_pad_mux),
- .pad_mux_list = sd0_4bit_grp_pad_mux,
-};
-
-static struct atlas7_pad_mux sd1_grp_pad_mux[] = {
- MUX(1, 48, 3, N, N, N, N),
- MUX(1, 49, 3, N, N, N, N),
- MUX(1, 44, 3, 0xa00, 0, 0xa80, 0),
- MUX(1, 43, 3, 0xa00, 1, 0xa80, 1),
- MUX(1, 42, 3, 0xa00, 2, 0xa80, 2),
- MUX(1, 41, 3, 0xa00, 3, 0xa80, 3),
- MUX(1, 40, 3, N, N, N, N),
- MUX(1, 39, 3, N, N, N, N),
- MUX(1, 38, 3, N, N, N, N),
- MUX(1, 37, 3, N, N, N, N),
-};
-
-static struct atlas7_grp_mux sd1_grp_mux = {
- .pad_mux_count = ARRAY_SIZE(sd1_grp_pad_mux),
- .pad_mux_list = sd1_grp_pad_mux,
-};
-
-static struct atlas7_pad_mux sd1_4bit_grp0_pad_mux[] = {
- MUX(1, 48, 3, N, N, N, N),
- MUX(1, 49, 3, N, N, N, N),
- MUX(1, 44, 3, 0xa00, 0, 0xa80, 0),
- MUX(1, 43, 3, 0xa00, 1, 0xa80, 1),
- MUX(1, 42, 3, 0xa00, 2, 0xa80, 2),
- MUX(1, 41, 3, 0xa00, 3, 0xa80, 3),
-};
-
-static struct atlas7_grp_mux sd1_4bit_grp0_mux = {
- .pad_mux_count = ARRAY_SIZE(sd1_4bit_grp0_pad_mux),
- .pad_mux_list = sd1_4bit_grp0_pad_mux,
-};
-
-static struct atlas7_pad_mux sd1_4bit_grp1_pad_mux[] = {
- MUX(1, 48, 3, N, N, N, N),
- MUX(1, 49, 3, N, N, N, N),
- MUX(1, 40, 4, 0xa00, 0, 0xa80, 0),
- MUX(1, 39, 4, 0xa00, 1, 0xa80, 1),
- MUX(1, 38, 4, 0xa00, 2, 0xa80, 2),
- MUX(1, 37, 4, 0xa00, 3, 0xa80, 3),
-};
-
-static struct atlas7_grp_mux sd1_4bit_grp1_mux = {
- .pad_mux_count = ARRAY_SIZE(sd1_4bit_grp1_pad_mux),
- .pad_mux_list = sd1_4bit_grp1_pad_mux,
-};
-
-static struct atlas7_pad_mux sd2_basic_grp_pad_mux[] = {
- MUX(1, 31, 1, N, N, N, N),
- MUX(1, 32, 1, N, N, N, N),
- MUX(1, 33, 1, N, N, N, N),
- MUX(1, 34, 1, N, N, N, N),
- MUX(1, 35, 1, N, N, N, N),
- MUX(1, 36, 1, N, N, N, N),
-};
-
-static struct atlas7_grp_mux sd2_basic_grp_mux = {
- .pad_mux_count = ARRAY_SIZE(sd2_basic_grp_pad_mux),
- .pad_mux_list = sd2_basic_grp_pad_mux,
-};
-
-static struct atlas7_pad_mux sd2_cdb_grp0_pad_mux[] = {
- MUX(1, 124, 2, 0xa08, 7, 0xa88, 7),
-};
-
-static struct atlas7_grp_mux sd2_cdb_grp0_mux = {
- .pad_mux_count = ARRAY_SIZE(sd2_cdb_grp0_pad_mux),
- .pad_mux_list = sd2_cdb_grp0_pad_mux,
-};
-
-static struct atlas7_pad_mux sd2_cdb_grp1_pad_mux[] = {
- MUX(1, 161, 6, 0xa08, 7, 0xa88, 7),
-};
-
-static struct atlas7_grp_mux sd2_cdb_grp1_mux = {
- .pad_mux_count = ARRAY_SIZE(sd2_cdb_grp1_pad_mux),
- .pad_mux_list = sd2_cdb_grp1_pad_mux,
-};
-
-static struct atlas7_pad_mux sd2_wpb_grp0_pad_mux[] = {
- MUX(1, 123, 2, 0xa10, 6, 0xa90, 6),
-};
-
-static struct atlas7_grp_mux sd2_wpb_grp0_mux = {
- .pad_mux_count = ARRAY_SIZE(sd2_wpb_grp0_pad_mux),
- .pad_mux_list = sd2_wpb_grp0_pad_mux,
-};
-
-static struct atlas7_pad_mux sd2_wpb_grp1_pad_mux[] = {
- MUX(1, 163, 7, 0xa10, 6, 0xa90, 6),
-};
-
-static struct atlas7_grp_mux sd2_wpb_grp1_mux = {
- .pad_mux_count = ARRAY_SIZE(sd2_wpb_grp1_pad_mux),
- .pad_mux_list = sd2_wpb_grp1_pad_mux,
-};
-
-static struct atlas7_pad_mux sd3_9_grp_pad_mux[] = {
- MUX(1, 85, 1, N, N, N, N),
- MUX(1, 86, 1, N, N, N, N),
- MUX(1, 87, 1, N, N, N, N),
- MUX(1, 88, 1, N, N, N, N),
- MUX(1, 89, 1, N, N, N, N),
- MUX(1, 90, 1, N, N, N, N),
-};
-
-static struct atlas7_grp_mux sd3_9_grp_mux = {
- .pad_mux_count = ARRAY_SIZE(sd3_9_grp_pad_mux),
- .pad_mux_list = sd3_9_grp_pad_mux,
-};
-
-static struct atlas7_pad_mux sd5_grp_pad_mux[] = {
- MUX(1, 91, 1, N, N, N, N),
- MUX(1, 92, 1, N, N, N, N),
- MUX(1, 93, 1, N, N, N, N),
- MUX(1, 94, 1, N, N, N, N),
- MUX(1, 95, 1, N, N, N, N),
- MUX(1, 96, 1, N, N, N, N),
-};
-
-static struct atlas7_grp_mux sd5_grp_mux = {
- .pad_mux_count = ARRAY_SIZE(sd5_grp_pad_mux),
- .pad_mux_list = sd5_grp_pad_mux,
-};
-
-static struct atlas7_pad_mux sd6_grp0_pad_mux[] = {
- MUX(1, 79, 4, 0xa00, 27, 0xa80, 27),
- MUX(1, 78, 4, 0xa00, 26, 0xa80, 26),
- MUX(1, 74, 4, 0xa00, 28, 0xa80, 28),
- MUX(1, 75, 4, 0xa00, 29, 0xa80, 29),
- MUX(1, 76, 4, 0xa00, 30, 0xa80, 30),
- MUX(1, 77, 4, 0xa00, 31, 0xa80, 31),
-};
-
-static struct atlas7_grp_mux sd6_grp0_mux = {
- .pad_mux_count = ARRAY_SIZE(sd6_grp0_pad_mux),
- .pad_mux_list = sd6_grp0_pad_mux,
-};
-
-static struct atlas7_pad_mux sd6_grp1_pad_mux[] = {
- MUX(1, 101, 3, 0xa00, 27, 0xa80, 27),
- MUX(1, 99, 3, 0xa00, 26, 0xa80, 26),
- MUX(1, 100, 3, 0xa00, 28, 0xa80, 28),
- MUX(1, 110, 3, 0xa00, 29, 0xa80, 29),
- MUX(1, 109, 3, 0xa00, 30, 0xa80, 30),
- MUX(1, 111, 3, 0xa00, 31, 0xa80, 31),
-};
-
-static struct atlas7_grp_mux sd6_grp1_mux = {
- .pad_mux_count = ARRAY_SIZE(sd6_grp1_pad_mux),
- .pad_mux_list = sd6_grp1_pad_mux,
-};
-
-static struct atlas7_pad_mux sp0_ext_ldo_on_grp_pad_mux[] = {
- MUX(0, 4, 2, N, N, N, N),
-};
-
-static struct atlas7_grp_mux sp0_ext_ldo_on_grp_mux = {
- .pad_mux_count = ARRAY_SIZE(sp0_ext_ldo_on_grp_pad_mux),
- .pad_mux_list = sp0_ext_ldo_on_grp_pad_mux,
-};
-
-static struct atlas7_pad_mux sp0_qspi_grp_pad_mux[] = {
- MUX(0, 12, 1, N, N, N, N),
- MUX(0, 13, 1, N, N, N, N),
- MUX(0, 14, 1, N, N, N, N),
- MUX(0, 15, 1, N, N, N, N),
- MUX(0, 16, 1, N, N, N, N),
- MUX(0, 17, 1, N, N, N, N),
-};
-
-static struct atlas7_grp_mux sp0_qspi_grp_mux = {
- .pad_mux_count = ARRAY_SIZE(sp0_qspi_grp_pad_mux),
- .pad_mux_list = sp0_qspi_grp_pad_mux,
-};
-
-static struct atlas7_pad_mux sp1_spi_grp_pad_mux[] = {
- MUX(1, 19, 1, N, N, N, N),
- MUX(1, 20, 1, N, N, N, N),
- MUX(1, 21, 1, N, N, N, N),
- MUX(1, 18, 1, N, N, N, N),
-};
-
-static struct atlas7_grp_mux sp1_spi_grp_mux = {
- .pad_mux_count = ARRAY_SIZE(sp1_spi_grp_pad_mux),
- .pad_mux_list = sp1_spi_grp_pad_mux,
-};
-
-static struct atlas7_pad_mux tpiu_trace_grp_pad_mux[] = {
- MUX(1, 53, 5, N, N, N, N),
- MUX(1, 56, 5, N, N, N, N),
- MUX(1, 57, 5, N, N, N, N),
- MUX(1, 58, 5, N, N, N, N),
- MUX(1, 59, 5, N, N, N, N),
- MUX(1, 60, 5, N, N, N, N),
- MUX(1, 61, 5, N, N, N, N),
- MUX(1, 62, 5, N, N, N, N),
- MUX(1, 63, 5, N, N, N, N),
- MUX(1, 64, 5, N, N, N, N),
- MUX(1, 65, 5, N, N, N, N),
- MUX(1, 66, 5, N, N, N, N),
- MUX(1, 67, 5, N, N, N, N),
- MUX(1, 68, 5, N, N, N, N),
- MUX(1, 69, 5, N, N, N, N),
- MUX(1, 70, 5, N, N, N, N),
- MUX(1, 71, 5, N, N, N, N),
- MUX(1, 72, 5, N, N, N, N),
-};
-
-static struct atlas7_grp_mux tpiu_trace_grp_mux = {
- .pad_mux_count = ARRAY_SIZE(tpiu_trace_grp_pad_mux),
- .pad_mux_list = tpiu_trace_grp_pad_mux,
-};
-
-static struct atlas7_pad_mux uart0_grp_pad_mux[] = {
- MUX(1, 121, 4, N, N, N, N),
- MUX(1, 120, 4, N, N, N, N),
- MUX(1, 134, 1, N, N, N, N),
- MUX(1, 133, 1, N, N, N, N),
-};
-
-static struct atlas7_grp_mux uart0_grp_mux = {
- .pad_mux_count = ARRAY_SIZE(uart0_grp_pad_mux),
- .pad_mux_list = uart0_grp_pad_mux,
-};
-
-static struct atlas7_pad_mux uart0_nopause_grp_pad_mux[] = {
- MUX(1, 134, 1, N, N, N, N),
- MUX(1, 133, 1, N, N, N, N),
-};
-
-static struct atlas7_grp_mux uart0_nopause_grp_mux = {
- .pad_mux_count = ARRAY_SIZE(uart0_nopause_grp_pad_mux),
- .pad_mux_list = uart0_nopause_grp_pad_mux,
-};
-
-static struct atlas7_pad_mux uart1_grp_pad_mux[] = {
- MUX(1, 136, 1, N, N, N, N),
- MUX(1, 135, 1, N, N, N, N),
-};
-
-static struct atlas7_grp_mux uart1_grp_mux = {
- .pad_mux_count = ARRAY_SIZE(uart1_grp_pad_mux),
- .pad_mux_list = uart1_grp_pad_mux,
-};
-
-static struct atlas7_pad_mux uart2_cts_grp0_pad_mux[] = {
- MUX(1, 132, 3, 0xa10, 2, 0xa90, 2),
-};
-
-static struct atlas7_grp_mux uart2_cts_grp0_mux = {
- .pad_mux_count = ARRAY_SIZE(uart2_cts_grp0_pad_mux),
- .pad_mux_list = uart2_cts_grp0_pad_mux,
-};
-
-static struct atlas7_pad_mux uart2_cts_grp1_pad_mux[] = {
- MUX(1, 162, 2, 0xa10, 2, 0xa90, 2),
-};
-
-static struct atlas7_grp_mux uart2_cts_grp1_mux = {
- .pad_mux_count = ARRAY_SIZE(uart2_cts_grp1_pad_mux),
- .pad_mux_list = uart2_cts_grp1_pad_mux,
-};
-
-static struct atlas7_pad_mux uart2_rts_grp0_pad_mux[] = {
- MUX(1, 131, 3, N, N, N, N),
-};
-
-static struct atlas7_grp_mux uart2_rts_grp0_mux = {
- .pad_mux_count = ARRAY_SIZE(uart2_rts_grp0_pad_mux),
- .pad_mux_list = uart2_rts_grp0_pad_mux,
-};
-
-static struct atlas7_pad_mux uart2_rts_grp1_pad_mux[] = {
- MUX(1, 161, 2, N, N, N, N),
-};
-
-static struct atlas7_grp_mux uart2_rts_grp1_mux = {
- .pad_mux_count = ARRAY_SIZE(uart2_rts_grp1_pad_mux),
- .pad_mux_list = uart2_rts_grp1_pad_mux,
-};
-
-static struct atlas7_pad_mux uart2_rxd_grp0_pad_mux[] = {
- MUX(0, 11, 2, 0xa10, 5, 0xa90, 5),
-};
-
-static struct atlas7_grp_mux uart2_rxd_grp0_mux = {
- .pad_mux_count = ARRAY_SIZE(uart2_rxd_grp0_pad_mux),
- .pad_mux_list = uart2_rxd_grp0_pad_mux,
-};
-
-static struct atlas7_pad_mux uart2_rxd_grp1_pad_mux[] = {
- MUX(1, 160, 2, 0xa10, 5, 0xa90, 5),
-};
-
-static struct atlas7_grp_mux uart2_rxd_grp1_mux = {
- .pad_mux_count = ARRAY_SIZE(uart2_rxd_grp1_pad_mux),
- .pad_mux_list = uart2_rxd_grp1_pad_mux,
-};
-
-static struct atlas7_pad_mux uart2_rxd_grp2_pad_mux[] = {
- MUX(1, 130, 3, 0xa10, 5, 0xa90, 5),
-};
-
-static struct atlas7_grp_mux uart2_rxd_grp2_mux = {
- .pad_mux_count = ARRAY_SIZE(uart2_rxd_grp2_pad_mux),
- .pad_mux_list = uart2_rxd_grp2_pad_mux,
-};
-
-static struct atlas7_pad_mux uart2_txd_grp0_pad_mux[] = {
- MUX(0, 10, 2, N, N, N, N),
-};
-
-static struct atlas7_grp_mux uart2_txd_grp0_mux = {
- .pad_mux_count = ARRAY_SIZE(uart2_txd_grp0_pad_mux),
- .pad_mux_list = uart2_txd_grp0_pad_mux,
-};
-
-static struct atlas7_pad_mux uart2_txd_grp1_pad_mux[] = {
- MUX(1, 159, 2, N, N, N, N),
-};
-
-static struct atlas7_grp_mux uart2_txd_grp1_mux = {
- .pad_mux_count = ARRAY_SIZE(uart2_txd_grp1_pad_mux),
- .pad_mux_list = uart2_txd_grp1_pad_mux,
-};
-
-static struct atlas7_pad_mux uart2_txd_grp2_pad_mux[] = {
- MUX(1, 129, 3, N, N, N, N),
-};
-
-static struct atlas7_grp_mux uart2_txd_grp2_mux = {
- .pad_mux_count = ARRAY_SIZE(uart2_txd_grp2_pad_mux),
- .pad_mux_list = uart2_txd_grp2_pad_mux,
-};
-
-static struct atlas7_pad_mux uart3_cts_grp0_pad_mux[] = {
- MUX(1, 125, 2, 0xa08, 0, 0xa88, 0),
-};
-
-static struct atlas7_grp_mux uart3_cts_grp0_mux = {
- .pad_mux_count = ARRAY_SIZE(uart3_cts_grp0_pad_mux),
- .pad_mux_list = uart3_cts_grp0_pad_mux,
-};
-
-static struct atlas7_pad_mux uart3_cts_grp1_pad_mux[] = {
- MUX(1, 111, 4, 0xa08, 0, 0xa88, 0),
-};
-
-static struct atlas7_grp_mux uart3_cts_grp1_mux = {
- .pad_mux_count = ARRAY_SIZE(uart3_cts_grp1_pad_mux),
- .pad_mux_list = uart3_cts_grp1_pad_mux,
-};
-
-static struct atlas7_pad_mux uart3_cts_grp2_pad_mux[] = {
- MUX(1, 140, 2, 0xa08, 0, 0xa88, 0),
-};
-
-static struct atlas7_grp_mux uart3_cts_grp2_mux = {
- .pad_mux_count = ARRAY_SIZE(uart3_cts_grp2_pad_mux),
- .pad_mux_list = uart3_cts_grp2_pad_mux,
-};
-
-static struct atlas7_pad_mux uart3_rts_grp0_pad_mux[] = {
- MUX(1, 126, 2, N, N, N, N),
-};
-
-static struct atlas7_grp_mux uart3_rts_grp0_mux = {
- .pad_mux_count = ARRAY_SIZE(uart3_rts_grp0_pad_mux),
- .pad_mux_list = uart3_rts_grp0_pad_mux,
-};
-
-static struct atlas7_pad_mux uart3_rts_grp1_pad_mux[] = {
- MUX(1, 109, 4, N, N, N, N),
-};
-
-static struct atlas7_grp_mux uart3_rts_grp1_mux = {
- .pad_mux_count = ARRAY_SIZE(uart3_rts_grp1_pad_mux),
- .pad_mux_list = uart3_rts_grp1_pad_mux,
-};
-
-static struct atlas7_pad_mux uart3_rts_grp2_pad_mux[] = {
- MUX(1, 139, 2, N, N, N, N),
-};
-
-static struct atlas7_grp_mux uart3_rts_grp2_mux = {
- .pad_mux_count = ARRAY_SIZE(uart3_rts_grp2_pad_mux),
- .pad_mux_list = uart3_rts_grp2_pad_mux,
-};
-
-static struct atlas7_pad_mux uart3_rxd_grp0_pad_mux[] = {
- MUX(1, 138, 1, 0xa00, 5, 0xa80, 5),
-};
-
-static struct atlas7_grp_mux uart3_rxd_grp0_mux = {
- .pad_mux_count = ARRAY_SIZE(uart3_rxd_grp0_pad_mux),
- .pad_mux_list = uart3_rxd_grp0_pad_mux,
-};
-
-static struct atlas7_pad_mux uart3_rxd_grp1_pad_mux[] = {
- MUX(1, 84, 2, 0xa00, 5, 0xa80, 5),
-};
-
-static struct atlas7_grp_mux uart3_rxd_grp1_mux = {
- .pad_mux_count = ARRAY_SIZE(uart3_rxd_grp1_pad_mux),
- .pad_mux_list = uart3_rxd_grp1_pad_mux,
-};
-
-static struct atlas7_pad_mux uart3_rxd_grp2_pad_mux[] = {
- MUX(1, 162, 3, 0xa00, 5, 0xa80, 5),
-};
-
-static struct atlas7_grp_mux uart3_rxd_grp2_mux = {
- .pad_mux_count = ARRAY_SIZE(uart3_rxd_grp2_pad_mux),
- .pad_mux_list = uart3_rxd_grp2_pad_mux,
-};
-
-static struct atlas7_pad_mux uart3_txd_grp0_pad_mux[] = {
- MUX(1, 137, 1, N, N, N, N),
-};
-
-static struct atlas7_grp_mux uart3_txd_grp0_mux = {
- .pad_mux_count = ARRAY_SIZE(uart3_txd_grp0_pad_mux),
- .pad_mux_list = uart3_txd_grp0_pad_mux,
-};
-
-static struct atlas7_pad_mux uart3_txd_grp1_pad_mux[] = {
- MUX(1, 83, 2, N, N, N, N),
-};
-
-static struct atlas7_grp_mux uart3_txd_grp1_mux = {
- .pad_mux_count = ARRAY_SIZE(uart3_txd_grp1_pad_mux),
- .pad_mux_list = uart3_txd_grp1_pad_mux,
-};
-
-static struct atlas7_pad_mux uart3_txd_grp2_pad_mux[] = {
- MUX(1, 161, 3, N, N, N, N),
-};
-
-static struct atlas7_grp_mux uart3_txd_grp2_mux = {
- .pad_mux_count = ARRAY_SIZE(uart3_txd_grp2_pad_mux),
- .pad_mux_list = uart3_txd_grp2_pad_mux,
-};
-
-static struct atlas7_pad_mux uart4_basic_grp_pad_mux[] = {
- MUX(1, 140, 1, N, N, N, N),
- MUX(1, 139, 1, N, N, N, N),
-};
-
-static struct atlas7_grp_mux uart4_basic_grp_mux = {
- .pad_mux_count = ARRAY_SIZE(uart4_basic_grp_pad_mux),
- .pad_mux_list = uart4_basic_grp_pad_mux,
-};
-
-static struct atlas7_pad_mux uart4_cts_grp0_pad_mux[] = {
- MUX(1, 122, 4, 0xa08, 1, 0xa88, 1),
-};
-
-static struct atlas7_grp_mux uart4_cts_grp0_mux = {
- .pad_mux_count = ARRAY_SIZE(uart4_cts_grp0_pad_mux),
- .pad_mux_list = uart4_cts_grp0_pad_mux,
-};
-
-static struct atlas7_pad_mux uart4_cts_grp1_pad_mux[] = {
- MUX(1, 100, 4, 0xa08, 1, 0xa88, 1),
-};
-
-static struct atlas7_grp_mux uart4_cts_grp1_mux = {
- .pad_mux_count = ARRAY_SIZE(uart4_cts_grp1_pad_mux),
- .pad_mux_list = uart4_cts_grp1_pad_mux,
-};
-
-static struct atlas7_pad_mux uart4_cts_grp2_pad_mux[] = {
- MUX(1, 117, 2, 0xa08, 1, 0xa88, 1),
-};
-
-static struct atlas7_grp_mux uart4_cts_grp2_mux = {
- .pad_mux_count = ARRAY_SIZE(uart4_cts_grp2_pad_mux),
- .pad_mux_list = uart4_cts_grp2_pad_mux,
-};
-
-static struct atlas7_pad_mux uart4_rts_grp0_pad_mux[] = {
- MUX(1, 123, 4, N, N, N, N),
-};
-
-static struct atlas7_grp_mux uart4_rts_grp0_mux = {
- .pad_mux_count = ARRAY_SIZE(uart4_rts_grp0_pad_mux),
- .pad_mux_list = uart4_rts_grp0_pad_mux,
-};
-
-static struct atlas7_pad_mux uart4_rts_grp1_pad_mux[] = {
- MUX(1, 99, 4, N, N, N, N),
-};
-
-static struct atlas7_grp_mux uart4_rts_grp1_mux = {
- .pad_mux_count = ARRAY_SIZE(uart4_rts_grp1_pad_mux),
- .pad_mux_list = uart4_rts_grp1_pad_mux,
-};
-
-static struct atlas7_pad_mux uart4_rts_grp2_pad_mux[] = {
- MUX(1, 116, 2, N, N, N, N),
-};
-
-static struct atlas7_grp_mux uart4_rts_grp2_mux = {
- .pad_mux_count = ARRAY_SIZE(uart4_rts_grp2_pad_mux),
- .pad_mux_list = uart4_rts_grp2_pad_mux,
-};
-
-static struct atlas7_pad_mux usb0_drvvbus_grp0_pad_mux[] = {
- MUX(1, 51, 2, N, N, N, N),
-};
-
-static struct atlas7_grp_mux usb0_drvvbus_grp0_mux = {
- .pad_mux_count = ARRAY_SIZE(usb0_drvvbus_grp0_pad_mux),
- .pad_mux_list = usb0_drvvbus_grp0_pad_mux,
-};
-
-static struct atlas7_pad_mux usb0_drvvbus_grp1_pad_mux[] = {
- MUX(1, 162, 7, N, N, N, N),
-};
-
-static struct atlas7_grp_mux usb0_drvvbus_grp1_mux = {
- .pad_mux_count = ARRAY_SIZE(usb0_drvvbus_grp1_pad_mux),
- .pad_mux_list = usb0_drvvbus_grp1_pad_mux,
-};
-
-static struct atlas7_pad_mux usb1_drvvbus_grp0_pad_mux[] = {
- MUX(1, 134, 2, N, N, N, N),
-};
-
-static struct atlas7_grp_mux usb1_drvvbus_grp0_mux = {
- .pad_mux_count = ARRAY_SIZE(usb1_drvvbus_grp0_pad_mux),
- .pad_mux_list = usb1_drvvbus_grp0_pad_mux,
-};
-
-static struct atlas7_pad_mux usb1_drvvbus_grp1_pad_mux[] = {
- MUX(1, 163, 2, N, N, N, N),
-};
-
-static struct atlas7_grp_mux usb1_drvvbus_grp1_mux = {
- .pad_mux_count = ARRAY_SIZE(usb1_drvvbus_grp1_pad_mux),
- .pad_mux_list = usb1_drvvbus_grp1_pad_mux,
-};
-
-static struct atlas7_pad_mux visbus_dout_grp_pad_mux[] = {
- MUX(1, 57, 6, N, N, N, N),
- MUX(1, 58, 6, N, N, N, N),
- MUX(1, 59, 6, N, N, N, N),
- MUX(1, 60, 6, N, N, N, N),
- MUX(1, 61, 6, N, N, N, N),
- MUX(1, 62, 6, N, N, N, N),
- MUX(1, 63, 6, N, N, N, N),
- MUX(1, 64, 6, N, N, N, N),
- MUX(1, 65, 6, N, N, N, N),
- MUX(1, 66, 6, N, N, N, N),
- MUX(1, 67, 6, N, N, N, N),
- MUX(1, 68, 6, N, N, N, N),
- MUX(1, 69, 6, N, N, N, N),
- MUX(1, 70, 6, N, N, N, N),
- MUX(1, 71, 6, N, N, N, N),
- MUX(1, 72, 6, N, N, N, N),
- MUX(1, 53, 6, N, N, N, N),
- MUX(1, 54, 6, N, N, N, N),
- MUX(1, 55, 6, N, N, N, N),
- MUX(1, 56, 6, N, N, N, N),
- MUX(1, 85, 6, N, N, N, N),
- MUX(1, 86, 6, N, N, N, N),
- MUX(1, 87, 6, N, N, N, N),
- MUX(1, 88, 6, N, N, N, N),
- MUX(1, 89, 6, N, N, N, N),
- MUX(1, 90, 6, N, N, N, N),
- MUX(1, 91, 6, N, N, N, N),
- MUX(1, 92, 6, N, N, N, N),
- MUX(1, 93, 6, N, N, N, N),
- MUX(1, 94, 6, N, N, N, N),
- MUX(1, 95, 6, N, N, N, N),
- MUX(1, 96, 6, N, N, N, N),
-};
-
-static struct atlas7_grp_mux visbus_dout_grp_mux = {
- .pad_mux_count = ARRAY_SIZE(visbus_dout_grp_pad_mux),
- .pad_mux_list = visbus_dout_grp_pad_mux,
-};
-
-static struct atlas7_pad_mux vi_vip1_grp_pad_mux[] = {
- MUX(1, 74, 1, N, N, N, N),
- MUX(1, 75, 1, N, N, N, N),
- MUX(1, 76, 1, N, N, N, N),
- MUX(1, 77, 1, N, N, N, N),
- MUX(1, 78, 1, N, N, N, N),
- MUX(1, 79, 1, N, N, N, N),
- MUX(1, 80, 1, N, N, N, N),
- MUX(1, 81, 1, N, N, N, N),
- MUX(1, 82, 1, N, N, N, N),
- MUX(1, 83, 1, N, N, N, N),
- MUX(1, 84, 1, N, N, N, N),
- MUX(1, 103, 2, N, N, N, N),
- MUX(1, 104, 2, N, N, N, N),
- MUX(1, 105, 2, N, N, N, N),
- MUX(1, 106, 2, N, N, N, N),
- MUX(1, 107, 2, N, N, N, N),
- MUX(1, 102, 2, N, N, N, N),
- MUX(1, 97, 2, N, N, N, N),
- MUX(1, 98, 2, N, N, N, N),
-};
-
-static struct atlas7_grp_mux vi_vip1_grp_mux = {
- .pad_mux_count = ARRAY_SIZE(vi_vip1_grp_pad_mux),
- .pad_mux_list = vi_vip1_grp_pad_mux,
-};
-
-static struct atlas7_pad_mux vi_vip1_ext_grp_pad_mux[] = {
- MUX(1, 74, 1, N, N, N, N),
- MUX(1, 75, 1, N, N, N, N),
- MUX(1, 76, 1, N, N, N, N),
- MUX(1, 77, 1, N, N, N, N),
- MUX(1, 78, 1, N, N, N, N),
- MUX(1, 79, 1, N, N, N, N),
- MUX(1, 80, 1, N, N, N, N),
- MUX(1, 81, 1, N, N, N, N),
- MUX(1, 82, 1, N, N, N, N),
- MUX(1, 83, 1, N, N, N, N),
- MUX(1, 84, 1, N, N, N, N),
- MUX(1, 108, 2, N, N, N, N),
- MUX(1, 103, 2, N, N, N, N),
- MUX(1, 104, 2, N, N, N, N),
- MUX(1, 105, 2, N, N, N, N),
- MUX(1, 106, 2, N, N, N, N),
- MUX(1, 107, 2, N, N, N, N),
- MUX(1, 102, 2, N, N, N, N),
- MUX(1, 97, 2, N, N, N, N),
- MUX(1, 98, 2, N, N, N, N),
- MUX(1, 99, 2, N, N, N, N),
- MUX(1, 100, 2, N, N, N, N),
-};
-
-static struct atlas7_grp_mux vi_vip1_ext_grp_mux = {
- .pad_mux_count = ARRAY_SIZE(vi_vip1_ext_grp_pad_mux),
- .pad_mux_list = vi_vip1_ext_grp_pad_mux,
-};
-
-static struct atlas7_pad_mux vi_vip1_low8bit_grp_pad_mux[] = {
- MUX(1, 74, 1, N, N, N, N),
- MUX(1, 75, 1, N, N, N, N),
- MUX(1, 76, 1, N, N, N, N),
- MUX(1, 77, 1, N, N, N, N),
- MUX(1, 78, 1, N, N, N, N),
- MUX(1, 79, 1, N, N, N, N),
- MUX(1, 80, 1, N, N, N, N),
- MUX(1, 81, 1, N, N, N, N),
- MUX(1, 82, 1, N, N, N, N),
- MUX(1, 83, 1, N, N, N, N),
- MUX(1, 84, 1, N, N, N, N),
-};
-
-static struct atlas7_grp_mux vi_vip1_low8bit_grp_mux = {
- .pad_mux_count = ARRAY_SIZE(vi_vip1_low8bit_grp_pad_mux),
- .pad_mux_list = vi_vip1_low8bit_grp_pad_mux,
-};
-
-static struct atlas7_pad_mux vi_vip1_high8bit_grp_pad_mux[] = {
- MUX(1, 82, 1, N, N, N, N),
- MUX(1, 83, 1, N, N, N, N),
- MUX(1, 84, 1, N, N, N, N),
- MUX(1, 103, 2, N, N, N, N),
- MUX(1, 104, 2, N, N, N, N),
- MUX(1, 105, 2, N, N, N, N),
- MUX(1, 106, 2, N, N, N, N),
- MUX(1, 107, 2, N, N, N, N),
- MUX(1, 102, 2, N, N, N, N),
- MUX(1, 97, 2, N, N, N, N),
- MUX(1, 98, 2, N, N, N, N),
-};
-
-static struct atlas7_grp_mux vi_vip1_high8bit_grp_mux = {
- .pad_mux_count = ARRAY_SIZE(vi_vip1_high8bit_grp_pad_mux),
- .pad_mux_list = vi_vip1_high8bit_grp_pad_mux,
-};
-
-static struct atlas7_pmx_func atlas7_pmx_functions[] = {
- FUNCTION("gnss_gpio", gnss_gpio_grp, &gnss_gpio_grp_mux),
- FUNCTION("lcd_vip_gpio", lcd_vip_gpio_grp, &lcd_vip_gpio_grp_mux),
- FUNCTION("sdio_i2s_gpio", sdio_i2s_gpio_grp, &sdio_i2s_gpio_grp_mux),
- FUNCTION("sp_rgmii_gpio", sp_rgmii_gpio_grp, &sp_rgmii_gpio_grp_mux),
- FUNCTION("lvds_gpio", lvds_gpio_grp, &lvds_gpio_grp_mux),
- FUNCTION("jtag_uart_nand_gpio",
- jtag_uart_nand_gpio_grp,
- &jtag_uart_nand_gpio_grp_mux),
- FUNCTION("rtc_gpio", rtc_gpio_grp, &rtc_gpio_grp_mux),
- FUNCTION("audio_ac97", audio_ac97_grp, &audio_ac97_grp_mux),
- FUNCTION("audio_digmic_m0",
- audio_digmic_grp0,
- &audio_digmic_grp0_mux),
- FUNCTION("audio_digmic_m1",
- audio_digmic_grp1,
- &audio_digmic_grp1_mux),
- FUNCTION("audio_digmic_m2",
- audio_digmic_grp2,
- &audio_digmic_grp2_mux),
- FUNCTION("audio_func_dbg",
- audio_func_dbg_grp,
- &audio_func_dbg_grp_mux),
- FUNCTION("audio_i2s", audio_i2s_grp, &audio_i2s_grp_mux),
- FUNCTION("audio_i2s_2ch", audio_i2s_2ch_grp, &audio_i2s_2ch_grp_mux),
- FUNCTION("audio_i2s_extclk",
- audio_i2s_extclk_grp,
- &audio_i2s_extclk_grp_mux),
- FUNCTION("audio_spdif_out_m0",
- audio_spdif_out_grp0,
- &audio_spdif_out_grp0_mux),
- FUNCTION("audio_spdif_out_m1",
- audio_spdif_out_grp1,
- &audio_spdif_out_grp1_mux),
- FUNCTION("audio_spdif_out_m2",
- audio_spdif_out_grp2,
- &audio_spdif_out_grp2_mux),
- FUNCTION("audio_uart0_basic",
- audio_uart0_basic_grp,
- &audio_uart0_basic_grp_mux),
- FUNCTION("audio_uart0_urfs_m0",
- audio_uart0_urfs_grp0,
- &audio_uart0_urfs_grp0_mux),
- FUNCTION("audio_uart0_urfs_m1",
- audio_uart0_urfs_grp1,
- &audio_uart0_urfs_grp1_mux),
- FUNCTION("audio_uart0_urfs_m2",
- audio_uart0_urfs_grp2,
- &audio_uart0_urfs_grp2_mux),
- FUNCTION("audio_uart0_urfs_m3",
- audio_uart0_urfs_grp3,
- &audio_uart0_urfs_grp3_mux),
- FUNCTION("audio_uart1_basic",
- audio_uart1_basic_grp,
- &audio_uart1_basic_grp_mux),
- FUNCTION("audio_uart1_urfs_m0",
- audio_uart1_urfs_grp0,
- &audio_uart1_urfs_grp0_mux),
- FUNCTION("audio_uart1_urfs_m1",
- audio_uart1_urfs_grp1,
- &audio_uart1_urfs_grp1_mux),
- FUNCTION("audio_uart1_urfs_m2",
- audio_uart1_urfs_grp2,
- &audio_uart1_urfs_grp2_mux),
- FUNCTION("audio_uart2_urfs_m0",
- audio_uart2_urfs_grp0,
- &audio_uart2_urfs_grp0_mux),
- FUNCTION("audio_uart2_urfs_m1",
- audio_uart2_urfs_grp1,
- &audio_uart2_urfs_grp1_mux),
- FUNCTION("audio_uart2_urfs_m2",
- audio_uart2_urfs_grp2,
- &audio_uart2_urfs_grp2_mux),
- FUNCTION("audio_uart2_urxd_m0",
- audio_uart2_urxd_grp0,
- &audio_uart2_urxd_grp0_mux),
- FUNCTION("audio_uart2_urxd_m1",
- audio_uart2_urxd_grp1,
- &audio_uart2_urxd_grp1_mux),
- FUNCTION("audio_uart2_urxd_m2",
- audio_uart2_urxd_grp2,
- &audio_uart2_urxd_grp2_mux),
- FUNCTION("audio_uart2_usclk_m0",
- audio_uart2_usclk_grp0,
- &audio_uart2_usclk_grp0_mux),
- FUNCTION("audio_uart2_usclk_m1",
- audio_uart2_usclk_grp1,
- &audio_uart2_usclk_grp1_mux),
- FUNCTION("audio_uart2_usclk_m2",
- audio_uart2_usclk_grp2,
- &audio_uart2_usclk_grp2_mux),
- FUNCTION("audio_uart2_utfs_m0",
- audio_uart2_utfs_grp0,
- &audio_uart2_utfs_grp0_mux),
- FUNCTION("audio_uart2_utfs_m1",
- audio_uart2_utfs_grp1,
- &audio_uart2_utfs_grp1_mux),
- FUNCTION("audio_uart2_utfs_m2",
- audio_uart2_utfs_grp2,
- &audio_uart2_utfs_grp2_mux),
- FUNCTION("audio_uart2_utxd_m0",
- audio_uart2_utxd_grp0,
- &audio_uart2_utxd_grp0_mux),
- FUNCTION("audio_uart2_utxd_m1",
- audio_uart2_utxd_grp1,
- &audio_uart2_utxd_grp1_mux),
- FUNCTION("audio_uart2_utxd_m2",
- audio_uart2_utxd_grp2,
- &audio_uart2_utxd_grp2_mux),
- FUNCTION("c_can_trnsvr_en_m0",
- c_can_trnsvr_en_grp0,
- &c_can_trnsvr_en_grp0_mux),
- FUNCTION("c_can_trnsvr_en_m1",
- c_can_trnsvr_en_grp1,
- &c_can_trnsvr_en_grp1_mux),
- FUNCTION("c_can_trnsvr_intr",
- c_can_trnsvr_intr_grp,
- &c_can_trnsvr_intr_grp_mux),
- FUNCTION("c_can_trnsvr_stb_n",
- c_can_trnsvr_stb_n_grp,
- &c_can_trnsvr_stb_n_grp_mux),
- FUNCTION("c0_can_rxd_trnsv0",
- c0_can_rxd_trnsv0_grp,
- &c0_can_rxd_trnsv0_grp_mux),
- FUNCTION("c0_can_rxd_trnsv1",
- c0_can_rxd_trnsv1_grp,
- &c0_can_rxd_trnsv1_grp_mux),
- FUNCTION("c0_can_txd_trnsv0",
- c0_can_txd_trnsv0_grp,
- &c0_can_txd_trnsv0_grp_mux),
- FUNCTION("c0_can_txd_trnsv1",
- c0_can_txd_trnsv1_grp,
- &c0_can_txd_trnsv1_grp_mux),
- FUNCTION("c1_can_rxd_m0", c1_can_rxd_grp0, &c1_can_rxd_grp0_mux),
- FUNCTION("c1_can_rxd_m1", c1_can_rxd_grp1, &c1_can_rxd_grp1_mux),
- FUNCTION("c1_can_rxd_m2", c1_can_rxd_grp2, &c1_can_rxd_grp2_mux),
- FUNCTION("c1_can_rxd_m3", c1_can_rxd_grp3, &c1_can_rxd_grp3_mux),
- FUNCTION("c1_can_txd_m0", c1_can_txd_grp0, &c1_can_txd_grp0_mux),
- FUNCTION("c1_can_txd_m1", c1_can_txd_grp1, &c1_can_txd_grp1_mux),
- FUNCTION("c1_can_txd_m2", c1_can_txd_grp2, &c1_can_txd_grp2_mux),
- FUNCTION("c1_can_txd_m3", c1_can_txd_grp3, &c1_can_txd_grp3_mux),
- FUNCTION("ca_audio_lpc", ca_audio_lpc_grp, &ca_audio_lpc_grp_mux),
- FUNCTION("ca_bt_lpc", ca_bt_lpc_grp, &ca_bt_lpc_grp_mux),
- FUNCTION("ca_coex", ca_coex_grp, &ca_coex_grp_mux),
- FUNCTION("ca_curator_lpc",
- ca_curator_lpc_grp,
- &ca_curator_lpc_grp_mux),
- FUNCTION("ca_pcm_debug", ca_pcm_debug_grp, &ca_pcm_debug_grp_mux),
- FUNCTION("ca_pio", ca_pio_grp, &ca_pio_grp_mux),
- FUNCTION("ca_sdio_debug", ca_sdio_debug_grp, &ca_sdio_debug_grp_mux),
- FUNCTION("ca_spi", ca_spi_grp, &ca_spi_grp_mux),
- FUNCTION("ca_trb", ca_trb_grp, &ca_trb_grp_mux),
- FUNCTION("ca_uart_debug", ca_uart_debug_grp, &ca_uart_debug_grp_mux),
- FUNCTION("clkc_m0", clkc_grp0, &clkc_grp0_mux),
- FUNCTION("clkc_m1", clkc_grp1, &clkc_grp1_mux),
- FUNCTION("gn_gnss_i2c", gn_gnss_i2c_grp, &gn_gnss_i2c_grp_mux),
- FUNCTION("gn_gnss_uart_nopause",
- gn_gnss_uart_nopause_grp,
- &gn_gnss_uart_nopause_grp_mux),
- FUNCTION("gn_gnss_uart", gn_gnss_uart_grp, &gn_gnss_uart_grp_mux),
- FUNCTION("gn_trg_spi_m0", gn_trg_spi_grp0, &gn_trg_spi_grp0_mux),
- FUNCTION("gn_trg_spi_m1", gn_trg_spi_grp1, &gn_trg_spi_grp1_mux),
- FUNCTION("cvbs_dbg", cvbs_dbg_grp, &cvbs_dbg_grp_mux),
- FUNCTION("cvbs_dbg_test_m0",
- cvbs_dbg_test_grp0,
- &cvbs_dbg_test_grp0_mux),
- FUNCTION("cvbs_dbg_test_m1",
- cvbs_dbg_test_grp1,
- &cvbs_dbg_test_grp1_mux),
- FUNCTION("cvbs_dbg_test_m2",
- cvbs_dbg_test_grp2,
- &cvbs_dbg_test_grp2_mux),
- FUNCTION("cvbs_dbg_test_m3",
- cvbs_dbg_test_grp3,
- &cvbs_dbg_test_grp3_mux),
- FUNCTION("cvbs_dbg_test_m4",
- cvbs_dbg_test_grp4,
- &cvbs_dbg_test_grp4_mux),
- FUNCTION("cvbs_dbg_test_m5",
- cvbs_dbg_test_grp5,
- &cvbs_dbg_test_grp5_mux),
- FUNCTION("cvbs_dbg_test_m6",
- cvbs_dbg_test_grp6,
- &cvbs_dbg_test_grp6_mux),
- FUNCTION("cvbs_dbg_test_m7",
- cvbs_dbg_test_grp7,
- &cvbs_dbg_test_grp7_mux),
- FUNCTION("cvbs_dbg_test_m8",
- cvbs_dbg_test_grp8,
- &cvbs_dbg_test_grp8_mux),
- FUNCTION("cvbs_dbg_test_m9",
- cvbs_dbg_test_grp9,
- &cvbs_dbg_test_grp9_mux),
- FUNCTION("cvbs_dbg_test_m10",
- cvbs_dbg_test_grp10,
- &cvbs_dbg_test_grp10_mux),
- FUNCTION("cvbs_dbg_test_m11",
- cvbs_dbg_test_grp11,
- &cvbs_dbg_test_grp11_mux),
- FUNCTION("cvbs_dbg_test_m12",
- cvbs_dbg_test_grp12,
- &cvbs_dbg_test_grp12_mux),
- FUNCTION("cvbs_dbg_test_m13",
- cvbs_dbg_test_grp13,
- &cvbs_dbg_test_grp13_mux),
- FUNCTION("cvbs_dbg_test_m14",
- cvbs_dbg_test_grp14,
- &cvbs_dbg_test_grp14_mux),
- FUNCTION("cvbs_dbg_test_m15",
- cvbs_dbg_test_grp15,
- &cvbs_dbg_test_grp15_mux),
- FUNCTION("gn_gnss_power", gn_gnss_power_grp, &gn_gnss_power_grp_mux),
- FUNCTION("gn_gnss_sw_status",
- gn_gnss_sw_status_grp,
- &gn_gnss_sw_status_grp_mux),
- FUNCTION("gn_gnss_eclk", gn_gnss_eclk_grp, &gn_gnss_eclk_grp_mux),
- FUNCTION("gn_gnss_irq1_m0",
- gn_gnss_irq1_grp0,
- &gn_gnss_irq1_grp0_mux),
- FUNCTION("gn_gnss_irq2_m0",
- gn_gnss_irq2_grp0,
- &gn_gnss_irq2_grp0_mux),
- FUNCTION("gn_gnss_tm", gn_gnss_tm_grp, &gn_gnss_tm_grp_mux),
- FUNCTION("gn_gnss_tsync", gn_gnss_tsync_grp, &gn_gnss_tsync_grp_mux),
- FUNCTION("gn_io_gnsssys_sw_cfg",
- gn_io_gnsssys_sw_cfg_grp,
- &gn_io_gnsssys_sw_cfg_grp_mux),
- FUNCTION("gn_trg_m0", gn_trg_grp0, &gn_trg_grp0_mux),
- FUNCTION("gn_trg_m1", gn_trg_grp1, &gn_trg_grp1_mux),
- FUNCTION("gn_trg_shutdown_m0",
- gn_trg_shutdown_grp0,
- &gn_trg_shutdown_grp0_mux),
- FUNCTION("gn_trg_shutdown_m1",
- gn_trg_shutdown_grp1,
- &gn_trg_shutdown_grp1_mux),
- FUNCTION("gn_trg_shutdown_m2",
- gn_trg_shutdown_grp2,
- &gn_trg_shutdown_grp2_mux),
- FUNCTION("gn_trg_shutdown_m3",
- gn_trg_shutdown_grp3,
- &gn_trg_shutdown_grp3_mux),
- FUNCTION("i2c0", i2c0_grp, &i2c0_grp_mux),
- FUNCTION("i2c1", i2c1_grp, &i2c1_grp_mux),
- FUNCTION("i2s0", i2s0_grp, &i2s0_grp_mux),
- FUNCTION("i2s1_basic", i2s1_basic_grp, &i2s1_basic_grp_mux),
- FUNCTION("i2s1_rxd0_m0", i2s1_rxd0_grp0, &i2s1_rxd0_grp0_mux),
- FUNCTION("i2s1_rxd0_m1", i2s1_rxd0_grp1, &i2s1_rxd0_grp1_mux),
- FUNCTION("i2s1_rxd0_m2", i2s1_rxd0_grp2, &i2s1_rxd0_grp2_mux),
- FUNCTION("i2s1_rxd0_m3", i2s1_rxd0_grp3, &i2s1_rxd0_grp3_mux),
- FUNCTION("i2s1_rxd0_m4", i2s1_rxd0_grp4, &i2s1_rxd0_grp4_mux),
- FUNCTION("i2s1_rxd1_m0", i2s1_rxd1_grp0, &i2s1_rxd1_grp0_mux),
- FUNCTION("i2s1_rxd1_m1", i2s1_rxd1_grp1, &i2s1_rxd1_grp1_mux),
- FUNCTION("i2s1_rxd1_m2", i2s1_rxd1_grp2, &i2s1_rxd1_grp2_mux),
- FUNCTION("i2s1_rxd1_m3", i2s1_rxd1_grp3, &i2s1_rxd1_grp3_mux),
- FUNCTION("i2s1_rxd1_m4", i2s1_rxd1_grp4, &i2s1_rxd1_grp4_mux),
- FUNCTION("jtag_jt_dbg_nsrst",
- jtag_jt_dbg_nsrst_grp,
- &jtag_jt_dbg_nsrst_grp_mux),
- FUNCTION("jtag_ntrst_m0", jtag_ntrst_grp0, &jtag_ntrst_grp0_mux),
- FUNCTION("jtag_ntrst_m1", jtag_ntrst_grp1, &jtag_ntrst_grp1_mux),
- FUNCTION("jtag_swdiotms_m0",
- jtag_swdiotms_grp0,
- &jtag_swdiotms_grp0_mux),
- FUNCTION("jtag_swdiotms_m1",
- jtag_swdiotms_grp1,
- &jtag_swdiotms_grp1_mux),
- FUNCTION("jtag_tck_m0", jtag_tck_grp0, &jtag_tck_grp0_mux),
- FUNCTION("jtag_tck_m1", jtag_tck_grp1, &jtag_tck_grp1_mux),
- FUNCTION("jtag_tdi_m0", jtag_tdi_grp0, &jtag_tdi_grp0_mux),
- FUNCTION("jtag_tdi_m1", jtag_tdi_grp1, &jtag_tdi_grp1_mux),
- FUNCTION("jtag_tdo_m0", jtag_tdo_grp0, &jtag_tdo_grp0_mux),
- FUNCTION("jtag_tdo_m1", jtag_tdo_grp1, &jtag_tdo_grp1_mux),
- FUNCTION("ks_kas_spi_m0", ks_kas_spi_grp0, &ks_kas_spi_grp0_mux),
- FUNCTION("ld_ldd", ld_ldd_grp, &ld_ldd_grp_mux),
- FUNCTION("ld_ldd_16bit", ld_ldd_16bit_grp, &ld_ldd_16bit_grp_mux),
- FUNCTION("ld_ldd_fck", ld_ldd_fck_grp, &ld_ldd_fck_grp_mux),
- FUNCTION("ld_ldd_lck", ld_ldd_lck_grp, &ld_ldd_lck_grp_mux),
- FUNCTION("lr_lcdrom", lr_lcdrom_grp, &lr_lcdrom_grp_mux),
- FUNCTION("lvds_analog", lvds_analog_grp, &lvds_analog_grp_mux),
- FUNCTION("nd_df_basic", nd_df_basic_grp, &nd_df_basic_grp_mux),
- FUNCTION("nd_df_wp", nd_df_wp_grp, &nd_df_wp_grp_mux),
- FUNCTION("nd_df_cs", nd_df_cs_grp, &nd_df_cs_grp_mux),
- FUNCTION("ps", ps_grp, &ps_grp_mux),
- FUNCTION("ps_no_dir", ps_no_dir_grp, &ps_no_dir_grp_mux),
- FUNCTION("pwc_core_on", pwc_core_on_grp, &pwc_core_on_grp_mux),
- FUNCTION("pwc_ext_on", pwc_ext_on_grp, &pwc_ext_on_grp_mux),
- FUNCTION("pwc_gpio3_clk", pwc_gpio3_clk_grp, &pwc_gpio3_clk_grp_mux),
- FUNCTION("pwc_io_on", pwc_io_on_grp, &pwc_io_on_grp_mux),
- FUNCTION("pwc_lowbatt_b_m0",
- pwc_lowbatt_b_grp0,
- &pwc_lowbatt_b_grp0_mux),
- FUNCTION("pwc_mem_on", pwc_mem_on_grp, &pwc_mem_on_grp_mux),
- FUNCTION("pwc_on_key_b_m0",
- pwc_on_key_b_grp0,
- &pwc_on_key_b_grp0_mux),
- FUNCTION("pwc_wakeup_src0",
- pwc_wakeup_src0_grp,
- &pwc_wakeup_src0_grp_mux),
- FUNCTION("pwc_wakeup_src1",
- pwc_wakeup_src1_grp,
- &pwc_wakeup_src1_grp_mux),
- FUNCTION("pwc_wakeup_src2",
- pwc_wakeup_src2_grp,
- &pwc_wakeup_src2_grp_mux),
- FUNCTION("pwc_wakeup_src3",
- pwc_wakeup_src3_grp,
- &pwc_wakeup_src3_grp_mux),
- FUNCTION("pw_cko0_m0", pw_cko0_grp0, &pw_cko0_grp0_mux),
- FUNCTION("pw_cko0_m1", pw_cko0_grp1, &pw_cko0_grp1_mux),
- FUNCTION("pw_cko0_m2", pw_cko0_grp2, &pw_cko0_grp2_mux),
- FUNCTION("pw_cko0_m3", pw_cko0_grp3, &pw_cko0_grp3_mux),
- FUNCTION("pw_cko1_m0", pw_cko1_grp0, &pw_cko1_grp0_mux),
- FUNCTION("pw_cko1_m1", pw_cko1_grp1, &pw_cko1_grp1_mux),
- FUNCTION("pw_cko1_m2", pw_cko1_grp2, &pw_cko1_grp2_mux),
- FUNCTION("pw_i2s01_clk_m0",
- pw_i2s01_clk_grp0,
- &pw_i2s01_clk_grp0_mux),
- FUNCTION("pw_i2s01_clk_m1",
- pw_i2s01_clk_grp1,
- &pw_i2s01_clk_grp1_mux),
- FUNCTION("pw_i2s01_clk_m2",
- pw_i2s01_clk_grp2,
- &pw_i2s01_clk_grp2_mux),
- FUNCTION("pw_pwm0_m0", pw_pwm0_grp0, &pw_pwm0_grp0_mux),
- FUNCTION("pw_pwm0_m1", pw_pwm0_grp1, &pw_pwm0_grp1_mux),
- FUNCTION("pw_pwm1_m0", pw_pwm1_grp0, &pw_pwm1_grp0_mux),
- FUNCTION("pw_pwm1_m1", pw_pwm1_grp1, &pw_pwm1_grp1_mux),
- FUNCTION("pw_pwm1_m2", pw_pwm1_grp2, &pw_pwm1_grp2_mux),
- FUNCTION("pw_pwm2_m0", pw_pwm2_grp0, &pw_pwm2_grp0_mux),
- FUNCTION("pw_pwm2_m1", pw_pwm2_grp1, &pw_pwm2_grp1_mux),
- FUNCTION("pw_pwm2_m2", pw_pwm2_grp2, &pw_pwm2_grp2_mux),
- FUNCTION("pw_pwm3_m0", pw_pwm3_grp0, &pw_pwm3_grp0_mux),
- FUNCTION("pw_pwm3_m1", pw_pwm3_grp1, &pw_pwm3_grp1_mux),
- FUNCTION("pw_pwm_cpu_vol_m0",
- pw_pwm_cpu_vol_grp0,
- &pw_pwm_cpu_vol_grp0_mux),
- FUNCTION("pw_pwm_cpu_vol_m1",
- pw_pwm_cpu_vol_grp1,
- &pw_pwm_cpu_vol_grp1_mux),
- FUNCTION("pw_pwm_cpu_vol_m2",
- pw_pwm_cpu_vol_grp2,
- &pw_pwm_cpu_vol_grp2_mux),
- FUNCTION("pw_backlight_m0",
- pw_backlight_grp0,
- &pw_backlight_grp0_mux),
- FUNCTION("pw_backlight_m1",
- pw_backlight_grp1,
- &pw_backlight_grp1_mux),
- FUNCTION("rg_eth_mac", rg_eth_mac_grp, &rg_eth_mac_grp_mux),
- FUNCTION("rg_gmac_phy_intr_n",
- rg_gmac_phy_intr_n_grp,
- &rg_gmac_phy_intr_n_grp_mux),
- FUNCTION("rg_rgmii_mac", rg_rgmii_mac_grp, &rg_rgmii_mac_grp_mux),
- FUNCTION("rg_rgmii_phy_ref_clk_m0",
- rg_rgmii_phy_ref_clk_grp0,
- &rg_rgmii_phy_ref_clk_grp0_mux),
- FUNCTION("rg_rgmii_phy_ref_clk_m1",
- rg_rgmii_phy_ref_clk_grp1,
- &rg_rgmii_phy_ref_clk_grp1_mux),
- FUNCTION("sd0", sd0_grp, &sd0_grp_mux),
- FUNCTION("sd0_4bit", sd0_4bit_grp, &sd0_4bit_grp_mux),
- FUNCTION("sd1", sd1_grp, &sd1_grp_mux),
- FUNCTION("sd1_4bit_m0", sd1_4bit_grp0, &sd1_4bit_grp0_mux),
- FUNCTION("sd1_4bit_m1", sd1_4bit_grp1, &sd1_4bit_grp1_mux),
- FUNCTION("sd2_basic", sd2_basic_grp, &sd2_basic_grp_mux),
- FUNCTION("sd2_cdb_m0", sd2_cdb_grp0, &sd2_cdb_grp0_mux),
- FUNCTION("sd2_cdb_m1", sd2_cdb_grp1, &sd2_cdb_grp1_mux),
- FUNCTION("sd2_wpb_m0", sd2_wpb_grp0, &sd2_wpb_grp0_mux),
- FUNCTION("sd2_wpb_m1", sd2_wpb_grp1, &sd2_wpb_grp1_mux),
- FUNCTION("sd3", sd3_9_grp, &sd3_9_grp_mux),
- FUNCTION("sd5", sd5_grp, &sd5_grp_mux),
- FUNCTION("sd6_m0", sd6_grp0, &sd6_grp0_mux),
- FUNCTION("sd6_m1", sd6_grp1, &sd6_grp1_mux),
- FUNCTION("sd9", sd3_9_grp, &sd3_9_grp_mux),
- FUNCTION("sp0_ext_ldo_on",
- sp0_ext_ldo_on_grp,
- &sp0_ext_ldo_on_grp_mux),
- FUNCTION("sp0_qspi", sp0_qspi_grp, &sp0_qspi_grp_mux),
- FUNCTION("sp1_spi", sp1_spi_grp, &sp1_spi_grp_mux),
- FUNCTION("tpiu_trace", tpiu_trace_grp, &tpiu_trace_grp_mux),
- FUNCTION("uart0", uart0_grp, &uart0_grp_mux),
- FUNCTION("uart0_nopause", uart0_nopause_grp, &uart0_nopause_grp_mux),
- FUNCTION("uart1", uart1_grp, &uart1_grp_mux),
- FUNCTION("uart2_cts_m0", uart2_cts_grp0, &uart2_cts_grp0_mux),
- FUNCTION("uart2_cts_m1", uart2_cts_grp1, &uart2_cts_grp1_mux),
- FUNCTION("uart2_rts_m0", uart2_rts_grp0, &uart2_rts_grp0_mux),
- FUNCTION("uart2_rts_m1", uart2_rts_grp1, &uart2_rts_grp1_mux),
- FUNCTION("uart2_rxd_m0", uart2_rxd_grp0, &uart2_rxd_grp0_mux),
- FUNCTION("uart2_rxd_m1", uart2_rxd_grp1, &uart2_rxd_grp1_mux),
- FUNCTION("uart2_rxd_m2", uart2_rxd_grp2, &uart2_rxd_grp2_mux),
- FUNCTION("uart2_txd_m0", uart2_txd_grp0, &uart2_txd_grp0_mux),
- FUNCTION("uart2_txd_m1", uart2_txd_grp1, &uart2_txd_grp1_mux),
- FUNCTION("uart2_txd_m2", uart2_txd_grp2, &uart2_txd_grp2_mux),
- FUNCTION("uart3_cts_m0", uart3_cts_grp0, &uart3_cts_grp0_mux),
- FUNCTION("uart3_cts_m1", uart3_cts_grp1, &uart3_cts_grp1_mux),
- FUNCTION("uart3_cts_m2", uart3_cts_grp2, &uart3_cts_grp2_mux),
- FUNCTION("uart3_rts_m0", uart3_rts_grp0, &uart3_rts_grp0_mux),
- FUNCTION("uart3_rts_m1", uart3_rts_grp1, &uart3_rts_grp1_mux),
- FUNCTION("uart3_rts_m2", uart3_rts_grp2, &uart3_rts_grp2_mux),
- FUNCTION("uart3_rxd_m0", uart3_rxd_grp0, &uart3_rxd_grp0_mux),
- FUNCTION("uart3_rxd_m1", uart3_rxd_grp1, &uart3_rxd_grp1_mux),
- FUNCTION("uart3_rxd_m2", uart3_rxd_grp2, &uart3_rxd_grp2_mux),
- FUNCTION("uart3_txd_m0", uart3_txd_grp0, &uart3_txd_grp0_mux),
- FUNCTION("uart3_txd_m1", uart3_txd_grp1, &uart3_txd_grp1_mux),
- FUNCTION("uart3_txd_m2", uart3_txd_grp2, &uart3_txd_grp2_mux),
- FUNCTION("uart4_basic", uart4_basic_grp, &uart4_basic_grp_mux),
- FUNCTION("uart4_cts_m0", uart4_cts_grp0, &uart4_cts_grp0_mux),
- FUNCTION("uart4_cts_m1", uart4_cts_grp1, &uart4_cts_grp1_mux),
- FUNCTION("uart4_cts_m2", uart4_cts_grp2, &uart4_cts_grp2_mux),
- FUNCTION("uart4_rts_m0", uart4_rts_grp0, &uart4_rts_grp0_mux),
- FUNCTION("uart4_rts_m1", uart4_rts_grp1, &uart4_rts_grp1_mux),
- FUNCTION("uart4_rts_m2", uart4_rts_grp2, &uart4_rts_grp2_mux),
- FUNCTION("usb0_drvvbus_m0",
- usb0_drvvbus_grp0,
- &usb0_drvvbus_grp0_mux),
- FUNCTION("usb0_drvvbus_m1",
- usb0_drvvbus_grp1,
- &usb0_drvvbus_grp1_mux),
- FUNCTION("usb1_drvvbus_m0",
- usb1_drvvbus_grp0,
- &usb1_drvvbus_grp0_mux),
- FUNCTION("usb1_drvvbus_m1",
- usb1_drvvbus_grp1,
- &usb1_drvvbus_grp1_mux),
- FUNCTION("visbus_dout", visbus_dout_grp, &visbus_dout_grp_mux),
- FUNCTION("vi_vip1", vi_vip1_grp, &vi_vip1_grp_mux),
- FUNCTION("vi_vip1_ext", vi_vip1_ext_grp, &vi_vip1_ext_grp_mux),
- FUNCTION("vi_vip1_low8bit",
- vi_vip1_low8bit_grp,
- &vi_vip1_low8bit_grp_mux),
- FUNCTION("vi_vip1_high8bit",
- vi_vip1_high8bit_grp,
- &vi_vip1_high8bit_grp_mux),
-};
-
-static struct atlas7_pinctrl_data atlas7_ioc_data = {
- .pads = (struct pinctrl_pin_desc *)atlas7_ioc_pads,
- .pads_cnt = ARRAY_SIZE(atlas7_ioc_pads),
- .grps = (struct atlas7_pin_group *)altas7_pin_groups,
- .grps_cnt = ARRAY_SIZE(altas7_pin_groups),
- .funcs = (struct atlas7_pmx_func *)atlas7_pmx_functions,
- .funcs_cnt = ARRAY_SIZE(atlas7_pmx_functions),
- .confs = (struct atlas7_pad_config *)atlas7_ioc_pad_confs,
- .confs_cnt = ARRAY_SIZE(atlas7_ioc_pad_confs),
-};
-
-/* Simple map data structure */
-struct map_data {
- u8 idx;
- u8 data;
-};
-
-/**
- * struct atlas7_pull_info - Atlas7 Pad pull info
- * @pad_type: The type of this Pad.
- * @mask: The mas value of this pin's pull bits.
- * @v2s: The map of pull register value to pull status.
- * @s2v: The map of pull status to pull register value.
- */
-struct atlas7_pull_info {
- u8 pad_type;
- u8 mask;
- const struct map_data *v2s;
- const struct map_data *s2v;
-};
-
-/* Pull Register value map to status */
-static const struct map_data p4we_pull_v2s[] = {
- { P4WE_PULL_UP, PULL_UP },
- { P4WE_HIGH_HYSTERESIS, HIGH_HYSTERESIS },
- { P4WE_HIGH_Z, HIGH_Z },
- { P4WE_PULL_DOWN, PULL_DOWN },
-};
-
-static const struct map_data p16st_pull_v2s[] = {
- { P16ST_PULL_UP, PULL_UP },
- { PD, PULL_UNKNOWN },
- { P16ST_HIGH_Z, HIGH_Z },
- { P16ST_PULL_DOWN, PULL_DOWN },
-};
-
-static const struct map_data pm31_pull_v2s[] = {
- { PM31_PULL_DISABLED, PULL_DOWN },
- { PM31_PULL_ENABLED, PULL_UP },
-};
-
-static const struct map_data pangd_pull_v2s[] = {
- { PANGD_PULL_UP, PULL_UP },
- { PD, PULL_UNKNOWN },
- { PANGD_HIGH_Z, HIGH_Z },
- { PANGD_PULL_DOWN, PULL_DOWN },
-};
-
-/* Pull status map to register value */
-static const struct map_data p4we_pull_s2v[] = {
- { PULL_UP, P4WE_PULL_UP },
- { HIGH_HYSTERESIS, P4WE_HIGH_HYSTERESIS },
- { HIGH_Z, P4WE_HIGH_Z },
- { PULL_DOWN, P4WE_PULL_DOWN },
- { PULL_DISABLE, -1 },
- { PULL_ENABLE, -1 },
-};
-
-static const struct map_data p16st_pull_s2v[] = {
- { PULL_UP, P16ST_PULL_UP },
- { HIGH_HYSTERESIS, -1 },
- { HIGH_Z, P16ST_HIGH_Z },
- { PULL_DOWN, P16ST_PULL_DOWN },
- { PULL_DISABLE, -1 },
- { PULL_ENABLE, -1 },
-};
-
-static const struct map_data pm31_pull_s2v[] = {
- { PULL_UP, PM31_PULL_ENABLED },
- { HIGH_HYSTERESIS, -1 },
- { HIGH_Z, -1 },
- { PULL_DOWN, PM31_PULL_DISABLED },
- { PULL_DISABLE, -1 },
- { PULL_ENABLE, -1 },
-};
-
-static const struct map_data pangd_pull_s2v[] = {
- { PULL_UP, PANGD_PULL_UP },
- { HIGH_HYSTERESIS, -1 },
- { HIGH_Z, PANGD_HIGH_Z },
- { PULL_DOWN, PANGD_PULL_DOWN },
- { PULL_DISABLE, -1 },
- { PULL_ENABLE, -1 },
-};
-
-static const struct atlas7_pull_info atlas7_pull_map[] = {
- { PAD_T_4WE_PD, P4WE_PULL_MASK, p4we_pull_v2s, p4we_pull_s2v },
- { PAD_T_4WE_PU, P4WE_PULL_MASK, p4we_pull_v2s, p4we_pull_s2v },
- { PAD_T_16ST, P16ST_PULL_MASK, p16st_pull_v2s, p16st_pull_s2v },
- { PAD_T_M31_0204_PD, PM31_PULL_MASK, pm31_pull_v2s, pm31_pull_s2v },
- { PAD_T_M31_0204_PU, PM31_PULL_MASK, pm31_pull_v2s, pm31_pull_s2v },
- { PAD_T_M31_0610_PD, PM31_PULL_MASK, pm31_pull_v2s, pm31_pull_s2v },
- { PAD_T_M31_0610_PU, PM31_PULL_MASK, pm31_pull_v2s, pm31_pull_s2v },
- { PAD_T_AD, PANGD_PULL_MASK, pangd_pull_v2s, pangd_pull_s2v },
-};
-
-/**
- * struct atlas7_ds_ma_info - Atlas7 Pad DriveStrength & currents info
- * @ma: The Drive Strength in current value .
- * @ds_16st: The correspond raw value of 16st pad.
- * @ds_4we: The correspond raw value of 4we pad.
- * @ds_0204m31: The correspond raw value of 0204m31 pad.
- * @ds_0610m31: The correspond raw value of 0610m31 pad.
- */
-struct atlas7_ds_ma_info {
- u32 ma;
- u32 ds_16st;
- u32 ds_4we;
- u32 ds_0204m31;
- u32 ds_0610m31;
-};
-
-static const struct atlas7_ds_ma_info atlas7_ma2ds_map[] = {
- { 2, DS_16ST_0, DS_4WE_0, DS_M31_0, DS_NULL },
- { 4, DS_16ST_1, DS_NULL, DS_M31_1, DS_NULL },
- { 6, DS_16ST_2, DS_NULL, DS_NULL, DS_M31_0 },
- { 8, DS_16ST_3, DS_4WE_1, DS_NULL, DS_NULL },
- { 10, DS_16ST_4, DS_NULL, DS_NULL, DS_M31_1 },
- { 12, DS_16ST_5, DS_NULL, DS_NULL, DS_NULL },
- { 14, DS_16ST_6, DS_NULL, DS_NULL, DS_NULL },
- { 16, DS_16ST_7, DS_4WE_2, DS_NULL, DS_NULL },
- { 18, DS_16ST_8, DS_NULL, DS_NULL, DS_NULL },
- { 20, DS_16ST_9, DS_NULL, DS_NULL, DS_NULL },
- { 22, DS_16ST_10, DS_NULL, DS_NULL, DS_NULL },
- { 24, DS_16ST_11, DS_NULL, DS_NULL, DS_NULL },
- { 26, DS_16ST_12, DS_NULL, DS_NULL, DS_NULL },
- { 28, DS_16ST_13, DS_4WE_3, DS_NULL, DS_NULL },
- { 30, DS_16ST_14, DS_NULL, DS_NULL, DS_NULL },
- { 32, DS_16ST_15, DS_NULL, DS_NULL, DS_NULL },
-};
-
-/**
- * struct atlas7_ds_info - Atlas7 Pad DriveStrength info
- * @type: The type of this Pad.
- * @mask: The mask value of this pin's pull bits.
- * @imval: The immediate value of drives trength register.
- * @reserved: Reserved space
- */
-struct atlas7_ds_info {
- u8 type;
- u8 mask;
- u8 imval;
- u8 reserved;
-};
-
-static const struct atlas7_ds_info atlas7_ds_map[] = {
- { PAD_T_4WE_PD, DS_2BIT_MASK, DS_2BIT_IM_VAL },
- { PAD_T_4WE_PU, DS_2BIT_MASK, DS_2BIT_IM_VAL },
- { PAD_T_16ST, DS_4BIT_MASK, DS_4BIT_IM_VAL },
- { PAD_T_M31_0204_PD, DS_1BIT_MASK, DS_1BIT_IM_VAL },
- { PAD_T_M31_0204_PU, DS_1BIT_MASK, DS_1BIT_IM_VAL },
- { PAD_T_M31_0610_PD, DS_1BIT_MASK, DS_1BIT_IM_VAL },
- { PAD_T_M31_0610_PU, DS_1BIT_MASK, DS_1BIT_IM_VAL },
- { PAD_T_AD, DS_NULL, DS_NULL },
-};
-
-static inline u32 atlas7_pin_to_bank(u32 pin)
-{
- return (pin >= ATLAS7_PINCTRL_BANK_0_PINS) ? 1 : 0;
-}
-
-static int atlas7_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
-{
- struct atlas7_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
-
- return pmx->pctl_data->funcs_cnt;
-}
-
-static const char *atlas7_pmx_get_func_name(struct pinctrl_dev *pctldev,
- u32 selector)
-{
- struct atlas7_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
-
- return pmx->pctl_data->funcs[selector].name;
-}
-
-static int atlas7_pmx_get_func_groups(struct pinctrl_dev *pctldev,
- u32 selector, const char * const **groups,
- u32 * const num_groups)
-{
- struct atlas7_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
-
- *groups = pmx->pctl_data->funcs[selector].groups;
- *num_groups = pmx->pctl_data->funcs[selector].num_groups;
-
- return 0;
-}
-
-static void __atlas7_pmx_pin_input_disable_set(struct atlas7_pmx *pmx,
- const struct atlas7_pad_mux *mux)
-{
- /* Set Input Disable to avoid input glitches
- *
- * All Input-Disable Control registers are located on IOCRTC.
- * So the regs bank is always 0.
- *
- */
- if (mux->dinput_reg && mux->dinput_val_reg) {
- writel(DI_MASK << mux->dinput_bit,
- pmx->regs[BANK_DS] + CLR_REG(mux->dinput_reg));
- writel(DI_DISABLE << mux->dinput_bit,
- pmx->regs[BANK_DS] + mux->dinput_reg);
-
-
- writel(DIV_MASK << mux->dinput_val_bit,
- pmx->regs[BANK_DS] + CLR_REG(mux->dinput_val_reg));
- writel(DIV_DISABLE << mux->dinput_val_bit,
- pmx->regs[BANK_DS] + mux->dinput_val_reg);
- }
-}
-
-static void __atlas7_pmx_pin_input_disable_clr(struct atlas7_pmx *pmx,
- const struct atlas7_pad_mux *mux)
-{
- /* Clear Input Disable to avoid input glitches */
- if (mux->dinput_reg && mux->dinput_val_reg) {
- writel(DI_MASK << mux->dinput_bit,
- pmx->regs[BANK_DS] + CLR_REG(mux->dinput_reg));
- writel(DI_ENABLE << mux->dinput_bit,
- pmx->regs[BANK_DS] + mux->dinput_reg);
-
- writel(DIV_MASK << mux->dinput_val_bit,
- pmx->regs[BANK_DS] + CLR_REG(mux->dinput_val_reg));
- writel(DIV_ENABLE << mux->dinput_val_bit,
- pmx->regs[BANK_DS] + mux->dinput_val_reg);
- }
-}
-
-static int __atlas7_pmx_pin_ad_sel(struct atlas7_pmx *pmx,
- struct atlas7_pad_config *conf,
- u32 bank, u32 ad_sel)
-{
- unsigned long regv;
-
- /* Write to clear register to clear A/D selector */
- writel(ANA_CLEAR_MASK << conf->ad_ctrl_bit,
- pmx->regs[bank] + CLR_REG(conf->ad_ctrl_reg));
-
- /* Set target pad A/D selector */
- regv = readl(pmx->regs[bank] + conf->ad_ctrl_reg);
- regv &= ~(ANA_CLEAR_MASK << conf->ad_ctrl_bit);
- writel(regv | (ad_sel << conf->ad_ctrl_bit),
- pmx->regs[bank] + conf->ad_ctrl_reg);
-
- regv = readl(pmx->regs[bank] + conf->ad_ctrl_reg);
- pr_debug("bank:%d reg:0x%04x val:0x%08lx\n",
- bank, conf->ad_ctrl_reg, regv);
- return 0;
-}
-
-static int __atlas7_pmx_pin_analog_enable(struct atlas7_pmx *pmx,
- struct atlas7_pad_config *conf, u32 bank)
-{
- /* Only PAD_T_AD pins can change between Analogue&Digital */
- if (conf->type != PAD_T_AD)
- return -EINVAL;
-
- return __atlas7_pmx_pin_ad_sel(pmx, conf, bank, 0);
-}
-
-static int __atlas7_pmx_pin_digital_enable(struct atlas7_pmx *pmx,
- struct atlas7_pad_config *conf, u32 bank)
-{
- /* Other type pads are always digital */
- if (conf->type != PAD_T_AD)
- return 0;
-
- return __atlas7_pmx_pin_ad_sel(pmx, conf, bank, 1);
-}
-
-static int __atlas7_pmx_pin_enable(struct atlas7_pmx *pmx,
- u32 pin, u32 func)
-{
- struct atlas7_pad_config *conf;
- u32 bank;
- int ret;
- unsigned long regv;
-
- pr_debug("PMX DUMP ### pin#%d func:%d #### START >>>\n",
- pin, func);
-
- /* Get this Pad's descriptor from PINCTRL */
- conf = &pmx->pctl_data->confs[pin];
- bank = atlas7_pin_to_bank(pin);
-
- /* Just enable the analog function of this pad */
- if (FUNC_ANALOGUE == func) {
- ret = __atlas7_pmx_pin_analog_enable(pmx, conf, bank);
- if (ret)
- dev_err(pmx->dev,
- "Convert pad#%d to analog failed, ret=%d\n",
- pin, ret);
- return ret;
- }
-
- /* Set Pads from analog to digital */
- ret = __atlas7_pmx_pin_digital_enable(pmx, conf, bank);
- if (ret) {
- dev_err(pmx->dev,
- "Convert pad#%d to digital failed, ret=%d\n",
- pin, ret);
- return ret;
- }
-
- /* Write to clear register to clear current function */
- writel(FUNC_CLEAR_MASK << conf->mux_bit,
- pmx->regs[bank] + CLR_REG(conf->mux_reg));
-
- /* Set target pad mux function */
- regv = readl(pmx->regs[bank] + conf->mux_reg);
- regv &= ~(FUNC_CLEAR_MASK << conf->mux_bit);
- writel(regv | (func << conf->mux_bit),
- pmx->regs[bank] + conf->mux_reg);
-
- regv = readl(pmx->regs[bank] + conf->mux_reg);
- pr_debug("bank:%d reg:0x%04x val:0x%08lx\n",
- bank, conf->mux_reg, regv);
-
- return 0;
-}
-
-static int atlas7_pmx_set_mux(struct pinctrl_dev *pctldev,
- u32 func_selector, u32 group_selector)
-{
- int idx, ret;
- struct atlas7_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
- struct atlas7_pmx_func *pmx_func;
- struct atlas7_pin_group *pin_grp;
- const struct atlas7_grp_mux *grp_mux;
- const struct atlas7_pad_mux *mux;
-
- pmx_func = &pmx->pctl_data->funcs[func_selector];
- pin_grp = &pmx->pctl_data->grps[group_selector];
-
- pr_debug("PMX DUMP ### Function:[%s] Group:[%s] #### START >>>\n",
- pmx_func->name, pin_grp->name);
-
- /* the sd3 and sd9 pin select by SYS2PCI_SDIO9SEL register */
- if (pin_grp->pins == (unsigned int *)&sd3_9_pins) {
- if (!strcmp(pmx_func->name, "sd9"))
- writel(1, pmx->sys2pci_base + SYS2PCI_SDIO9SEL);
- else
- writel(0, pmx->sys2pci_base + SYS2PCI_SDIO9SEL);
- }
-
- grp_mux = pmx_func->grpmux;
-
- for (idx = 0; idx < grp_mux->pad_mux_count; idx++) {
- mux = &grp_mux->pad_mux_list[idx];
- __atlas7_pmx_pin_input_disable_set(pmx, mux);
- ret = __atlas7_pmx_pin_enable(pmx, mux->pin, mux->func);
- if (ret) {
- dev_err(pmx->dev,
- "FUNC:%s GRP:%s PIN#%d.%d failed, ret=%d\n",
- pmx_func->name, pin_grp->name,
- mux->pin, mux->func, ret);
- BUG_ON(1);
- }
- __atlas7_pmx_pin_input_disable_clr(pmx, mux);
- }
- pr_debug("PMX DUMP ### Function:[%s] Group:[%s] #### END <<<\n",
- pmx_func->name, pin_grp->name);
-
- return 0;
-}
-
-static u32 convert_current_to_drive_strength(u32 type, u32 ma)
-{
- int idx;
-
- for (idx = 0; idx < ARRAY_SIZE(atlas7_ma2ds_map); idx++) {
- if (atlas7_ma2ds_map[idx].ma != ma)
- continue;
-
- if (type == PAD_T_4WE_PD || type == PAD_T_4WE_PU)
- return atlas7_ma2ds_map[idx].ds_4we;
- else if (type == PAD_T_16ST)
- return atlas7_ma2ds_map[idx].ds_16st;
- else if (type == PAD_T_M31_0204_PD || type == PAD_T_M31_0204_PU)
- return atlas7_ma2ds_map[idx].ds_0204m31;
- else if (type == PAD_T_M31_0610_PD || type == PAD_T_M31_0610_PU)
- return atlas7_ma2ds_map[idx].ds_0610m31;
- }
-
- return DS_NULL;
-}
-
-static int altas7_pinctrl_set_pull_sel(struct pinctrl_dev *pctldev,
- u32 pin, u32 sel)
-{
- struct atlas7_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
- struct atlas7_pad_config *conf = &pmx->pctl_data->confs[pin];
- const struct atlas7_pull_info *pull_info;
- u32 bank;
- unsigned long regv;
- void __iomem *pull_sel_reg;
-
- bank = atlas7_pin_to_bank(pin);
- pull_info = &atlas7_pull_map[conf->type];
- pull_sel_reg = pmx->regs[bank] + conf->pupd_reg;
-
- /* Retrieve correspond register value from table by sel */
- regv = pull_info->s2v[sel].data & pull_info->mask;
-
- /* Clear & Set new value to pull register */
- writel(pull_info->mask << conf->pupd_bit, CLR_REG(pull_sel_reg));
- writel(regv << conf->pupd_bit, pull_sel_reg);
-
- pr_debug("PIN_CFG ### SET PIN#%d PULL SELECTOR:%d == OK ####\n",
- pin, sel);
- return 0;
-}
-
-static int __altas7_pinctrl_set_drive_strength_sel(struct pinctrl_dev *pctldev,
- u32 pin, u32 sel)
-{
- struct atlas7_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
- struct atlas7_pad_config *conf = &pmx->pctl_data->confs[pin];
- const struct atlas7_ds_info *ds_info;
- u32 bank;
- void __iomem *ds_sel_reg;
-
- ds_info = &atlas7_ds_map[conf->type];
- if (sel & (~(ds_info->mask)))
- goto unsupport;
-
- bank = atlas7_pin_to_bank(pin);
- ds_sel_reg = pmx->regs[bank] + conf->drvstr_reg;
-
- writel(ds_info->imval << conf->drvstr_bit, CLR_REG(ds_sel_reg));
- writel(sel << conf->drvstr_bit, ds_sel_reg);
-
- return 0;
-
-unsupport:
- pr_err("Pad#%d type[%d] doesn't support ds code[%d]!\n",
- pin, conf->type, sel);
- return -ENOTSUPP;
-}
-
-static int altas7_pinctrl_set_drive_strength_sel(struct pinctrl_dev *pctldev,
- u32 pin, u32 ma)
-{
- struct atlas7_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
- struct atlas7_pad_config *conf = &pmx->pctl_data->confs[pin];
- u32 type = conf->type;
- u32 sel;
- int ret;
-
- sel = convert_current_to_drive_strength(conf->type, ma);
- if (DS_NULL == sel) {
- pr_err("Pad#%d type[%d] doesn't support ds current[%d]!\n",
- pin, type, ma);
- return -ENOTSUPP;
- }
-
- ret = __altas7_pinctrl_set_drive_strength_sel(pctldev,
- pin, sel);
- pr_debug("PIN_CFG ### SET PIN#%d DS:%d MA:%d == %s ####\n",
- pin, sel, ma, ret?"FAILED":"OK");
- return ret;
-}
-
-static int atlas7_pmx_gpio_request_enable(struct pinctrl_dev *pctldev,
- struct pinctrl_gpio_range *range, u32 pin)
-{
- struct atlas7_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
- u32 idx;
-
- dev_dbg(pmx->dev,
- "atlas7_pmx_gpio_request_enable: pin=%d\n", pin);
- for (idx = 0; idx < range->npins; idx++) {
- if (pin == range->pins[idx])
- break;
- }
-
- if (idx >= range->npins) {
- dev_err(pmx->dev,
- "The pin#%d could not be requested as GPIO!!\n",
- pin);
- return -EPERM;
- }
-
- __atlas7_pmx_pin_enable(pmx, pin, FUNC_GPIO);
-
- return 0;
-}
-
-static const struct pinmux_ops atlas7_pinmux_ops = {
- .get_functions_count = atlas7_pmx_get_funcs_count,
- .get_function_name = atlas7_pmx_get_func_name,
- .get_function_groups = atlas7_pmx_get_func_groups,
- .set_mux = atlas7_pmx_set_mux,
- .gpio_request_enable = atlas7_pmx_gpio_request_enable,
-};
-
-static int atlas7_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
-{
- struct atlas7_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
-
- return pmx->pctl_data->grps_cnt;
-}
-
-static const char *atlas7_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
- u32 group)
-{
- struct atlas7_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
-
- return pmx->pctl_data->grps[group].name;
-}
-
-static int atlas7_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
- u32 group, const u32 **pins, u32 *num_pins)
-{
- struct atlas7_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
-
- *num_pins = pmx->pctl_data->grps[group].num_pins;
- *pins = pmx->pctl_data->grps[group].pins;
-
- return 0;
-}
-
-static int atlas7_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
- struct device_node *np_config,
- struct pinctrl_map **map,
- u32 *num_maps)
-{
- return pinconf_generic_dt_node_to_map(pctldev, np_config, map,
- num_maps, PIN_MAP_TYPE_INVALID);
-}
-
-static void atlas7_pinctrl_dt_free_map(struct pinctrl_dev *pctldev,
- struct pinctrl_map *map, u32 num_maps)
-{
- kfree(map);
-}
-
-static const struct pinctrl_ops atlas7_pinctrl_ops = {
- .get_groups_count = atlas7_pinctrl_get_groups_count,
- .get_group_name = atlas7_pinctrl_get_group_name,
- .get_group_pins = atlas7_pinctrl_get_group_pins,
- .dt_node_to_map = atlas7_pinctrl_dt_node_to_map,
- .dt_free_map = atlas7_pinctrl_dt_free_map,
-};
-
-static int atlas7_pin_config_set(struct pinctrl_dev *pctldev,
- unsigned pin, unsigned long *configs,
- unsigned num_configs)
-{
- u16 param;
- u32 arg;
- int idx, err;
-
- for (idx = 0; idx < num_configs; idx++) {
- param = pinconf_to_config_param(configs[idx]);
- arg = pinconf_to_config_argument(configs[idx]);
-
- pr_debug("PMX CFG###### ATLAS7 PIN#%d [%s] CONFIG PARAM:%d ARG:%d >>>>>\n",
- pin, atlas7_ioc_pads[pin].name, param, arg);
- switch (param) {
- case PIN_CONFIG_BIAS_PULL_UP:
- err = altas7_pinctrl_set_pull_sel(pctldev,
- pin, PULL_UP);
- if (err)
- return err;
- break;
-
- case PIN_CONFIG_BIAS_PULL_DOWN:
- err = altas7_pinctrl_set_pull_sel(pctldev,
- pin, PULL_DOWN);
- if (err)
- return err;
- break;
-
- case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
- err = altas7_pinctrl_set_pull_sel(pctldev,
- pin, HIGH_HYSTERESIS);
- if (err)
- return err;
- break;
- case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
- err = altas7_pinctrl_set_pull_sel(pctldev,
- pin, HIGH_Z);
- if (err)
- return err;
- break;
-
- case PIN_CONFIG_DRIVE_STRENGTH:
- err = altas7_pinctrl_set_drive_strength_sel(pctldev,
- pin, arg);
- if (err)
- return err;
- break;
- default:
- return -ENOTSUPP;
- }
- pr_debug("PMX CFG###### ATLAS7 PIN#%d [%s] CONFIG PARAM:%d ARG:%d <<<<\n",
- pin, atlas7_ioc_pads[pin].name, param, arg);
- }
-
- return 0;
-}
-
-static int atlas7_pin_config_group_set(struct pinctrl_dev *pctldev,
- unsigned group, unsigned long *configs,
- unsigned num_configs)
-{
- const unsigned *pins;
- unsigned npins;
- int i, ret;
-
- ret = atlas7_pinctrl_get_group_pins(pctldev, group, &pins, &npins);
- if (ret)
- return ret;
- for (i = 0; i < npins; i++) {
- if (atlas7_pin_config_set(pctldev, pins[i],
- configs, num_configs))
- return -ENOTSUPP;
- }
- return 0;
-}
-
-static const struct pinconf_ops atlas7_pinconf_ops = {
- .pin_config_set = atlas7_pin_config_set,
- .pin_config_group_set = atlas7_pin_config_group_set,
- .is_generic = true,
-};
-
-static int atlas7_pinmux_probe(struct platform_device *pdev)
-{
- int ret, idx;
- struct atlas7_pmx *pmx;
- struct device_node *np = pdev->dev.of_node;
- u32 banks = ATLAS7_PINCTRL_REG_BANKS;
- struct device_node *sys2pci_np;
- struct resource res;
-
- /* Create state holders etc for this driver */
- pmx = devm_kzalloc(&pdev->dev, sizeof(*pmx), GFP_KERNEL);
- if (!pmx)
- return -ENOMEM;
-
- /* The sd3 and sd9 shared all pins, and the function select by
- * SYS2PCI_SDIO9SEL register
- */
- sys2pci_np = of_find_node_by_name(NULL, "sys2pci");
- if (!sys2pci_np)
- return -EINVAL;
-
- ret = of_address_to_resource(sys2pci_np, 0, &res);
- of_node_put(sys2pci_np);
- if (ret)
- return ret;
-
- pmx->sys2pci_base = devm_ioremap_resource(&pdev->dev, &res);
- if (IS_ERR(pmx->sys2pci_base))
- return -ENOMEM;
-
- pmx->dev = &pdev->dev;
-
- pmx->pctl_data = &atlas7_ioc_data;
- pmx->pctl_desc.name = "pinctrl-atlas7";
- pmx->pctl_desc.pins = pmx->pctl_data->pads;
- pmx->pctl_desc.npins = pmx->pctl_data->pads_cnt;
- pmx->pctl_desc.pctlops = &atlas7_pinctrl_ops;
- pmx->pctl_desc.pmxops = &atlas7_pinmux_ops;
- pmx->pctl_desc.confops = &atlas7_pinconf_ops;
-
- for (idx = 0; idx < banks; idx++) {
- pmx->regs[idx] = of_iomap(np, idx);
- if (!pmx->regs[idx]) {
- dev_err(&pdev->dev,
- "can't map ioc bank#%d registers\n", idx);
- ret = -ENOMEM;
- goto unmap_io;
- }
- }
-
- /* Now register the pin controller and all pins it handles */
- pmx->pctl = pinctrl_register(&pmx->pctl_desc, &pdev->dev, pmx);
- if (IS_ERR(pmx->pctl)) {
- dev_err(&pdev->dev, "could not register atlas7 pinmux driver\n");
- ret = PTR_ERR(pmx->pctl);
- goto unmap_io;
- }
-
- platform_set_drvdata(pdev, pmx);
-
- dev_info(&pdev->dev, "initialized atlas7 pinmux driver\n");
-
- return 0;
-
-unmap_io:
- for (idx = 0; idx < banks; idx++) {
- if (!pmx->regs[idx])
- break;
- iounmap(pmx->regs[idx]);
- }
-
- return ret;
-}
-
-#ifdef CONFIG_PM_SLEEP
-static int atlas7_pinmux_suspend_noirq(struct device *dev)
-{
- struct atlas7_pmx *pmx = dev_get_drvdata(dev);
- struct atlas7_pad_status *status;
- struct atlas7_pad_config *conf;
- const struct atlas7_ds_info *ds_info;
- const struct atlas7_pull_info *pull_info;
- int idx;
- u32 bank;
- unsigned long regv;
-
- for (idx = 0; idx < pmx->pctl_desc.npins; idx++) {
- /* Get this Pad's descriptor from PINCTRL */
- conf = &pmx->pctl_data->confs[idx];
- bank = atlas7_pin_to_bank(idx);
- status = &pmx->sleep_data[idx];
-
- /* Save Function selector */
- regv = readl(pmx->regs[bank] + conf->mux_reg);
- status->func = (regv >> conf->mux_bit) & FUNC_CLEAR_MASK;
-
- /* Check if Pad is in Analogue selector */
- if (conf->ad_ctrl_reg == -1)
- goto save_ds_sel;
-
- regv = readl(pmx->regs[bank] + conf->ad_ctrl_reg);
- if (!(regv & (conf->ad_ctrl_bit << ANA_CLEAR_MASK)))
- status->func = FUNC_ANALOGUE;
-
-save_ds_sel:
- if (conf->drvstr_reg == -1)
- goto save_pull_sel;
-
- /* Save Drive Strength selector */
- ds_info = &atlas7_ds_map[conf->type];
- regv = readl(pmx->regs[bank] + conf->drvstr_reg);
- status->dstr = (regv >> conf->drvstr_bit) & ds_info->mask;
-
-save_pull_sel:
- /* Save Pull selector */
- pull_info = &atlas7_pull_map[conf->type];
- regv = readl(pmx->regs[bank] + conf->pupd_reg);
- regv = (regv >> conf->pupd_bit) & pull_info->mask;
- status->pull = pull_info->v2s[regv].data;
- }
-
- /*
- * Save disable input selector, this selector is not for Pin,
- * but for Mux function.
- */
- for (idx = 0; idx < NUM_OF_IN_DISABLE_REG; idx++) {
- pmx->status_ds[idx] = readl(pmx->regs[BANK_DS] +
- IN_DISABLE_0_REG_SET + 0x8 * idx);
- pmx->status_dsv[idx] = readl(pmx->regs[BANK_DS] +
- IN_DISABLE_VAL_0_REG_SET + 0x8 * idx);
- }
-
- return 0;
-}
-
-static int atlas7_pinmux_resume_noirq(struct device *dev)
-{
- struct atlas7_pmx *pmx = dev_get_drvdata(dev);
- struct atlas7_pad_status *status;
- int idx;
-
- for (idx = 0; idx < pmx->pctl_desc.npins; idx++) {
- /* Get this Pad's descriptor from PINCTRL */
- status = &pmx->sleep_data[idx];
-
- /* Restore Function selector */
- __atlas7_pmx_pin_enable(pmx, idx, (u32)status->func & 0xff);
-
- if (FUNC_ANALOGUE == status->func)
- goto restore_pull_sel;
-
- /* Restore Drive Strength selector */
- __altas7_pinctrl_set_drive_strength_sel(pmx->pctl, idx,
- (u32)status->dstr & 0xff);
-
-restore_pull_sel:
- /* Restore Pull selector */
- altas7_pinctrl_set_pull_sel(pmx->pctl, idx,
- (u32)status->pull & 0xff);
- }
-
- /*
- * Restore disable input selector, this selector is not for Pin,
- * but for Mux function
- */
- for (idx = 0; idx < NUM_OF_IN_DISABLE_REG; idx++) {
- writel(~0, pmx->regs[BANK_DS] +
- IN_DISABLE_0_REG_CLR + 0x8 * idx);
- writel(pmx->status_ds[idx], pmx->regs[BANK_DS] +
- IN_DISABLE_0_REG_SET + 0x8 * idx);
- writel(~0, pmx->regs[BANK_DS] +
- IN_DISABLE_VAL_0_REG_CLR + 0x8 * idx);
- writel(pmx->status_dsv[idx], pmx->regs[BANK_DS] +
- IN_DISABLE_VAL_0_REG_SET + 0x8 * idx);
- }
-
- return 0;
-}
-
-static const struct dev_pm_ops atlas7_pinmux_pm_ops = {
- .suspend_noirq = atlas7_pinmux_suspend_noirq,
- .resume_noirq = atlas7_pinmux_resume_noirq,
- .freeze_noirq = atlas7_pinmux_suspend_noirq,
- .restore_noirq = atlas7_pinmux_resume_noirq,
-};
-#endif
-
-static const struct of_device_id atlas7_pinmux_ids[] = {
- { .compatible = "sirf,atlas7-ioc",},
- {},
-};
-
-static struct platform_driver atlas7_pinmux_driver = {
- .driver = {
- .name = "atlas7-ioc",
- .of_match_table = atlas7_pinmux_ids,
-#ifdef CONFIG_PM_SLEEP
- .pm = &atlas7_pinmux_pm_ops,
-#endif
- },
- .probe = atlas7_pinmux_probe,
-};
-
-static int __init atlas7_pinmux_init(void)
-{
- return platform_driver_register(&atlas7_pinmux_driver);
-}
-arch_initcall(atlas7_pinmux_init);
-
-
-/*
- * The Following is GPIO Code
- */
-static inline struct
-atlas7_gpio_bank *atlas7_gpio_to_bank(struct atlas7_gpio_chip *a7gc, u32 gpio)
-{
- return &a7gc->banks[GPIO_TO_BANK(gpio)];
-}
-
-static int __atlas7_gpio_to_pin(struct atlas7_gpio_chip *a7gc, u32 gpio)
-{
- struct atlas7_gpio_bank *bank;
- u32 ofs;
-
- bank = atlas7_gpio_to_bank(a7gc, gpio);
- ofs = gpio - bank->gpio_offset;
- if (ofs >= bank->ngpio)
- return -ENODEV;
-
- return bank->gpio_pins[ofs];
-}
-
-static void atlas7_gpio_irq_ack(struct irq_data *d)
-{
- struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
- struct atlas7_gpio_chip *a7gc = gpiochip_get_data(gc);
- struct atlas7_gpio_bank *bank;
- void __iomem *ctrl_reg;
- u32 val, pin_in_bank;
- unsigned long flags;
-
- bank = atlas7_gpio_to_bank(a7gc, d->hwirq);
- pin_in_bank = d->hwirq - bank->gpio_offset;
- ctrl_reg = ATLAS7_GPIO_CTRL(bank, pin_in_bank);
-
- raw_spin_lock_irqsave(&a7gc->lock, flags);
-
- val = readl(ctrl_reg);
- /* clear interrupt status */
- writel(val, ctrl_reg);
-
- raw_spin_unlock_irqrestore(&a7gc->lock, flags);
-}
-
-static void __atlas7_gpio_irq_mask(struct atlas7_gpio_chip *a7gc, int idx)
-{
- struct atlas7_gpio_bank *bank;
- void __iomem *ctrl_reg;
- u32 val, pin_in_bank;
-
- bank = atlas7_gpio_to_bank(a7gc, idx);
- pin_in_bank = idx - bank->gpio_offset;
- ctrl_reg = ATLAS7_GPIO_CTRL(bank, pin_in_bank);
-
- val = readl(ctrl_reg);
- val &= ~(ATLAS7_GPIO_CTL_INTR_EN_MASK |
- ATLAS7_GPIO_CTL_INTR_STATUS_MASK);
- writel(val, ctrl_reg);
-}
-
-static void atlas7_gpio_irq_mask(struct irq_data *d)
-{
- struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
- struct atlas7_gpio_chip *a7gc = gpiochip_get_data(gc);
- unsigned long flags;
-
- raw_spin_lock_irqsave(&a7gc->lock, flags);
-
- __atlas7_gpio_irq_mask(a7gc, d->hwirq);
-
- raw_spin_unlock_irqrestore(&a7gc->lock, flags);
-}
-
-static void atlas7_gpio_irq_unmask(struct irq_data *d)
-{
- struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
- struct atlas7_gpio_chip *a7gc = gpiochip_get_data(gc);
- struct atlas7_gpio_bank *bank;
- void __iomem *ctrl_reg;
- u32 val, pin_in_bank;
- unsigned long flags;
-
- bank = atlas7_gpio_to_bank(a7gc, d->hwirq);
- pin_in_bank = d->hwirq - bank->gpio_offset;
- ctrl_reg = ATLAS7_GPIO_CTRL(bank, pin_in_bank);
-
- raw_spin_lock_irqsave(&a7gc->lock, flags);
-
- val = readl(ctrl_reg);
- val &= ~ATLAS7_GPIO_CTL_INTR_STATUS_MASK;
- val |= ATLAS7_GPIO_CTL_INTR_EN_MASK;
- writel(val, ctrl_reg);
-
- raw_spin_unlock_irqrestore(&a7gc->lock, flags);
-}
-
-static int atlas7_gpio_irq_type(struct irq_data *d,
- unsigned int type)
-{
- struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
- struct atlas7_gpio_chip *a7gc = gpiochip_get_data(gc);
- struct atlas7_gpio_bank *bank;
- void __iomem *ctrl_reg;
- u32 val, pin_in_bank;
- unsigned long flags;
-
- bank = atlas7_gpio_to_bank(a7gc, d->hwirq);
- pin_in_bank = d->hwirq - bank->gpio_offset;
- ctrl_reg = ATLAS7_GPIO_CTRL(bank, pin_in_bank);
-
- raw_spin_lock_irqsave(&a7gc->lock, flags);
-
- val = readl(ctrl_reg);
- val &= ~(ATLAS7_GPIO_CTL_INTR_STATUS_MASK |
- ATLAS7_GPIO_CTL_INTR_EN_MASK);
-
- switch (type) {
- case IRQ_TYPE_NONE:
- break;
-
- case IRQ_TYPE_EDGE_RISING:
- val |= ATLAS7_GPIO_CTL_INTR_HIGH_MASK |
- ATLAS7_GPIO_CTL_INTR_TYPE_MASK;
- val &= ~ATLAS7_GPIO_CTL_INTR_LOW_MASK;
- break;
-
- case IRQ_TYPE_EDGE_FALLING:
- val &= ~ATLAS7_GPIO_CTL_INTR_HIGH_MASK;
- val |= ATLAS7_GPIO_CTL_INTR_LOW_MASK |
- ATLAS7_GPIO_CTL_INTR_TYPE_MASK;
- break;
-
- case IRQ_TYPE_EDGE_BOTH:
- val |= ATLAS7_GPIO_CTL_INTR_HIGH_MASK |
- ATLAS7_GPIO_CTL_INTR_LOW_MASK |
- ATLAS7_GPIO_CTL_INTR_TYPE_MASK;
- break;
-
- case IRQ_TYPE_LEVEL_LOW:
- val &= ~(ATLAS7_GPIO_CTL_INTR_HIGH_MASK |
- ATLAS7_GPIO_CTL_INTR_TYPE_MASK);
- val |= ATLAS7_GPIO_CTL_INTR_LOW_MASK;
- break;
-
- case IRQ_TYPE_LEVEL_HIGH:
- val |= ATLAS7_GPIO_CTL_INTR_HIGH_MASK;
- val &= ~(ATLAS7_GPIO_CTL_INTR_LOW_MASK |
- ATLAS7_GPIO_CTL_INTR_TYPE_MASK);
- break;
- }
-
- writel(val, ctrl_reg);
-
- raw_spin_unlock_irqrestore(&a7gc->lock, flags);
-
- return 0;
-}
-
-static struct irq_chip atlas7_gpio_irq_chip = {
- .name = "atlas7-gpio-irq",
- .irq_ack = atlas7_gpio_irq_ack,
- .irq_mask = atlas7_gpio_irq_mask,
- .irq_unmask = atlas7_gpio_irq_unmask,
- .irq_set_type = atlas7_gpio_irq_type,
-};
-
-static void atlas7_gpio_handle_irq(struct irq_desc *desc)
-{
- struct gpio_chip *gc = irq_desc_get_handler_data(desc);
- struct atlas7_gpio_chip *a7gc = gpiochip_get_data(gc);
- struct atlas7_gpio_bank *bank = NULL;
- u32 status, ctrl;
- int pin_in_bank = 0, idx;
- struct irq_chip *chip = irq_desc_get_chip(desc);
- unsigned int irq = irq_desc_get_irq(desc);
-
- for (idx = 0; idx < a7gc->nbank; idx++) {
- bank = &a7gc->banks[idx];
- if (bank->irq == irq)
- break;
- }
- BUG_ON(idx == a7gc->nbank);
-
- chained_irq_enter(chip, desc);
-
- status = readl(ATLAS7_GPIO_INT_STATUS(bank));
- if (!status) {
- pr_warn("%s: gpio [%s] status %#x no interrupt is flagged\n",
- __func__, gc->label, status);
- handle_bad_irq(desc);
- return;
- }
-
- while (status) {
- ctrl = readl(ATLAS7_GPIO_CTRL(bank, pin_in_bank));
-
- /*
- * Here we must check whether the corresponding GPIO's
- * interrupt has been enabled, otherwise just skip it
- */
- if ((status & 0x1) && (ctrl & ATLAS7_GPIO_CTL_INTR_EN_MASK)) {
- pr_debug("%s: chip[%s] gpio:%d happens\n",
- __func__, gc->label,
- bank->gpio_offset + pin_in_bank);
- generic_handle_irq(
- irq_find_mapping(gc->irq.domain,
- bank->gpio_offset + pin_in_bank));
- }
-
- if (++pin_in_bank >= bank->ngpio)
- break;
-
- status = status >> 1;
- }
-
- chained_irq_exit(chip, desc);
-}
-
-static void __atlas7_gpio_set_input(struct atlas7_gpio_chip *a7gc,
- unsigned int gpio)
-{
- struct atlas7_gpio_bank *bank;
- void __iomem *ctrl_reg;
- u32 val, pin_in_bank;
-
- bank = atlas7_gpio_to_bank(a7gc, gpio);
- pin_in_bank = gpio - bank->gpio_offset;
- ctrl_reg = ATLAS7_GPIO_CTRL(bank, pin_in_bank);
-
- val = readl(ctrl_reg);
- val &= ~ATLAS7_GPIO_CTL_OUT_EN_MASK;
- writel(val, ctrl_reg);
-}
-
-static int atlas7_gpio_request(struct gpio_chip *chip,
- unsigned int gpio)
-{
- struct atlas7_gpio_chip *a7gc = gpiochip_get_data(chip);
- int ret;
- unsigned long flags;
-
- ret = __atlas7_gpio_to_pin(a7gc, gpio);
- if (ret < 0)
- return ret;
-
- if (pinctrl_gpio_request(chip->base + gpio))
- return -ENODEV;
-
- raw_spin_lock_irqsave(&a7gc->lock, flags);
-
- /*
- * default status:
- * set direction as input and mask irq
- */
- __atlas7_gpio_set_input(a7gc, gpio);
- __atlas7_gpio_irq_mask(a7gc, gpio);
-
- raw_spin_unlock_irqrestore(&a7gc->lock, flags);
-
- return 0;
-}
-
-static void atlas7_gpio_free(struct gpio_chip *chip,
- unsigned int gpio)
-{
- struct atlas7_gpio_chip *a7gc = gpiochip_get_data(chip);
- unsigned long flags;
-
- raw_spin_lock_irqsave(&a7gc->lock, flags);
-
- __atlas7_gpio_irq_mask(a7gc, gpio);
- __atlas7_gpio_set_input(a7gc, gpio);
-
- raw_spin_unlock_irqrestore(&a7gc->lock, flags);
-
- pinctrl_gpio_free(chip->base + gpio);
-}
-
-static int atlas7_gpio_direction_input(struct gpio_chip *chip,
- unsigned int gpio)
-{
- struct atlas7_gpio_chip *a7gc = gpiochip_get_data(chip);
- unsigned long flags;
-
- raw_spin_lock_irqsave(&a7gc->lock, flags);
-
- __atlas7_gpio_set_input(a7gc, gpio);
-
- raw_spin_unlock_irqrestore(&a7gc->lock, flags);
-
- return 0;
-}
-
-static void __atlas7_gpio_set_output(struct atlas7_gpio_chip *a7gc,
- unsigned int gpio, int value)
-{
- struct atlas7_gpio_bank *bank;
- void __iomem *ctrl_reg;
- u32 out_ctrl, pin_in_bank;
-
- bank = atlas7_gpio_to_bank(a7gc, gpio);
- pin_in_bank = gpio - bank->gpio_offset;
- ctrl_reg = ATLAS7_GPIO_CTRL(bank, pin_in_bank);
-
- out_ctrl = readl(ctrl_reg);
- if (value)
- out_ctrl |= ATLAS7_GPIO_CTL_DATAOUT_MASK;
- else
- out_ctrl &= ~ATLAS7_GPIO_CTL_DATAOUT_MASK;
-
- out_ctrl &= ~ATLAS7_GPIO_CTL_INTR_EN_MASK;
- out_ctrl |= ATLAS7_GPIO_CTL_OUT_EN_MASK;
- writel(out_ctrl, ctrl_reg);
-}
-
-static int atlas7_gpio_direction_output(struct gpio_chip *chip,
- unsigned int gpio, int value)
-{
- struct atlas7_gpio_chip *a7gc = gpiochip_get_data(chip);
- unsigned long flags;
-
- raw_spin_lock_irqsave(&a7gc->lock, flags);
-
- __atlas7_gpio_set_output(a7gc, gpio, value);
-
- raw_spin_unlock_irqrestore(&a7gc->lock, flags);
-
- return 0;
-}
-
-static int atlas7_gpio_get_value(struct gpio_chip *chip,
- unsigned int gpio)
-{
- struct atlas7_gpio_chip *a7gc = gpiochip_get_data(chip);
- struct atlas7_gpio_bank *bank;
- u32 val, pin_in_bank;
- unsigned long flags;
-
- bank = atlas7_gpio_to_bank(a7gc, gpio);
- pin_in_bank = gpio - bank->gpio_offset;
-
- raw_spin_lock_irqsave(&a7gc->lock, flags);
-
- val = readl(ATLAS7_GPIO_CTRL(bank, pin_in_bank));
-
- raw_spin_unlock_irqrestore(&a7gc->lock, flags);
-
- return !!(val & ATLAS7_GPIO_CTL_DATAIN_MASK);
-}
-
-static void atlas7_gpio_set_value(struct gpio_chip *chip,
- unsigned int gpio, int value)
-{
- struct atlas7_gpio_chip *a7gc = gpiochip_get_data(chip);
- struct atlas7_gpio_bank *bank;
- void __iomem *ctrl_reg;
- u32 ctrl, pin_in_bank;
- unsigned long flags;
-
- bank = atlas7_gpio_to_bank(a7gc, gpio);
- pin_in_bank = gpio - bank->gpio_offset;
- ctrl_reg = ATLAS7_GPIO_CTRL(bank, pin_in_bank);
-
- raw_spin_lock_irqsave(&a7gc->lock, flags);
-
- ctrl = readl(ctrl_reg);
- if (value)
- ctrl |= ATLAS7_GPIO_CTL_DATAOUT_MASK;
- else
- ctrl &= ~ATLAS7_GPIO_CTL_DATAOUT_MASK;
- writel(ctrl, ctrl_reg);
-
- raw_spin_unlock_irqrestore(&a7gc->lock, flags);
-}
-
-static const struct of_device_id atlas7_gpio_ids[] = {
- { .compatible = "sirf,atlas7-gpio", },
- {},
-};
-
-static int atlas7_gpio_probe(struct platform_device *pdev)
-{
- struct device_node *np = pdev->dev.of_node;
- struct atlas7_gpio_chip *a7gc;
- struct gpio_chip *chip;
- u32 nbank;
- int ret, idx;
- struct gpio_irq_chip *girq;
-
- ret = of_property_read_u32(np, "gpio-banks", &nbank);
- if (ret) {
- dev_err(&pdev->dev,
- "Could not find GPIO bank info,ret=%d!\n",
- ret);
- return ret;
- }
-
- /* retrieve gpio descriptor data */
- a7gc = devm_kzalloc(&pdev->dev, struct_size(a7gc, banks, nbank),
- GFP_KERNEL);
- if (!a7gc)
- return -ENOMEM;
-
- /* Get Gpio clk */
- a7gc->clk = of_clk_get(np, 0);
- if (!IS_ERR(a7gc->clk)) {
- ret = clk_prepare_enable(a7gc->clk);
- if (ret) {
- dev_err(&pdev->dev,
- "Could not enable clock!\n");
- return ret;
- }
- }
-
- /* Get Gpio Registers */
- a7gc->reg = of_iomap(np, 0);
- if (!a7gc->reg) {
- dev_err(&pdev->dev, "Could not map GPIO Registers!\n");
- return -ENOMEM;
- }
-
- a7gc->nbank = nbank;
- raw_spin_lock_init(&a7gc->lock);
-
- /* Setup GPIO Chip */
- chip = &a7gc->chip;
- chip->request = atlas7_gpio_request;
- chip->free = atlas7_gpio_free;
- chip->direction_input = atlas7_gpio_direction_input;
- chip->get = atlas7_gpio_get_value;
- chip->direction_output = atlas7_gpio_direction_output;
- chip->set = atlas7_gpio_set_value;
- chip->base = -1;
- /* Each chip can support 32 pins at one bank */
- chip->ngpio = NGPIO_OF_BANK * nbank;
- chip->label = kstrdup(np->name, GFP_KERNEL);
- chip->of_node = np;
- chip->of_gpio_n_cells = 2;
- chip->parent = &pdev->dev;
-
- girq = &chip->irq;
- girq->chip = &atlas7_gpio_irq_chip;
- girq->parent_handler = atlas7_gpio_handle_irq;
- girq->num_parents = nbank;
- girq->parents = devm_kcalloc(&pdev->dev, nbank,
- sizeof(*girq->parents),
- GFP_KERNEL);
- if (!girq->parents)
- return -ENOMEM;
- for (idx = 0; idx < nbank; idx++) {
- struct atlas7_gpio_bank *bank;
-
- bank = &a7gc->banks[idx];
- /* Set ctrl registers' base of this bank */
- bank->base = ATLAS7_GPIO_BASE(a7gc, idx);
- bank->gpio_offset = idx * NGPIO_OF_BANK;
-
- /* Get interrupt number from DTS */
- ret = of_irq_get(np, idx);
- if (ret <= 0) {
- dev_err(&pdev->dev,
- "Unable to find IRQ number. ret=%d\n", ret);
- if (!ret)
- ret = -ENXIO;
- goto failed;
- }
- bank->irq = ret;
- girq->parents[idx] = ret;
- }
- girq->default_type = IRQ_TYPE_NONE;
- girq->handler = handle_level_irq;
-
- /* Add gpio chip to system */
- ret = gpiochip_add_data(chip, a7gc);
- if (ret) {
- dev_err(&pdev->dev,
- "%pOF: error in probe function with status %d\n",
- np, ret);
- goto failed;
- }
-
- platform_set_drvdata(pdev, a7gc);
- dev_info(&pdev->dev, "add to system.\n");
- return 0;
-failed:
- return ret;
-}
-
-#ifdef CONFIG_PM_SLEEP
-static int atlas7_gpio_suspend_noirq(struct device *dev)
-{
- struct atlas7_gpio_chip *a7gc = dev_get_drvdata(dev);
- struct atlas7_gpio_bank *bank;
- void __iomem *ctrl_reg;
- u32 idx, pin;
-
- for (idx = 0; idx < a7gc->nbank; idx++) {
- bank = &a7gc->banks[idx];
- for (pin = 0; pin < bank->ngpio; pin++) {
- ctrl_reg = ATLAS7_GPIO_CTRL(bank, pin);
- bank->sleep_data[pin] = readl(ctrl_reg);
- }
- }
-
- return 0;
-}
-
-static int atlas7_gpio_resume_noirq(struct device *dev)
-{
- struct atlas7_gpio_chip *a7gc = dev_get_drvdata(dev);
- struct atlas7_gpio_bank *bank;
- void __iomem *ctrl_reg;
- u32 idx, pin;
-
- for (idx = 0; idx < a7gc->nbank; idx++) {
- bank = &a7gc->banks[idx];
- for (pin = 0; pin < bank->ngpio; pin++) {
- ctrl_reg = ATLAS7_GPIO_CTRL(bank, pin);
- writel(bank->sleep_data[pin], ctrl_reg);
- }
- }
-
- return 0;
-}
-
-static const struct dev_pm_ops atlas7_gpio_pm_ops = {
- .suspend_noirq = atlas7_gpio_suspend_noirq,
- .resume_noirq = atlas7_gpio_resume_noirq,
- .freeze_noirq = atlas7_gpio_suspend_noirq,
- .restore_noirq = atlas7_gpio_resume_noirq,
-};
-#endif
-
-static struct platform_driver atlas7_gpio_driver = {
- .driver = {
- .name = "atlas7-gpio",
- .of_match_table = atlas7_gpio_ids,
-#ifdef CONFIG_PM_SLEEP
- .pm = &atlas7_gpio_pm_ops,
-#endif
- },
- .probe = atlas7_gpio_probe,
-};
-
-static int __init atlas7_gpio_init(void)
-{
- return platform_driver_register(&atlas7_gpio_driver);
-}
-subsys_initcall(atlas7_gpio_init);
diff --git a/drivers/pinctrl/sirf/pinctrl-prima2.c b/drivers/pinctrl/sirf/pinctrl-prima2.c
deleted file mode 100644
index 49da2a7..0000000
--- a/drivers/pinctrl/sirf/pinctrl-prima2.c
+++ /dev/null
@@ -1,1131 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-/*
- * pinctrl pads, groups, functions for CSR SiRFprimaII
- *
- * Copyright (c) 2011 - 2014 Cambridge Silicon Radio Limited, a CSR plc group
- * company.
- */
-
-#include <linux/pinctrl/pinctrl.h>
-#include <linux/bitops.h>
-
-#include "pinctrl-sirf.h"
-
-/*
- * pad list for the pinmux subsystem
- * refer to CS-131858-DC-6A.xls
- */
-static const struct pinctrl_pin_desc sirfsoc_pads[] = {
- PINCTRL_PIN(0, "gpio0-0"),
- PINCTRL_PIN(1, "gpio0-1"),
- PINCTRL_PIN(2, "gpio0-2"),
- PINCTRL_PIN(3, "gpio0-3"),
- PINCTRL_PIN(4, "pwm0"),
- PINCTRL_PIN(5, "pwm1"),
- PINCTRL_PIN(6, "pwm2"),
- PINCTRL_PIN(7, "pwm3"),
- PINCTRL_PIN(8, "warm_rst_b"),
- PINCTRL_PIN(9, "odo_0"),
- PINCTRL_PIN(10, "odo_1"),
- PINCTRL_PIN(11, "dr_dir"),
- PINCTRL_PIN(12, "viprom_fa"),
- PINCTRL_PIN(13, "scl_1"),
- PINCTRL_PIN(14, "ntrst"),
- PINCTRL_PIN(15, "sda_1"),
- PINCTRL_PIN(16, "x_ldd[16]"),
- PINCTRL_PIN(17, "x_ldd[17]"),
- PINCTRL_PIN(18, "x_ldd[18]"),
- PINCTRL_PIN(19, "x_ldd[19]"),
- PINCTRL_PIN(20, "x_ldd[20]"),
- PINCTRL_PIN(21, "x_ldd[21]"),
- PINCTRL_PIN(22, "x_ldd[22]"),
- PINCTRL_PIN(23, "x_ldd[23], lcdrom_frdy"),
- PINCTRL_PIN(24, "gps_sgn"),
- PINCTRL_PIN(25, "gps_mag"),
- PINCTRL_PIN(26, "gps_clk"),
- PINCTRL_PIN(27, "sd_cd_b_1"),
- PINCTRL_PIN(28, "sd_vcc_on_1"),
- PINCTRL_PIN(29, "sd_wp_b_1"),
- PINCTRL_PIN(30, "sd_clk_3"),
- PINCTRL_PIN(31, "sd_cmd_3"),
-
- PINCTRL_PIN(32, "x_sd_dat_3[0]"),
- PINCTRL_PIN(33, "x_sd_dat_3[1]"),
- PINCTRL_PIN(34, "x_sd_dat_3[2]"),
- PINCTRL_PIN(35, "x_sd_dat_3[3]"),
- PINCTRL_PIN(36, "x_sd_clk_4"),
- PINCTRL_PIN(37, "x_sd_cmd_4"),
- PINCTRL_PIN(38, "x_sd_dat_4[0]"),
- PINCTRL_PIN(39, "x_sd_dat_4[1]"),
- PINCTRL_PIN(40, "x_sd_dat_4[2]"),
- PINCTRL_PIN(41, "x_sd_dat_4[3]"),
- PINCTRL_PIN(42, "x_cko_1"),
- PINCTRL_PIN(43, "x_ac97_bit_clk"),
- PINCTRL_PIN(44, "x_ac97_dout"),
- PINCTRL_PIN(45, "x_ac97_din"),
- PINCTRL_PIN(46, "x_ac97_sync"),
- PINCTRL_PIN(47, "x_txd_1"),
- PINCTRL_PIN(48, "x_txd_2"),
- PINCTRL_PIN(49, "x_rxd_1"),
- PINCTRL_PIN(50, "x_rxd_2"),
- PINCTRL_PIN(51, "x_usclk_0"),
- PINCTRL_PIN(52, "x_utxd_0"),
- PINCTRL_PIN(53, "x_urxd_0"),
- PINCTRL_PIN(54, "x_utfs_0"),
- PINCTRL_PIN(55, "x_urfs_0"),
- PINCTRL_PIN(56, "x_usclk_1"),
- PINCTRL_PIN(57, "x_utxd_1"),
- PINCTRL_PIN(58, "x_urxd_1"),
- PINCTRL_PIN(59, "x_utfs_1"),
- PINCTRL_PIN(60, "x_urfs_1"),
- PINCTRL_PIN(61, "x_usclk_2"),
- PINCTRL_PIN(62, "x_utxd_2"),
- PINCTRL_PIN(63, "x_urxd_2"),
-
- PINCTRL_PIN(64, "x_utfs_2"),
- PINCTRL_PIN(65, "x_urfs_2"),
- PINCTRL_PIN(66, "x_df_we_b"),
- PINCTRL_PIN(67, "x_df_re_b"),
- PINCTRL_PIN(68, "x_txd_0"),
- PINCTRL_PIN(69, "x_rxd_0"),
- PINCTRL_PIN(78, "x_cko_0"),
- PINCTRL_PIN(79, "x_vip_pxd[7]"),
- PINCTRL_PIN(80, "x_vip_pxd[6]"),
- PINCTRL_PIN(81, "x_vip_pxd[5]"),
- PINCTRL_PIN(82, "x_vip_pxd[4]"),
- PINCTRL_PIN(83, "x_vip_pxd[3]"),
- PINCTRL_PIN(84, "x_vip_pxd[2]"),
- PINCTRL_PIN(85, "x_vip_pxd[1]"),
- PINCTRL_PIN(86, "x_vip_pxd[0]"),
- PINCTRL_PIN(87, "x_vip_vsync"),
- PINCTRL_PIN(88, "x_vip_hsync"),
- PINCTRL_PIN(89, "x_vip_pxclk"),
- PINCTRL_PIN(90, "x_sda_0"),
- PINCTRL_PIN(91, "x_scl_0"),
- PINCTRL_PIN(92, "x_df_ry_by"),
- PINCTRL_PIN(93, "x_df_cs_b[1]"),
- PINCTRL_PIN(94, "x_df_cs_b[0]"),
- PINCTRL_PIN(95, "x_l_pclk"),
-
- PINCTRL_PIN(96, "x_l_lck"),
- PINCTRL_PIN(97, "x_l_fck"),
- PINCTRL_PIN(98, "x_l_de"),
- PINCTRL_PIN(99, "x_ldd[0]"),
- PINCTRL_PIN(100, "x_ldd[1]"),
- PINCTRL_PIN(101, "x_ldd[2]"),
- PINCTRL_PIN(102, "x_ldd[3]"),
- PINCTRL_PIN(103, "x_ldd[4]"),
- PINCTRL_PIN(104, "x_ldd[5]"),
- PINCTRL_PIN(105, "x_ldd[6]"),
- PINCTRL_PIN(106, "x_ldd[7]"),
- PINCTRL_PIN(107, "x_ldd[8]"),
- PINCTRL_PIN(108, "x_ldd[9]"),
- PINCTRL_PIN(109, "x_ldd[10]"),
- PINCTRL_PIN(110, "x_ldd[11]"),
- PINCTRL_PIN(111, "x_ldd[12]"),
- PINCTRL_PIN(112, "x_ldd[13]"),
- PINCTRL_PIN(113, "x_ldd[14]"),
- PINCTRL_PIN(114, "x_ldd[15]"),
-
- PINCTRL_PIN(115, "x_usb1_dp"),
- PINCTRL_PIN(116, "x_usb1_dn"),
-};
-
-static const struct sirfsoc_muxmask lcd_16bits_sirfsoc_muxmask[] = {
- {
- .group = 3,
- .mask = BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) |
- BIT(6) | BIT(7) | BIT(8) | BIT(9) | BIT(10) | BIT(11) |
- BIT(12) | BIT(13) | BIT(14) | BIT(15) | BIT(16) |
- BIT(17) | BIT(18),
- }, {
- .group = 2,
- .mask = BIT(31),
- },
-};
-
-static const struct sirfsoc_padmux lcd_16bits_padmux = {
- .muxmask_counts = ARRAY_SIZE(lcd_16bits_sirfsoc_muxmask),
- .muxmask = lcd_16bits_sirfsoc_muxmask,
- .ctrlreg = SIRFSOC_RSC_PIN_MUX,
- .funcmask = BIT(4),
- .funcval = 0,
-};
-
-static const unsigned lcd_16bits_pins[] = { 95, 96, 97, 98, 99, 100, 101, 102,
- 103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113, 114 };
-
-static const struct sirfsoc_muxmask lcd_18bits_muxmask[] = {
- {
- .group = 3,
- .mask = BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) |
- BIT(6) | BIT(7) | BIT(8) | BIT(9) | BIT(10) | BIT(11) |
- BIT(12) | BIT(13) | BIT(14) | BIT(15) | BIT(16) |
- BIT(17) | BIT(18),
- }, {
- .group = 2,
- .mask = BIT(31),
- }, {
- .group = 0,
- .mask = BIT(16) | BIT(17),
- },
-};
-
-static const struct sirfsoc_padmux lcd_18bits_padmux = {
- .muxmask_counts = ARRAY_SIZE(lcd_18bits_muxmask),
- .muxmask = lcd_18bits_muxmask,
- .ctrlreg = SIRFSOC_RSC_PIN_MUX,
- .funcmask = BIT(4),
- .funcval = 0,
-};
-
-static const unsigned lcd_18bits_pins[] = { 16, 17, 95, 96, 97, 98, 99, 100,
- 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113, 114};
-
-static const struct sirfsoc_muxmask lcd_24bits_muxmask[] = {
- {
- .group = 3,
- .mask = BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) |
- BIT(6) | BIT(7) | BIT(8) | BIT(9) | BIT(10) | BIT(11) |
- BIT(12) | BIT(13) | BIT(14) | BIT(15) | BIT(16) |
- BIT(17) | BIT(18),
- }, {
- .group = 2,
- .mask = BIT(31),
- }, {
- .group = 0,
- .mask = BIT(16) | BIT(17) | BIT(18) | BIT(19) | BIT(20) |
- BIT(21) | BIT(22) | BIT(23),
- },
-};
-
-static const struct sirfsoc_padmux lcd_24bits_padmux = {
- .muxmask_counts = ARRAY_SIZE(lcd_24bits_muxmask),
- .muxmask = lcd_24bits_muxmask,
- .ctrlreg = SIRFSOC_RSC_PIN_MUX,
- .funcmask = BIT(4),
- .funcval = 0,
-};
-
-static const unsigned lcd_24bits_pins[] = { 16, 17, 18, 19, 20, 21, 22, 23,
- 95, 96, 97, 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, 108, 109,
- 110, 111, 112, 113, 114 };
-
-static const struct sirfsoc_muxmask lcdrom_muxmask[] = {
- {
- .group = 3,
- .mask = BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) |
- BIT(6) | BIT(7) | BIT(8) | BIT(9) | BIT(10) | BIT(11) |
- BIT(12) | BIT(13) | BIT(14) | BIT(15) | BIT(16) |
- BIT(17) | BIT(18),
- }, {
- .group = 2,
- .mask = BIT(31),
- }, {
- .group = 0,
- .mask = BIT(23),
- },
-};
-
-static const struct sirfsoc_padmux lcdrom_padmux = {
- .muxmask_counts = ARRAY_SIZE(lcdrom_muxmask),
- .muxmask = lcdrom_muxmask,
- .ctrlreg = SIRFSOC_RSC_PIN_MUX,
- .funcmask = BIT(4),
- .funcval = BIT(4),
-};
-
-static const unsigned lcdrom_pins[] = { 23, 95, 96, 97, 98, 99, 100, 101, 102,
- 103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113, 114 };
-
-static const struct sirfsoc_muxmask uart0_muxmask[] = {
- {
- .group = 2,
- .mask = BIT(4) | BIT(5),
- }, {
- .group = 1,
- .mask = BIT(23) | BIT(28),
- },
-};
-
-static const struct sirfsoc_padmux uart0_padmux = {
- .muxmask_counts = ARRAY_SIZE(uart0_muxmask),
- .muxmask = uart0_muxmask,
- .ctrlreg = SIRFSOC_RSC_PIN_MUX,
- .funcmask = BIT(9),
- .funcval = BIT(9),
-};
-
-static const unsigned uart0_pins[] = { 55, 60, 68, 69 };
-
-static const struct sirfsoc_muxmask uart0_nostreamctrl_muxmask[] = {
- {
- .group = 2,
- .mask = BIT(4) | BIT(5),
- },
-};
-
-static const struct sirfsoc_padmux uart0_nostreamctrl_padmux = {
- .muxmask_counts = ARRAY_SIZE(uart0_nostreamctrl_muxmask),
- .muxmask = uart0_nostreamctrl_muxmask,
-};
-
-static const unsigned uart0_nostreamctrl_pins[] = { 68, 69 };
-
-static const struct sirfsoc_muxmask uart1_muxmask[] = {
- {
- .group = 1,
- .mask = BIT(15) | BIT(17),
- },
-};
-
-static const struct sirfsoc_padmux uart1_padmux = {
- .muxmask_counts = ARRAY_SIZE(uart1_muxmask),
- .muxmask = uart1_muxmask,
-};
-
-static const unsigned uart1_pins[] = { 47, 49 };
-
-static const struct sirfsoc_muxmask uart2_muxmask[] = {
- {
- .group = 1,
- .mask = BIT(16) | BIT(18) | BIT(24) | BIT(27),
- },
-};
-
-static const struct sirfsoc_padmux uart2_padmux = {
- .muxmask_counts = ARRAY_SIZE(uart2_muxmask),
- .muxmask = uart2_muxmask,
- .ctrlreg = SIRFSOC_RSC_PIN_MUX,
- .funcmask = BIT(10),
- .funcval = BIT(10),
-};
-
-static const unsigned uart2_pins[] = { 48, 50, 56, 59 };
-
-static const struct sirfsoc_muxmask uart2_nostreamctrl_muxmask[] = {
- {
- .group = 1,
- .mask = BIT(16) | BIT(18),
- },
-};
-
-static const struct sirfsoc_padmux uart2_nostreamctrl_padmux = {
- .muxmask_counts = ARRAY_SIZE(uart2_nostreamctrl_muxmask),
- .muxmask = uart2_nostreamctrl_muxmask,
-};
-
-static const unsigned uart2_nostreamctrl_pins[] = { 48, 50 };
-
-static const struct sirfsoc_muxmask sdmmc3_muxmask[] = {
- {
- .group = 0,
- .mask = BIT(30) | BIT(31),
- }, {
- .group = 1,
- .mask = BIT(0) | BIT(1) | BIT(2) | BIT(3),
- },
-};
-
-static const struct sirfsoc_padmux sdmmc3_padmux = {
- .muxmask_counts = ARRAY_SIZE(sdmmc3_muxmask),
- .muxmask = sdmmc3_muxmask,
- .ctrlreg = SIRFSOC_RSC_PIN_MUX,
- .funcmask = BIT(7),
- .funcval = 0,
-};
-
-static const unsigned sdmmc3_pins[] = { 30, 31, 32, 33, 34, 35 };
-
-static const struct sirfsoc_muxmask spi0_muxmask[] = {
- {
- .group = 1,
- .mask = BIT(0) | BIT(1) | BIT(2) | BIT(3),
- },
-};
-
-static const struct sirfsoc_padmux spi0_padmux = {
- .muxmask_counts = ARRAY_SIZE(spi0_muxmask),
- .muxmask = spi0_muxmask,
- .ctrlreg = SIRFSOC_RSC_PIN_MUX,
- .funcmask = BIT(7),
- .funcval = BIT(7),
-};
-
-static const unsigned spi0_pins[] = { 32, 33, 34, 35 };
-
-static const struct sirfsoc_muxmask sdmmc4_muxmask[] = {
- {
- .group = 1,
- .mask = BIT(4) | BIT(5) | BIT(6) | BIT(7) | BIT(8) | BIT(9),
- },
-};
-
-static const struct sirfsoc_padmux sdmmc4_padmux = {
- .muxmask_counts = ARRAY_SIZE(sdmmc4_muxmask),
- .muxmask = sdmmc4_muxmask,
-};
-
-static const unsigned sdmmc4_pins[] = { 36, 37, 38, 39, 40, 41 };
-
-static const struct sirfsoc_muxmask cko1_muxmask[] = {
- {
- .group = 1,
- .mask = BIT(10),
- },
-};
-
-static const struct sirfsoc_padmux cko1_padmux = {
- .muxmask_counts = ARRAY_SIZE(cko1_muxmask),
- .muxmask = cko1_muxmask,
- .ctrlreg = SIRFSOC_RSC_PIN_MUX,
- .funcmask = BIT(3),
- .funcval = 0,
-};
-
-static const unsigned cko1_pins[] = { 42 };
-
-static const struct sirfsoc_muxmask i2s_mclk_muxmask[] = {
- {
- .group = 1,
- .mask = BIT(10),
- },
-};
-
-static const struct sirfsoc_padmux i2s_mclk_padmux = {
- .muxmask_counts = ARRAY_SIZE(i2s_mclk_muxmask),
- .muxmask = i2s_mclk_muxmask,
- .ctrlreg = SIRFSOC_RSC_PIN_MUX,
- .funcmask = BIT(3),
- .funcval = BIT(3),
-};
-
-static const unsigned i2s_mclk_pins[] = { 42 };
-
-static const struct sirfsoc_muxmask i2s_ext_clk_input_muxmask[] = {
- {
- .group = 1,
- .mask = BIT(19),
- },
-};
-
-static const struct sirfsoc_padmux i2s_ext_clk_input_padmux = {
- .muxmask_counts = ARRAY_SIZE(i2s_ext_clk_input_muxmask),
- .muxmask = i2s_ext_clk_input_muxmask,
- .ctrlreg = SIRFSOC_RSC_PIN_MUX,
- .funcmask = BIT(2),
- .funcval = BIT(2),
-};
-
-static const unsigned i2s_ext_clk_input_pins[] = { 51 };
-
-static const struct sirfsoc_muxmask i2s_muxmask[] = {
- {
- .group = 1,
- .mask = BIT(11) | BIT(12) | BIT(13) | BIT(14),
- },
-};
-
-static const struct sirfsoc_padmux i2s_padmux = {
- .muxmask_counts = ARRAY_SIZE(i2s_muxmask),
- .muxmask = i2s_muxmask,
- .ctrlreg = SIRFSOC_RSC_PIN_MUX,
-};
-
-static const unsigned i2s_pins[] = { 43, 44, 45, 46 };
-
-static const struct sirfsoc_muxmask i2s_no_din_muxmask[] = {
- {
- .group = 1,
- .mask = BIT(11) | BIT(12) | BIT(14),
- },
-};
-
-static const struct sirfsoc_padmux i2s_no_din_padmux = {
- .muxmask_counts = ARRAY_SIZE(i2s_no_din_muxmask),
- .muxmask = i2s_no_din_muxmask,
- .ctrlreg = SIRFSOC_RSC_PIN_MUX,
-};
-
-static const unsigned i2s_no_din_pins[] = { 43, 44, 46 };
-
-static const struct sirfsoc_muxmask i2s_6chn_muxmask[] = {
- {
- .group = 1,
- .mask = BIT(11) | BIT(12) | BIT(13) | BIT(14)
- | BIT(23) | BIT(28),
- },
-};
-
-static const struct sirfsoc_padmux i2s_6chn_padmux = {
- .muxmask_counts = ARRAY_SIZE(i2s_6chn_muxmask),
- .muxmask = i2s_6chn_muxmask,
- .ctrlreg = SIRFSOC_RSC_PIN_MUX,
- .funcmask = BIT(1) | BIT(9),
- .funcval = BIT(1) | BIT(9),
-};
-
-static const unsigned i2s_6chn_pins[] = { 43, 44, 45, 46, 55, 60 };
-
-static const struct sirfsoc_muxmask ac97_muxmask[] = {
- {
- .group = 1,
- .mask = BIT(11) | BIT(12) | BIT(13) | BIT(14),
- },
-};
-
-static const struct sirfsoc_padmux ac97_padmux = {
- .muxmask_counts = ARRAY_SIZE(ac97_muxmask),
- .muxmask = ac97_muxmask,
- .ctrlreg = SIRFSOC_RSC_PIN_MUX,
- .funcmask = BIT(8),
- .funcval = 0,
-};
-
-static const unsigned ac97_pins[] = { 43, 44, 45, 46 };
-
-static const struct sirfsoc_muxmask spi1_muxmask[] = {
- {
- .group = 1,
- .mask = BIT(11) | BIT(12) | BIT(13) | BIT(14),
- },
-};
-
-static const struct sirfsoc_padmux spi1_padmux = {
- .muxmask_counts = ARRAY_SIZE(spi1_muxmask),
- .muxmask = spi1_muxmask,
- .ctrlreg = SIRFSOC_RSC_PIN_MUX,
- .funcmask = BIT(8),
- .funcval = BIT(8),
-};
-
-static const unsigned spi1_pins[] = { 43, 44, 45, 46 };
-
-static const struct sirfsoc_muxmask sdmmc1_muxmask[] = {
- {
- .group = 0,
- .mask = BIT(27) | BIT(28) | BIT(29),
- },
-};
-
-static const struct sirfsoc_padmux sdmmc1_padmux = {
- .muxmask_counts = ARRAY_SIZE(sdmmc1_muxmask),
- .muxmask = sdmmc1_muxmask,
-};
-
-static const unsigned sdmmc1_pins[] = { 27, 28, 29 };
-
-static const struct sirfsoc_muxmask gps_muxmask[] = {
- {
- .group = 0,
- .mask = BIT(24) | BIT(25) | BIT(26),
- },
-};
-
-static const struct sirfsoc_padmux gps_padmux = {
- .muxmask_counts = ARRAY_SIZE(gps_muxmask),
- .muxmask = gps_muxmask,
- .ctrlreg = SIRFSOC_RSC_PIN_MUX,
- .funcmask = BIT(12) | BIT(13) | BIT(14),
- .funcval = BIT(12),
-};
-
-static const unsigned gps_pins[] = { 24, 25, 26 };
-
-static const struct sirfsoc_muxmask sdmmc5_muxmask[] = {
- {
- .group = 0,
- .mask = BIT(24) | BIT(25) | BIT(26),
- },
-};
-
-static const struct sirfsoc_padmux sdmmc5_padmux = {
- .muxmask_counts = ARRAY_SIZE(sdmmc5_muxmask),
- .muxmask = sdmmc5_muxmask,
- .ctrlreg = SIRFSOC_RSC_PIN_MUX,
- .funcmask = BIT(13) | BIT(14),
- .funcval = BIT(13) | BIT(14),
-};
-
-static const unsigned sdmmc5_pins[] = { 24, 25, 26 };
-
-static const struct sirfsoc_muxmask usp0_muxmask[] = {
- {
- .group = 1,
- .mask = BIT(19) | BIT(20) | BIT(21) | BIT(22) | BIT(23),
- },
-};
-
-static const struct sirfsoc_padmux usp0_padmux = {
- .muxmask_counts = ARRAY_SIZE(usp0_muxmask),
- .muxmask = usp0_muxmask,
- .ctrlreg = SIRFSOC_RSC_PIN_MUX,
- .funcmask = BIT(1) | BIT(2) | BIT(6) | BIT(9),
- .funcval = 0,
-};
-
-static const unsigned usp0_pins[] = { 51, 52, 53, 54, 55 };
-
-static const struct sirfsoc_muxmask usp0_only_utfs_muxmask[] = {
- {
- .group = 1,
- .mask = BIT(19) | BIT(20) | BIT(21) | BIT(22),
- },
-};
-
-static const struct sirfsoc_padmux usp0_only_utfs_padmux = {
- .muxmask_counts = ARRAY_SIZE(usp0_only_utfs_muxmask),
- .muxmask = usp0_only_utfs_muxmask,
- .ctrlreg = SIRFSOC_RSC_PIN_MUX,
- .funcmask = BIT(1) | BIT(2) | BIT(6),
- .funcval = 0,
-};
-
-static const unsigned usp0_only_utfs_pins[] = { 51, 52, 53, 54 };
-
-static const struct sirfsoc_muxmask usp0_only_urfs_muxmask[] = {
- {
- .group = 1,
- .mask = BIT(19) | BIT(20) | BIT(21) | BIT(23),
- },
-};
-
-static const struct sirfsoc_padmux usp0_only_urfs_padmux = {
- .muxmask_counts = ARRAY_SIZE(usp0_only_urfs_muxmask),
- .muxmask = usp0_only_urfs_muxmask,
- .ctrlreg = SIRFSOC_RSC_PIN_MUX,
- .funcmask = BIT(1) | BIT(2) | BIT(9),
- .funcval = 0,
-};
-
-static const unsigned usp0_only_urfs_pins[] = { 51, 52, 53, 55 };
-
-static const struct sirfsoc_muxmask usp0_uart_nostreamctrl_muxmask[] = {
- {
- .group = 1,
- .mask = BIT(20) | BIT(21),
- },
-};
-
-static const struct sirfsoc_padmux usp0_uart_nostreamctrl_padmux = {
- .muxmask_counts = ARRAY_SIZE(usp0_uart_nostreamctrl_muxmask),
- .muxmask = usp0_uart_nostreamctrl_muxmask,
-};
-
-static const unsigned usp0_uart_nostreamctrl_pins[] = { 52, 53 };
-
-static const struct sirfsoc_muxmask usp1_muxmask[] = {
- {
- .group = 1,
- .mask = BIT(24) | BIT(25) | BIT(26) | BIT(27) | BIT(28),
- },
-};
-
-static const struct sirfsoc_padmux usp1_padmux = {
- .muxmask_counts = ARRAY_SIZE(usp1_muxmask),
- .muxmask = usp1_muxmask,
- .ctrlreg = SIRFSOC_RSC_PIN_MUX,
- .funcmask = BIT(1) | BIT(9) | BIT(10) | BIT(11),
- .funcval = 0,
-};
-
-static const unsigned usp1_pins[] = { 56, 57, 58, 59, 60 };
-
-static const struct sirfsoc_muxmask usp1_uart_nostreamctrl_muxmask[] = {
- {
- .group = 1,
- .mask = BIT(25) | BIT(26),
- },
-};
-
-static const struct sirfsoc_padmux usp1_uart_nostreamctrl_padmux = {
- .muxmask_counts = ARRAY_SIZE(usp1_uart_nostreamctrl_muxmask),
- .muxmask = usp1_uart_nostreamctrl_muxmask,
-};
-
-static const unsigned usp1_uart_nostreamctrl_pins[] = { 57, 58 };
-
-static const struct sirfsoc_muxmask usp2_muxmask[] = {
- {
- .group = 1,
- .mask = BIT(29) | BIT(30) | BIT(31),
- }, {
- .group = 2,
- .mask = BIT(0) | BIT(1),
- },
-};
-
-static const struct sirfsoc_padmux usp2_padmux = {
- .muxmask_counts = ARRAY_SIZE(usp2_muxmask),
- .muxmask = usp2_muxmask,
- .ctrlreg = SIRFSOC_RSC_PIN_MUX,
- .funcmask = BIT(13) | BIT(14),
- .funcval = 0,
-};
-
-static const unsigned usp2_pins[] = { 61, 62, 63, 64, 65 };
-
-static const struct sirfsoc_muxmask usp2_uart_nostreamctrl_muxmask[] = {
- {
- .group = 1,
- .mask = BIT(30) | BIT(31),
- },
-};
-
-static const struct sirfsoc_padmux usp2_uart_nostreamctrl_padmux = {
- .muxmask_counts = ARRAY_SIZE(usp2_uart_nostreamctrl_muxmask),
- .muxmask = usp2_uart_nostreamctrl_muxmask,
-};
-
-static const unsigned usp2_uart_nostreamctrl_pins[] = { 62, 63 };
-
-static const struct sirfsoc_muxmask nand_muxmask[] = {
- {
- .group = 2,
- .mask = BIT(2) | BIT(3) | BIT(28) | BIT(29) | BIT(30),
- },
-};
-
-static const struct sirfsoc_padmux nand_padmux = {
- .muxmask_counts = ARRAY_SIZE(nand_muxmask),
- .muxmask = nand_muxmask,
- .ctrlreg = SIRFSOC_RSC_PIN_MUX,
- .funcmask = BIT(5),
- .funcval = 0,
-};
-
-static const unsigned nand_pins[] = { 64, 65, 92, 93, 94 };
-
-static const struct sirfsoc_padmux sdmmc0_padmux = {
- .muxmask_counts = 0,
- .ctrlreg = SIRFSOC_RSC_PIN_MUX,
- .funcmask = BIT(5),
- .funcval = 0,
-};
-
-static const unsigned sdmmc0_pins[] = { };
-
-static const struct sirfsoc_muxmask sdmmc2_muxmask[] = {
- {
- .group = 2,
- .mask = BIT(2) | BIT(3),
- },
-};
-
-static const struct sirfsoc_padmux sdmmc2_padmux = {
- .muxmask_counts = ARRAY_SIZE(sdmmc2_muxmask),
- .muxmask = sdmmc2_muxmask,
- .ctrlreg = SIRFSOC_RSC_PIN_MUX,
- .funcmask = BIT(5),
- .funcval = BIT(5),
-};
-
-static const unsigned sdmmc2_pins[] = { 66, 67 };
-
-static const struct sirfsoc_muxmask cko0_muxmask[] = {
- {
- .group = 2,
- .mask = BIT(14),
- },
-};
-
-static const struct sirfsoc_padmux cko0_padmux = {
- .muxmask_counts = ARRAY_SIZE(cko0_muxmask),
- .muxmask = cko0_muxmask,
-};
-
-static const unsigned cko0_pins[] = { 78 };
-
-static const struct sirfsoc_muxmask vip_muxmask[] = {
- {
- .group = 2,
- .mask = BIT(15) | BIT(16) | BIT(17) | BIT(18) | BIT(19)
- | BIT(20) | BIT(21) | BIT(22) | BIT(23) | BIT(24) |
- BIT(25),
- },
-};
-
-static const struct sirfsoc_padmux vip_padmux = {
- .muxmask_counts = ARRAY_SIZE(vip_muxmask),
- .muxmask = vip_muxmask,
- .ctrlreg = SIRFSOC_RSC_PIN_MUX,
- .funcmask = BIT(0),
- .funcval = 0,
-};
-
-static const unsigned vip_pins[] = { 79, 80, 81, 82, 83, 84, 85, 86, 87,
- 88, 89 };
-
-static const struct sirfsoc_muxmask i2c0_muxmask[] = {
- {
- .group = 2,
- .mask = BIT(26) | BIT(27),
- },
-};
-
-static const struct sirfsoc_padmux i2c0_padmux = {
- .muxmask_counts = ARRAY_SIZE(i2c0_muxmask),
- .muxmask = i2c0_muxmask,
-};
-
-static const unsigned i2c0_pins[] = { 90, 91 };
-
-static const struct sirfsoc_muxmask i2c1_muxmask[] = {
- {
- .group = 0,
- .mask = BIT(13) | BIT(15),
- },
-};
-
-static const struct sirfsoc_padmux i2c1_padmux = {
- .muxmask_counts = ARRAY_SIZE(i2c1_muxmask),
- .muxmask = i2c1_muxmask,
-};
-
-static const unsigned i2c1_pins[] = { 13, 15 };
-
-static const struct sirfsoc_muxmask viprom_muxmask[] = {
- {
- .group = 2,
- .mask = BIT(15) | BIT(16) | BIT(17) | BIT(18) | BIT(19)
- | BIT(20) | BIT(21) | BIT(22) | BIT(23) | BIT(24) |
- BIT(25),
- }, {
- .group = 0,
- .mask = BIT(12),
- },
-};
-
-static const struct sirfsoc_padmux viprom_padmux = {
- .muxmask_counts = ARRAY_SIZE(viprom_muxmask),
- .muxmask = viprom_muxmask,
- .ctrlreg = SIRFSOC_RSC_PIN_MUX,
- .funcmask = BIT(0),
- .funcval = BIT(0),
-};
-
-static const unsigned viprom_pins[] = { 12, 79, 80, 81, 82, 83, 84, 85, 86,
- 87, 88, 89 };
-
-static const struct sirfsoc_muxmask pwm0_muxmask[] = {
- {
- .group = 0,
- .mask = BIT(4),
- },
-};
-
-static const struct sirfsoc_padmux pwm0_padmux = {
- .muxmask_counts = ARRAY_SIZE(pwm0_muxmask),
- .muxmask = pwm0_muxmask,
- .ctrlreg = SIRFSOC_RSC_PIN_MUX,
- .funcmask = BIT(12),
- .funcval = 0,
-};
-
-static const unsigned pwm0_pins[] = { 4 };
-
-static const struct sirfsoc_muxmask pwm1_muxmask[] = {
- {
- .group = 0,
- .mask = BIT(5),
- },
-};
-
-static const struct sirfsoc_padmux pwm1_padmux = {
- .muxmask_counts = ARRAY_SIZE(pwm1_muxmask),
- .muxmask = pwm1_muxmask,
-};
-
-static const unsigned pwm1_pins[] = { 5 };
-
-static const struct sirfsoc_muxmask pwm2_muxmask[] = {
- {
- .group = 0,
- .mask = BIT(6),
- },
-};
-
-static const struct sirfsoc_padmux pwm2_padmux = {
- .muxmask_counts = ARRAY_SIZE(pwm2_muxmask),
- .muxmask = pwm2_muxmask,
-};
-
-static const unsigned pwm2_pins[] = { 6 };
-
-static const struct sirfsoc_muxmask pwm3_muxmask[] = {
- {
- .group = 0,
- .mask = BIT(7),
- },
-};
-
-static const struct sirfsoc_padmux pwm3_padmux = {
- .muxmask_counts = ARRAY_SIZE(pwm3_muxmask),
- .muxmask = pwm3_muxmask,
-};
-
-static const unsigned pwm3_pins[] = { 7 };
-
-static const struct sirfsoc_muxmask warm_rst_muxmask[] = {
- {
- .group = 0,
- .mask = BIT(8),
- },
-};
-
-static const struct sirfsoc_padmux warm_rst_padmux = {
- .muxmask_counts = ARRAY_SIZE(warm_rst_muxmask),
- .muxmask = warm_rst_muxmask,
-};
-
-static const unsigned warm_rst_pins[] = { 8 };
-
-static const struct sirfsoc_muxmask usb0_utmi_drvbus_muxmask[] = {
- {
- .group = 1,
- .mask = BIT(22),
- },
-};
-static const struct sirfsoc_padmux usb0_utmi_drvbus_padmux = {
- .muxmask_counts = ARRAY_SIZE(usb0_utmi_drvbus_muxmask),
- .muxmask = usb0_utmi_drvbus_muxmask,
- .ctrlreg = SIRFSOC_RSC_PIN_MUX,
- .funcmask = BIT(6),
- .funcval = BIT(6), /* refer to PAD_UTMI_DRVVBUS0_ENABLE */
-};
-
-static const unsigned usb0_utmi_drvbus_pins[] = { 54 };
-
-static const struct sirfsoc_muxmask usb1_utmi_drvbus_muxmask[] = {
- {
- .group = 1,
- .mask = BIT(27),
- },
-};
-
-static const struct sirfsoc_padmux usb1_utmi_drvbus_padmux = {
- .muxmask_counts = ARRAY_SIZE(usb1_utmi_drvbus_muxmask),
- .muxmask = usb1_utmi_drvbus_muxmask,
- .ctrlreg = SIRFSOC_RSC_PIN_MUX,
- .funcmask = BIT(11),
- .funcval = BIT(11), /* refer to PAD_UTMI_DRVVBUS1_ENABLE */
-};
-
-static const unsigned usb1_utmi_drvbus_pins[] = { 59 };
-
-static const struct sirfsoc_padmux usb1_dp_dn_padmux = {
- .muxmask_counts = 0,
- .ctrlreg = SIRFSOC_RSC_USB_UART_SHARE,
- .funcmask = BIT(2),
- .funcval = BIT(2),
-};
-
-static const unsigned usb1_dp_dn_pins[] = { 115, 116 };
-
-static const struct sirfsoc_padmux uart1_route_io_usb1_padmux = {
- .muxmask_counts = 0,
- .ctrlreg = SIRFSOC_RSC_USB_UART_SHARE,
- .funcmask = BIT(2),
- .funcval = 0,
-};
-
-static const unsigned uart1_route_io_usb1_pins[] = { 115, 116 };
-
-static const struct sirfsoc_muxmask pulse_count_muxmask[] = {
- {
- .group = 0,
- .mask = BIT(9) | BIT(10) | BIT(11),
- },
-};
-
-static const struct sirfsoc_padmux pulse_count_padmux = {
- .muxmask_counts = ARRAY_SIZE(pulse_count_muxmask),
- .muxmask = pulse_count_muxmask,
-};
-
-static const unsigned pulse_count_pins[] = { 9, 10, 11 };
-
-static const struct sirfsoc_pin_group sirfsoc_pin_groups[] = {
- SIRFSOC_PIN_GROUP("lcd_16bitsgrp", lcd_16bits_pins),
- SIRFSOC_PIN_GROUP("lcd_18bitsgrp", lcd_18bits_pins),
- SIRFSOC_PIN_GROUP("lcd_24bitsgrp", lcd_24bits_pins),
- SIRFSOC_PIN_GROUP("lcdrom_grp", lcdrom_pins),
- SIRFSOC_PIN_GROUP("uart0grp", uart0_pins),
- SIRFSOC_PIN_GROUP("uart0_nostreamctrlgrp", uart0_nostreamctrl_pins),
- SIRFSOC_PIN_GROUP("uart1grp", uart1_pins),
- SIRFSOC_PIN_GROUP("uart2grp", uart2_pins),
- SIRFSOC_PIN_GROUP("uart2_nostreamctrlgrp", uart2_nostreamctrl_pins),
- SIRFSOC_PIN_GROUP("usp0grp", usp0_pins),
- SIRFSOC_PIN_GROUP("usp0_uart_nostreamctrl_grp",
- usp0_uart_nostreamctrl_pins),
- SIRFSOC_PIN_GROUP("usp0_only_utfs_grp", usp0_only_utfs_pins),
- SIRFSOC_PIN_GROUP("usp0_only_urfs_grp", usp0_only_urfs_pins),
- SIRFSOC_PIN_GROUP("usp1grp", usp1_pins),
- SIRFSOC_PIN_GROUP("usp1_uart_nostreamctrl_grp",
- usp1_uart_nostreamctrl_pins),
- SIRFSOC_PIN_GROUP("usp2grp", usp2_pins),
- SIRFSOC_PIN_GROUP("usp2_uart_nostreamctrl_grp",
- usp2_uart_nostreamctrl_pins),
- SIRFSOC_PIN_GROUP("i2c0grp", i2c0_pins),
- SIRFSOC_PIN_GROUP("i2c1grp", i2c1_pins),
- SIRFSOC_PIN_GROUP("pwm0grp", pwm0_pins),
- SIRFSOC_PIN_GROUP("pwm1grp", pwm1_pins),
- SIRFSOC_PIN_GROUP("pwm2grp", pwm2_pins),
- SIRFSOC_PIN_GROUP("pwm3grp", pwm3_pins),
- SIRFSOC_PIN_GROUP("vipgrp", vip_pins),
- SIRFSOC_PIN_GROUP("vipromgrp", viprom_pins),
- SIRFSOC_PIN_GROUP("warm_rstgrp", warm_rst_pins),
- SIRFSOC_PIN_GROUP("cko0grp", cko0_pins),
- SIRFSOC_PIN_GROUP("cko1grp", cko1_pins),
- SIRFSOC_PIN_GROUP("sdmmc0grp", sdmmc0_pins),
- SIRFSOC_PIN_GROUP("sdmmc1grp", sdmmc1_pins),
- SIRFSOC_PIN_GROUP("sdmmc2grp", sdmmc2_pins),
- SIRFSOC_PIN_GROUP("sdmmc3grp", sdmmc3_pins),
- SIRFSOC_PIN_GROUP("sdmmc4grp", sdmmc4_pins),
- SIRFSOC_PIN_GROUP("sdmmc5grp", sdmmc5_pins),
- SIRFSOC_PIN_GROUP("usb0_utmi_drvbusgrp", usb0_utmi_drvbus_pins),
- SIRFSOC_PIN_GROUP("usb1_utmi_drvbusgrp", usb1_utmi_drvbus_pins),
- SIRFSOC_PIN_GROUP("usb1_dp_dngrp", usb1_dp_dn_pins),
- SIRFSOC_PIN_GROUP("uart1_route_io_usb1grp", uart1_route_io_usb1_pins),
- SIRFSOC_PIN_GROUP("pulse_countgrp", pulse_count_pins),
- SIRFSOC_PIN_GROUP("i2smclkgrp", i2s_mclk_pins),
- SIRFSOC_PIN_GROUP("i2s_ext_clk_inputgrp", i2s_ext_clk_input_pins),
- SIRFSOC_PIN_GROUP("i2sgrp", i2s_pins),
- SIRFSOC_PIN_GROUP("i2s_no_dingrp", i2s_no_din_pins),
- SIRFSOC_PIN_GROUP("i2s_6chngrp", i2s_6chn_pins),
- SIRFSOC_PIN_GROUP("ac97grp", ac97_pins),
- SIRFSOC_PIN_GROUP("nandgrp", nand_pins),
- SIRFSOC_PIN_GROUP("spi0grp", spi0_pins),
- SIRFSOC_PIN_GROUP("spi1grp", spi1_pins),
- SIRFSOC_PIN_GROUP("gpsgrp", gps_pins),
-};
-
-static const char * const lcd_16bitsgrp[] = { "lcd_16bitsgrp" };
-static const char * const lcd_18bitsgrp[] = { "lcd_18bitsgrp" };
-static const char * const lcd_24bitsgrp[] = { "lcd_24bitsgrp" };
-static const char * const lcdromgrp[] = { "lcdromgrp" };
-static const char * const uart0grp[] = { "uart0grp" };
-static const char * const uart0_nostreamctrlgrp[] = { "uart0_nostreamctrlgrp" };
-static const char * const uart1grp[] = { "uart1grp" };
-static const char * const uart2grp[] = { "uart2grp" };
-static const char * const uart2_nostreamctrlgrp[] = { "uart2_nostreamctrlgrp" };
-static const char * const usp0grp[] = { "usp0grp" };
-static const char * const usp0_uart_nostreamctrl_grp[] = {
- "usp0_uart_nostreamctrl_grp"
-};
-static const char * const usp0_only_utfs_grp[] = { "usp0_only_utfs_grp" };
-static const char * const usp0_only_urfs_grp[] = { "usp0_only_urfs_grp" };
-static const char * const usp1grp[] = { "usp1grp" };
-static const char * const usp1_uart_nostreamctrl_grp[] = {
- "usp1_uart_nostreamctrl_grp"
-};
-static const char * const usp2grp[] = { "usp2grp" };
-static const char * const usp2_uart_nostreamctrl_grp[] = {
- "usp2_uart_nostreamctrl_grp"
-};
-static const char * const i2c0grp[] = { "i2c0grp" };
-static const char * const i2c1grp[] = { "i2c1grp" };
-static const char * const pwm0grp[] = { "pwm0grp" };
-static const char * const pwm1grp[] = { "pwm1grp" };
-static const char * const pwm2grp[] = { "pwm2grp" };
-static const char * const pwm3grp[] = { "pwm3grp" };
-static const char * const vipgrp[] = { "vipgrp" };
-static const char * const vipromgrp[] = { "vipromgrp" };
-static const char * const warm_rstgrp[] = { "warm_rstgrp" };
-static const char * const cko0grp[] = { "cko0grp" };
-static const char * const cko1grp[] = { "cko1grp" };
-static const char * const sdmmc0grp[] = { "sdmmc0grp" };
-static const char * const sdmmc1grp[] = { "sdmmc1grp" };
-static const char * const sdmmc2grp[] = { "sdmmc2grp" };
-static const char * const sdmmc3grp[] = { "sdmmc3grp" };
-static const char * const sdmmc4grp[] = { "sdmmc4grp" };
-static const char * const sdmmc5grp[] = { "sdmmc5grp" };
-static const char * const usb0_utmi_drvbusgrp[] = { "usb0_utmi_drvbusgrp" };
-static const char * const usb1_utmi_drvbusgrp[] = { "usb1_utmi_drvbusgrp" };
-static const char * const usb1_dp_dngrp[] = { "usb1_dp_dngrp" };
-static const char * const
- uart1_route_io_usb1grp[] = { "uart1_route_io_usb1grp" };
-static const char * const pulse_countgrp[] = { "pulse_countgrp" };
-static const char * const i2smclkgrp[] = { "i2smclkgrp" };
-static const char * const i2s_ext_clk_inputgrp[] = { "i2s_ext_clk_inputgrp" };
-static const char * const i2sgrp[] = { "i2sgrp" };
-static const char * const i2s_no_dingrp[] = { "i2s_no_dingrp" };
-static const char * const i2s_6chngrp[] = { "i2s_6chngrp" };
-static const char * const ac97grp[] = { "ac97grp" };
-static const char * const nandgrp[] = { "nandgrp" };
-static const char * const spi0grp[] = { "spi0grp" };
-static const char * const spi1grp[] = { "spi1grp" };
-static const char * const gpsgrp[] = { "gpsgrp" };
-
-static const struct sirfsoc_pmx_func sirfsoc_pmx_functions[] = {
- SIRFSOC_PMX_FUNCTION("lcd_16bits", lcd_16bitsgrp, lcd_16bits_padmux),
- SIRFSOC_PMX_FUNCTION("lcd_18bits", lcd_18bitsgrp, lcd_18bits_padmux),
- SIRFSOC_PMX_FUNCTION("lcd_24bits", lcd_24bitsgrp, lcd_24bits_padmux),
- SIRFSOC_PMX_FUNCTION("lcdrom", lcdromgrp, lcdrom_padmux),
- SIRFSOC_PMX_FUNCTION("uart0", uart0grp, uart0_padmux),
- SIRFSOC_PMX_FUNCTION("uart0_nostreamctrl",
- uart0_nostreamctrlgrp, uart0_nostreamctrl_padmux),
- SIRFSOC_PMX_FUNCTION("uart1", uart1grp, uart1_padmux),
- SIRFSOC_PMX_FUNCTION("uart2", uart2grp, uart2_padmux),
- SIRFSOC_PMX_FUNCTION("uart2_nostreamctrl",
- uart2_nostreamctrlgrp, uart2_nostreamctrl_padmux),
- SIRFSOC_PMX_FUNCTION("usp0", usp0grp, usp0_padmux),
- SIRFSOC_PMX_FUNCTION("usp0_uart_nostreamctrl",
- usp0_uart_nostreamctrl_grp, usp0_uart_nostreamctrl_padmux),
- SIRFSOC_PMX_FUNCTION("usp0_only_utfs",
- usp0_only_utfs_grp, usp0_only_utfs_padmux),
- SIRFSOC_PMX_FUNCTION("usp0_only_urfs",
- usp0_only_urfs_grp, usp0_only_urfs_padmux),
- SIRFSOC_PMX_FUNCTION("usp1", usp1grp, usp1_padmux),
- SIRFSOC_PMX_FUNCTION("usp1_uart_nostreamctrl",
- usp1_uart_nostreamctrl_grp, usp1_uart_nostreamctrl_padmux),
- SIRFSOC_PMX_FUNCTION("usp2", usp2grp, usp2_padmux),
- SIRFSOC_PMX_FUNCTION("usp2_uart_nostreamctrl",
- usp2_uart_nostreamctrl_grp, usp2_uart_nostreamctrl_padmux),
- SIRFSOC_PMX_FUNCTION("i2c0", i2c0grp, i2c0_padmux),
- SIRFSOC_PMX_FUNCTION("i2c1", i2c1grp, i2c1_padmux),
- SIRFSOC_PMX_FUNCTION("pwm0", pwm0grp, pwm0_padmux),
- SIRFSOC_PMX_FUNCTION("pwm1", pwm1grp, pwm1_padmux),
- SIRFSOC_PMX_FUNCTION("pwm2", pwm2grp, pwm2_padmux),
- SIRFSOC_PMX_FUNCTION("pwm3", pwm3grp, pwm3_padmux),
- SIRFSOC_PMX_FUNCTION("vip", vipgrp, vip_padmux),
- SIRFSOC_PMX_FUNCTION("viprom", vipromgrp, viprom_padmux),
- SIRFSOC_PMX_FUNCTION("warm_rst", warm_rstgrp, warm_rst_padmux),
- SIRFSOC_PMX_FUNCTION("cko0", cko0grp, cko0_padmux),
- SIRFSOC_PMX_FUNCTION("cko1", cko1grp, cko1_padmux),
- SIRFSOC_PMX_FUNCTION("sdmmc0", sdmmc0grp, sdmmc0_padmux),
- SIRFSOC_PMX_FUNCTION("sdmmc1", sdmmc1grp, sdmmc1_padmux),
- SIRFSOC_PMX_FUNCTION("sdmmc2", sdmmc2grp, sdmmc2_padmux),
- SIRFSOC_PMX_FUNCTION("sdmmc3", sdmmc3grp, sdmmc3_padmux),
- SIRFSOC_PMX_FUNCTION("sdmmc4", sdmmc4grp, sdmmc4_padmux),
- SIRFSOC_PMX_FUNCTION("sdmmc5", sdmmc5grp, sdmmc5_padmux),
- SIRFSOC_PMX_FUNCTION("usb0_utmi_drvbus",
- usb0_utmi_drvbusgrp, usb0_utmi_drvbus_padmux),
- SIRFSOC_PMX_FUNCTION("usb1_utmi_drvbus",
- usb1_utmi_drvbusgrp, usb1_utmi_drvbus_padmux),
- SIRFSOC_PMX_FUNCTION("usb1_dp_dn", usb1_dp_dngrp, usb1_dp_dn_padmux),
- SIRFSOC_PMX_FUNCTION("uart1_route_io_usb1",
- uart1_route_io_usb1grp, uart1_route_io_usb1_padmux),
- SIRFSOC_PMX_FUNCTION("pulse_count", pulse_countgrp, pulse_count_padmux),
- SIRFSOC_PMX_FUNCTION("i2s_mclk", i2smclkgrp, i2s_mclk_padmux),
- SIRFSOC_PMX_FUNCTION("i2s_ext_clk_input", i2s_ext_clk_inputgrp,
- i2s_ext_clk_input_padmux),
- SIRFSOC_PMX_FUNCTION("i2s", i2sgrp, i2s_padmux),
- SIRFSOC_PMX_FUNCTION("i2s_no_din", i2s_no_dingrp, i2s_no_din_padmux),
- SIRFSOC_PMX_FUNCTION("i2s_6chn", i2s_6chngrp, i2s_6chn_padmux),
- SIRFSOC_PMX_FUNCTION("ac97", ac97grp, ac97_padmux),
- SIRFSOC_PMX_FUNCTION("nand", nandgrp, nand_padmux),
- SIRFSOC_PMX_FUNCTION("spi0", spi0grp, spi0_padmux),
- SIRFSOC_PMX_FUNCTION("spi1", spi1grp, spi1_padmux),
- SIRFSOC_PMX_FUNCTION("gps", gpsgrp, gps_padmux),
-};
-
-struct sirfsoc_pinctrl_data prima2_pinctrl_data = {
- (struct pinctrl_pin_desc *)sirfsoc_pads,
- ARRAY_SIZE(sirfsoc_pads),
- (struct sirfsoc_pin_group *)sirfsoc_pin_groups,
- ARRAY_SIZE(sirfsoc_pin_groups),
- (struct sirfsoc_pmx_func *)sirfsoc_pmx_functions,
- ARRAY_SIZE(sirfsoc_pmx_functions),
-};
-
diff --git a/drivers/pinctrl/sirf/pinctrl-sirf.c b/drivers/pinctrl/sirf/pinctrl-sirf.c
deleted file mode 100644
index 63a287d..0000000
--- a/drivers/pinctrl/sirf/pinctrl-sirf.c
+++ /dev/null
@@ -1,894 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-/*
- * pinmux driver for CSR SiRFprimaII
- *
- * Authors:
- * Rongjun Ying <rongjun.ying@csr.com>
- * Yuping Luo <yuping.luo@csr.com>
- * Barry Song <baohua.song@csr.com>
- *
- * Copyright (c) 2011 - 2014 Cambridge Silicon Radio Limited, a CSR plc group
- * company.
- */
-
-#include <linux/init.h>
-#include <linux/irq.h>
-#include <linux/platform_device.h>
-#include <linux/io.h>
-#include <linux/slab.h>
-#include <linux/err.h>
-#include <linux/pinctrl/pinctrl.h>
-#include <linux/pinctrl/pinmux.h>
-#include <linux/pinctrl/consumer.h>
-#include <linux/pinctrl/machine.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-#include <linux/of_device.h>
-#include <linux/of_platform.h>
-#include <linux/bitops.h>
-#include <linux/gpio/driver.h>
-#include <linux/of_gpio.h>
-
-#include "pinctrl-sirf.h"
-
-#define DRIVER_NAME "pinmux-sirf"
-
-struct sirfsoc_gpio_bank {
- int id;
- int parent_irq;
- spinlock_t lock;
-};
-
-struct sirfsoc_gpio_chip {
- struct of_mm_gpio_chip chip;
- struct sirfsoc_gpio_bank sgpio_bank[SIRFSOC_GPIO_NO_OF_BANKS];
- spinlock_t lock;
-};
-
-static struct sirfsoc_pin_group *sirfsoc_pin_groups;
-static int sirfsoc_pingrp_cnt;
-
-static int sirfsoc_get_groups_count(struct pinctrl_dev *pctldev)
-{
- return sirfsoc_pingrp_cnt;
-}
-
-static const char *sirfsoc_get_group_name(struct pinctrl_dev *pctldev,
- unsigned selector)
-{
- return sirfsoc_pin_groups[selector].name;
-}
-
-static int sirfsoc_get_group_pins(struct pinctrl_dev *pctldev,
- unsigned selector,
- const unsigned **pins,
- unsigned *num_pins)
-{
- *pins = sirfsoc_pin_groups[selector].pins;
- *num_pins = sirfsoc_pin_groups[selector].num_pins;
- return 0;
-}
-
-static void sirfsoc_pin_dbg_show(struct pinctrl_dev *pctldev,
- struct seq_file *s, unsigned offset)
-{
- seq_printf(s, " " DRIVER_NAME);
-}
-
-static int sirfsoc_dt_node_to_map(struct pinctrl_dev *pctldev,
- struct device_node *np_config,
- struct pinctrl_map **map, unsigned *num_maps)
-{
- struct sirfsoc_pmx *spmx = pinctrl_dev_get_drvdata(pctldev);
- struct device_node *np;
- struct property *prop;
- const char *function, *group;
- int ret, index = 0, count = 0;
-
- /* calculate number of maps required */
- for_each_child_of_node(np_config, np) {
- ret = of_property_read_string(np, "sirf,function", &function);
- if (ret < 0) {
- of_node_put(np);
- return ret;
- }
-
- ret = of_property_count_strings(np, "sirf,pins");
- if (ret < 0) {
- of_node_put(np);
- return ret;
- }
-
- count += ret;
- }
-
- if (!count) {
- dev_err(spmx->dev, "No child nodes passed via DT\n");
- return -ENODEV;
- }
-
- *map = kcalloc(count, sizeof(**map), GFP_KERNEL);
- if (!*map)
- return -ENOMEM;
-
- for_each_child_of_node(np_config, np) {
- of_property_read_string(np, "sirf,function", &function);
- of_property_for_each_string(np, "sirf,pins", prop, group) {
- (*map)[index].type = PIN_MAP_TYPE_MUX_GROUP;
- (*map)[index].data.mux.group = group;
- (*map)[index].data.mux.function = function;
- index++;
- }
- }
-
- *num_maps = count;
-
- return 0;
-}
-
-static void sirfsoc_dt_free_map(struct pinctrl_dev *pctldev,
- struct pinctrl_map *map, unsigned num_maps)
-{
- kfree(map);
-}
-
-static const struct pinctrl_ops sirfsoc_pctrl_ops = {
- .get_groups_count = sirfsoc_get_groups_count,
- .get_group_name = sirfsoc_get_group_name,
- .get_group_pins = sirfsoc_get_group_pins,
- .pin_dbg_show = sirfsoc_pin_dbg_show,
- .dt_node_to_map = sirfsoc_dt_node_to_map,
- .dt_free_map = sirfsoc_dt_free_map,
-};
-
-static struct sirfsoc_pmx_func *sirfsoc_pmx_functions;
-static int sirfsoc_pmxfunc_cnt;
-
-static void sirfsoc_pinmux_endisable(struct sirfsoc_pmx *spmx,
- unsigned selector, bool enable)
-{
- int i;
- const struct sirfsoc_padmux *mux =
- sirfsoc_pmx_functions[selector].padmux;
- const struct sirfsoc_muxmask *mask = mux->muxmask;
-
- for (i = 0; i < mux->muxmask_counts; i++) {
- u32 muxval;
- muxval = readl(spmx->gpio_virtbase +
- SIRFSOC_GPIO_PAD_EN(mask[i].group));
- if (enable)
- muxval = muxval & ~mask[i].mask;
- else
- muxval = muxval | mask[i].mask;
- writel(muxval, spmx->gpio_virtbase +
- SIRFSOC_GPIO_PAD_EN(mask[i].group));
- }
-
- if (mux->funcmask && enable) {
- u32 func_en_val;
-
- func_en_val =
- readl(spmx->rsc_virtbase + mux->ctrlreg);
- func_en_val =
- (func_en_val & ~mux->funcmask) | (mux->funcval);
- writel(func_en_val, spmx->rsc_virtbase + mux->ctrlreg);
- }
-}
-
-static int sirfsoc_pinmux_set_mux(struct pinctrl_dev *pmxdev,
- unsigned selector,
- unsigned group)
-{
- struct sirfsoc_pmx *spmx;
-
- spmx = pinctrl_dev_get_drvdata(pmxdev);
- sirfsoc_pinmux_endisable(spmx, selector, true);
-
- return 0;
-}
-
-static int sirfsoc_pinmux_get_funcs_count(struct pinctrl_dev *pmxdev)
-{
- return sirfsoc_pmxfunc_cnt;
-}
-
-static const char *sirfsoc_pinmux_get_func_name(struct pinctrl_dev *pctldev,
- unsigned selector)
-{
- return sirfsoc_pmx_functions[selector].name;
-}
-
-static int sirfsoc_pinmux_get_groups(struct pinctrl_dev *pctldev,
- unsigned selector,
- const char * const **groups,
- unsigned * const num_groups)
-{
- *groups = sirfsoc_pmx_functions[selector].groups;
- *num_groups = sirfsoc_pmx_functions[selector].num_groups;
- return 0;
-}
-
-static int sirfsoc_pinmux_request_gpio(struct pinctrl_dev *pmxdev,
- struct pinctrl_gpio_range *range, unsigned offset)
-{
- struct sirfsoc_pmx *spmx;
-
- int group = range->id;
-
- u32 muxval;
-
- spmx = pinctrl_dev_get_drvdata(pmxdev);
-
- muxval = readl(spmx->gpio_virtbase +
- SIRFSOC_GPIO_PAD_EN(group));
- muxval = muxval | (1 << (offset - range->pin_base));
- writel(muxval, spmx->gpio_virtbase +
- SIRFSOC_GPIO_PAD_EN(group));
-
- return 0;
-}
-
-static const struct pinmux_ops sirfsoc_pinmux_ops = {
- .set_mux = sirfsoc_pinmux_set_mux,
- .get_functions_count = sirfsoc_pinmux_get_funcs_count,
- .get_function_name = sirfsoc_pinmux_get_func_name,
- .get_function_groups = sirfsoc_pinmux_get_groups,
- .gpio_request_enable = sirfsoc_pinmux_request_gpio,
-};
-
-static struct pinctrl_desc sirfsoc_pinmux_desc = {
- .name = DRIVER_NAME,
- .pctlops = &sirfsoc_pctrl_ops,
- .pmxops = &sirfsoc_pinmux_ops,
- .owner = THIS_MODULE,
-};
-
-static void __iomem *sirfsoc_rsc_of_iomap(void)
-{
- const struct of_device_id rsc_ids[] = {
- { .compatible = "sirf,prima2-rsc" },
- {}
- };
- struct device_node *np;
-
- np = of_find_matching_node(NULL, rsc_ids);
- if (!np)
- panic("unable to find compatible rsc node in dtb\n");
-
- return of_iomap(np, 0);
-}
-
-static int sirfsoc_gpio_of_xlate(struct gpio_chip *gc,
- const struct of_phandle_args *gpiospec,
- u32 *flags)
-{
- if (gpiospec->args[0] > SIRFSOC_GPIO_NO_OF_BANKS * SIRFSOC_GPIO_BANK_SIZE)
- return -EINVAL;
-
- if (flags)
- *flags = gpiospec->args[1];
-
- return gpiospec->args[0];
-}
-
-static const struct of_device_id pinmux_ids[] = {
- { .compatible = "sirf,prima2-pinctrl", .data = &prima2_pinctrl_data, },
- { .compatible = "sirf,atlas6-pinctrl", .data = &atlas6_pinctrl_data, },
- {}
-};
-
-static int sirfsoc_pinmux_probe(struct platform_device *pdev)
-{
- int ret;
- struct sirfsoc_pmx *spmx;
- struct device_node *np = pdev->dev.of_node;
- const struct sirfsoc_pinctrl_data *pdata;
-
- /* Create state holders etc for this driver */
- spmx = devm_kzalloc(&pdev->dev, sizeof(*spmx), GFP_KERNEL);
- if (!spmx)
- return -ENOMEM;
-
- spmx->dev = &pdev->dev;
-
- platform_set_drvdata(pdev, spmx);
-
- spmx->gpio_virtbase = of_iomap(np, 0);
- if (!spmx->gpio_virtbase) {
- dev_err(&pdev->dev, "can't map gpio registers\n");
- return -ENOMEM;
- }
-
- spmx->rsc_virtbase = sirfsoc_rsc_of_iomap();
- if (!spmx->rsc_virtbase) {
- ret = -ENOMEM;
- dev_err(&pdev->dev, "can't map rsc registers\n");
- goto out_no_rsc_remap;
- }
-
- pdata = of_match_node(pinmux_ids, np)->data;
- sirfsoc_pin_groups = pdata->grps;
- sirfsoc_pingrp_cnt = pdata->grps_cnt;
- sirfsoc_pmx_functions = pdata->funcs;
- sirfsoc_pmxfunc_cnt = pdata->funcs_cnt;
- sirfsoc_pinmux_desc.pins = pdata->pads;
- sirfsoc_pinmux_desc.npins = pdata->pads_cnt;
-
-
- /* Now register the pin controller and all pins it handles */
- spmx->pmx = pinctrl_register(&sirfsoc_pinmux_desc, &pdev->dev, spmx);
- if (IS_ERR(spmx->pmx)) {
- dev_err(&pdev->dev, "could not register SIRFSOC pinmux driver\n");
- ret = PTR_ERR(spmx->pmx);
- goto out_no_pmx;
- }
-
- dev_info(&pdev->dev, "initialized SIRFSOC pinmux driver\n");
-
- return 0;
-
-out_no_pmx:
- iounmap(spmx->rsc_virtbase);
-out_no_rsc_remap:
- iounmap(spmx->gpio_virtbase);
- return ret;
-}
-
-#ifdef CONFIG_PM_SLEEP
-static int sirfsoc_pinmux_suspend_noirq(struct device *dev)
-{
- int i, j;
- struct sirfsoc_pmx *spmx = dev_get_drvdata(dev);
-
- for (i = 0; i < SIRFSOC_GPIO_NO_OF_BANKS; i++) {
- for (j = 0; j < SIRFSOC_GPIO_BANK_SIZE; j++) {
- spmx->gpio_regs[i][j] = readl(spmx->gpio_virtbase +
- SIRFSOC_GPIO_CTRL(i, j));
- }
- spmx->ints_regs[i] = readl(spmx->gpio_virtbase +
- SIRFSOC_GPIO_INT_STATUS(i));
- spmx->paden_regs[i] = readl(spmx->gpio_virtbase +
- SIRFSOC_GPIO_PAD_EN(i));
- }
- spmx->dspen_regs = readl(spmx->gpio_virtbase + SIRFSOC_GPIO_DSP_EN0);
-
- for (i = 0; i < 3; i++)
- spmx->rsc_regs[i] = readl(spmx->rsc_virtbase + 4 * i);
-
- return 0;
-}
-
-static int sirfsoc_pinmux_resume_noirq(struct device *dev)
-{
- int i, j;
- struct sirfsoc_pmx *spmx = dev_get_drvdata(dev);
-
- for (i = 0; i < SIRFSOC_GPIO_NO_OF_BANKS; i++) {
- for (j = 0; j < SIRFSOC_GPIO_BANK_SIZE; j++) {
- writel(spmx->gpio_regs[i][j], spmx->gpio_virtbase +
- SIRFSOC_GPIO_CTRL(i, j));
- }
- writel(spmx->ints_regs[i], spmx->gpio_virtbase +
- SIRFSOC_GPIO_INT_STATUS(i));
- writel(spmx->paden_regs[i], spmx->gpio_virtbase +
- SIRFSOC_GPIO_PAD_EN(i));
- }
- writel(spmx->dspen_regs, spmx->gpio_virtbase + SIRFSOC_GPIO_DSP_EN0);
-
- for (i = 0; i < 3; i++)
- writel(spmx->rsc_regs[i], spmx->rsc_virtbase + 4 * i);
-
- return 0;
-}
-
-static const struct dev_pm_ops sirfsoc_pinmux_pm_ops = {
- .suspend_noirq = sirfsoc_pinmux_suspend_noirq,
- .resume_noirq = sirfsoc_pinmux_resume_noirq,
- .freeze_noirq = sirfsoc_pinmux_suspend_noirq,
- .restore_noirq = sirfsoc_pinmux_resume_noirq,
-};
-#endif
-
-static struct platform_driver sirfsoc_pinmux_driver = {
- .driver = {
- .name = DRIVER_NAME,
- .of_match_table = pinmux_ids,
-#ifdef CONFIG_PM_SLEEP
- .pm = &sirfsoc_pinmux_pm_ops,
-#endif
- },
- .probe = sirfsoc_pinmux_probe,
-};
-
-static int __init sirfsoc_pinmux_init(void)
-{
- return platform_driver_register(&sirfsoc_pinmux_driver);
-}
-arch_initcall(sirfsoc_pinmux_init);
-
-static inline struct sirfsoc_gpio_bank *
-sirfsoc_gpio_to_bank(struct sirfsoc_gpio_chip *sgpio, unsigned int offset)
-{
- return &sgpio->sgpio_bank[offset / SIRFSOC_GPIO_BANK_SIZE];
-}
-
-static inline int sirfsoc_gpio_to_bankoff(unsigned int offset)
-{
- return offset % SIRFSOC_GPIO_BANK_SIZE;
-}
-
-static void sirfsoc_gpio_irq_ack(struct irq_data *d)
-{
- struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
- struct sirfsoc_gpio_chip *sgpio = gpiochip_get_data(gc);
- struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, d->hwirq);
- int idx = sirfsoc_gpio_to_bankoff(d->hwirq);
- u32 val, offset;
- unsigned long flags;
-
- offset = SIRFSOC_GPIO_CTRL(bank->id, idx);
-
- spin_lock_irqsave(&sgpio->lock, flags);
-
- val = readl(sgpio->chip.regs + offset);
-
- writel(val, sgpio->chip.regs + offset);
-
- spin_unlock_irqrestore(&sgpio->lock, flags);
-}
-
-static void __sirfsoc_gpio_irq_mask(struct sirfsoc_gpio_chip *sgpio,
- struct sirfsoc_gpio_bank *bank,
- int idx)
-{
- u32 val, offset;
- unsigned long flags;
-
- offset = SIRFSOC_GPIO_CTRL(bank->id, idx);
-
- spin_lock_irqsave(&sgpio->lock, flags);
-
- val = readl(sgpio->chip.regs + offset);
- val &= ~SIRFSOC_GPIO_CTL_INTR_EN_MASK;
- val &= ~SIRFSOC_GPIO_CTL_INTR_STS_MASK;
- writel(val, sgpio->chip.regs + offset);
-
- spin_unlock_irqrestore(&sgpio->lock, flags);
-}
-
-static void sirfsoc_gpio_irq_mask(struct irq_data *d)
-{
- struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
- struct sirfsoc_gpio_chip *sgpio = gpiochip_get_data(gc);
- struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, d->hwirq);
-
- __sirfsoc_gpio_irq_mask(sgpio, bank, d->hwirq % SIRFSOC_GPIO_BANK_SIZE);
-}
-
-static void sirfsoc_gpio_irq_unmask(struct irq_data *d)
-{
- struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
- struct sirfsoc_gpio_chip *sgpio = gpiochip_get_data(gc);
- struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, d->hwirq);
- int idx = sirfsoc_gpio_to_bankoff(d->hwirq);
- u32 val, offset;
- unsigned long flags;
-
- offset = SIRFSOC_GPIO_CTRL(bank->id, idx);
-
- spin_lock_irqsave(&sgpio->lock, flags);
-
- val = readl(sgpio->chip.regs + offset);
- val &= ~SIRFSOC_GPIO_CTL_INTR_STS_MASK;
- val |= SIRFSOC_GPIO_CTL_INTR_EN_MASK;
- writel(val, sgpio->chip.regs + offset);
-
- spin_unlock_irqrestore(&sgpio->lock, flags);
-}
-
-static int sirfsoc_gpio_irq_type(struct irq_data *d, unsigned type)
-{
- struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
- struct sirfsoc_gpio_chip *sgpio = gpiochip_get_data(gc);
- struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, d->hwirq);
- int idx = sirfsoc_gpio_to_bankoff(d->hwirq);
- u32 val, offset;
- unsigned long flags;
-
- offset = SIRFSOC_GPIO_CTRL(bank->id, idx);
-
- spin_lock_irqsave(&sgpio->lock, flags);
-
- val = readl(sgpio->chip.regs + offset);
- val &= ~(SIRFSOC_GPIO_CTL_INTR_STS_MASK | SIRFSOC_GPIO_CTL_OUT_EN_MASK);
-
- switch (type) {
- case IRQ_TYPE_NONE:
- break;
- case IRQ_TYPE_EDGE_RISING:
- val |= SIRFSOC_GPIO_CTL_INTR_HIGH_MASK |
- SIRFSOC_GPIO_CTL_INTR_TYPE_MASK;
- val &= ~SIRFSOC_GPIO_CTL_INTR_LOW_MASK;
- break;
- case IRQ_TYPE_EDGE_FALLING:
- val &= ~SIRFSOC_GPIO_CTL_INTR_HIGH_MASK;
- val |= SIRFSOC_GPIO_CTL_INTR_LOW_MASK |
- SIRFSOC_GPIO_CTL_INTR_TYPE_MASK;
- break;
- case IRQ_TYPE_EDGE_BOTH:
- val |= SIRFSOC_GPIO_CTL_INTR_HIGH_MASK |
- SIRFSOC_GPIO_CTL_INTR_LOW_MASK |
- SIRFSOC_GPIO_CTL_INTR_TYPE_MASK;
- break;
- case IRQ_TYPE_LEVEL_LOW:
- val &= ~(SIRFSOC_GPIO_CTL_INTR_HIGH_MASK |
- SIRFSOC_GPIO_CTL_INTR_TYPE_MASK);
- val |= SIRFSOC_GPIO_CTL_INTR_LOW_MASK;
- break;
- case IRQ_TYPE_LEVEL_HIGH:
- val |= SIRFSOC_GPIO_CTL_INTR_HIGH_MASK;
- val &= ~(SIRFSOC_GPIO_CTL_INTR_LOW_MASK |
- SIRFSOC_GPIO_CTL_INTR_TYPE_MASK);
- break;
- }
-
- writel(val, sgpio->chip.regs + offset);
-
- spin_unlock_irqrestore(&sgpio->lock, flags);
-
- return 0;
-}
-
-static struct irq_chip sirfsoc_irq_chip = {
- .name = "sirf-gpio-irq",
- .irq_ack = sirfsoc_gpio_irq_ack,
- .irq_mask = sirfsoc_gpio_irq_mask,
- .irq_unmask = sirfsoc_gpio_irq_unmask,
- .irq_set_type = sirfsoc_gpio_irq_type,
-};
-
-static void sirfsoc_gpio_handle_irq(struct irq_desc *desc)
-{
- unsigned int irq = irq_desc_get_irq(desc);
- struct gpio_chip *gc = irq_desc_get_handler_data(desc);
- struct sirfsoc_gpio_chip *sgpio = gpiochip_get_data(gc);
- struct sirfsoc_gpio_bank *bank;
- u32 status, ctrl;
- int idx = 0;
- struct irq_chip *chip = irq_desc_get_chip(desc);
- int i;
-
- for (i = 0; i < SIRFSOC_GPIO_NO_OF_BANKS; i++) {
- bank = &sgpio->sgpio_bank[i];
- if (bank->parent_irq == irq)
- break;
- }
- BUG_ON(i == SIRFSOC_GPIO_NO_OF_BANKS);
-
- chained_irq_enter(chip, desc);
-
- status = readl(sgpio->chip.regs + SIRFSOC_GPIO_INT_STATUS(bank->id));
- if (!status) {
- printk(KERN_WARNING
- "%s: gpio id %d status %#x no interrupt is flagged\n",
- __func__, bank->id, status);
- handle_bad_irq(desc);
- return;
- }
-
- while (status) {
- ctrl = readl(sgpio->chip.regs + SIRFSOC_GPIO_CTRL(bank->id, idx));
-
- /*
- * Here we must check whether the corresponding GPIO's interrupt
- * has been enabled, otherwise just skip it
- */
- if ((status & 0x1) && (ctrl & SIRFSOC_GPIO_CTL_INTR_EN_MASK)) {
- pr_debug("%s: gpio id %d idx %d happens\n",
- __func__, bank->id, idx);
- generic_handle_irq(irq_find_mapping(gc->irq.domain, idx +
- bank->id * SIRFSOC_GPIO_BANK_SIZE));
- }
-
- idx++;
- status = status >> 1;
- }
-
- chained_irq_exit(chip, desc);
-}
-
-static inline void sirfsoc_gpio_set_input(struct sirfsoc_gpio_chip *sgpio,
- unsigned ctrl_offset)
-{
- u32 val;
-
- val = readl(sgpio->chip.regs + ctrl_offset);
- val &= ~SIRFSOC_GPIO_CTL_OUT_EN_MASK;
- writel(val, sgpio->chip.regs + ctrl_offset);
-}
-
-static int sirfsoc_gpio_request(struct gpio_chip *chip, unsigned offset)
-{
- struct sirfsoc_gpio_chip *sgpio = gpiochip_get_data(chip);
- struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, offset);
- unsigned long flags;
-
- if (pinctrl_gpio_request(chip->base + offset))
- return -ENODEV;
-
- spin_lock_irqsave(&bank->lock, flags);
-
- /*
- * default status:
- * set direction as input and mask irq
- */
- sirfsoc_gpio_set_input(sgpio, SIRFSOC_GPIO_CTRL(bank->id, offset));
- __sirfsoc_gpio_irq_mask(sgpio, bank, offset);
-
- spin_unlock_irqrestore(&bank->lock, flags);
-
- return 0;
-}
-
-static void sirfsoc_gpio_free(struct gpio_chip *chip, unsigned offset)
-{
- struct sirfsoc_gpio_chip *sgpio = gpiochip_get_data(chip);
- struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, offset);
- unsigned long flags;
-
- spin_lock_irqsave(&bank->lock, flags);
-
- __sirfsoc_gpio_irq_mask(sgpio, bank, offset);
- sirfsoc_gpio_set_input(sgpio, SIRFSOC_GPIO_CTRL(bank->id, offset));
-
- spin_unlock_irqrestore(&bank->lock, flags);
-
- pinctrl_gpio_free(chip->base + offset);
-}
-
-static int sirfsoc_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
-{
- struct sirfsoc_gpio_chip *sgpio = gpiochip_get_data(chip);
- struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, gpio);
- int idx = sirfsoc_gpio_to_bankoff(gpio);
- unsigned long flags;
- unsigned offset;
-
- offset = SIRFSOC_GPIO_CTRL(bank->id, idx);
-
- spin_lock_irqsave(&bank->lock, flags);
-
- sirfsoc_gpio_set_input(sgpio, offset);
-
- spin_unlock_irqrestore(&bank->lock, flags);
-
- return 0;
-}
-
-static inline void sirfsoc_gpio_set_output(struct sirfsoc_gpio_chip *sgpio,
- struct sirfsoc_gpio_bank *bank,
- unsigned offset,
- int value)
-{
- u32 out_ctrl;
- unsigned long flags;
-
- spin_lock_irqsave(&bank->lock, flags);
-
- out_ctrl = readl(sgpio->chip.regs + offset);
- if (value)
- out_ctrl |= SIRFSOC_GPIO_CTL_DATAOUT_MASK;
- else
- out_ctrl &= ~SIRFSOC_GPIO_CTL_DATAOUT_MASK;
-
- out_ctrl &= ~SIRFSOC_GPIO_CTL_INTR_EN_MASK;
- out_ctrl |= SIRFSOC_GPIO_CTL_OUT_EN_MASK;
- writel(out_ctrl, sgpio->chip.regs + offset);
-
- spin_unlock_irqrestore(&bank->lock, flags);
-}
-
-static int sirfsoc_gpio_direction_output(struct gpio_chip *chip,
- unsigned gpio, int value)
-{
- struct sirfsoc_gpio_chip *sgpio = gpiochip_get_data(chip);
- struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, gpio);
- int idx = sirfsoc_gpio_to_bankoff(gpio);
- u32 offset;
- unsigned long flags;
-
- offset = SIRFSOC_GPIO_CTRL(bank->id, idx);
-
- spin_lock_irqsave(&sgpio->lock, flags);
-
- sirfsoc_gpio_set_output(sgpio, bank, offset, value);
-
- spin_unlock_irqrestore(&sgpio->lock, flags);
-
- return 0;
-}
-
-static int sirfsoc_gpio_get_value(struct gpio_chip *chip, unsigned offset)
-{
- struct sirfsoc_gpio_chip *sgpio = gpiochip_get_data(chip);
- struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, offset);
- u32 val;
- unsigned long flags;
-
- spin_lock_irqsave(&bank->lock, flags);
-
- val = readl(sgpio->chip.regs + SIRFSOC_GPIO_CTRL(bank->id, offset));
-
- spin_unlock_irqrestore(&bank->lock, flags);
-
- return !!(val & SIRFSOC_GPIO_CTL_DATAIN_MASK);
-}
-
-static void sirfsoc_gpio_set_value(struct gpio_chip *chip, unsigned offset,
- int value)
-{
- struct sirfsoc_gpio_chip *sgpio = gpiochip_get_data(chip);
- struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, offset);
- u32 ctrl;
- unsigned long flags;
-
- spin_lock_irqsave(&bank->lock, flags);
-
- ctrl = readl(sgpio->chip.regs + SIRFSOC_GPIO_CTRL(bank->id, offset));
- if (value)
- ctrl |= SIRFSOC_GPIO_CTL_DATAOUT_MASK;
- else
- ctrl &= ~SIRFSOC_GPIO_CTL_DATAOUT_MASK;
- writel(ctrl, sgpio->chip.regs + SIRFSOC_GPIO_CTRL(bank->id, offset));
-
- spin_unlock_irqrestore(&bank->lock, flags);
-}
-
-static void sirfsoc_gpio_set_pullup(struct sirfsoc_gpio_chip *sgpio,
- const u32 *pullups)
-{
- int i, n;
- const unsigned long *p = (const unsigned long *)pullups;
-
- for (i = 0; i < SIRFSOC_GPIO_NO_OF_BANKS; i++) {
- for_each_set_bit(n, p + i, BITS_PER_LONG) {
- u32 offset = SIRFSOC_GPIO_CTRL(i, n);
- u32 val = readl(sgpio->chip.regs + offset);
- val |= SIRFSOC_GPIO_CTL_PULL_MASK;
- val |= SIRFSOC_GPIO_CTL_PULL_HIGH;
- writel(val, sgpio->chip.regs + offset);
- }
- }
-}
-
-static void sirfsoc_gpio_set_pulldown(struct sirfsoc_gpio_chip *sgpio,
- const u32 *pulldowns)
-{
- int i, n;
- const unsigned long *p = (const unsigned long *)pulldowns;
-
- for (i = 0; i < SIRFSOC_GPIO_NO_OF_BANKS; i++) {
- for_each_set_bit(n, p + i, BITS_PER_LONG) {
- u32 offset = SIRFSOC_GPIO_CTRL(i, n);
- u32 val = readl(sgpio->chip.regs + offset);
- val |= SIRFSOC_GPIO_CTL_PULL_MASK;
- val &= ~SIRFSOC_GPIO_CTL_PULL_HIGH;
- writel(val, sgpio->chip.regs + offset);
- }
- }
-}
-
-static int sirfsoc_gpio_probe(struct device_node *np)
-{
- int i, err = 0;
- struct sirfsoc_gpio_chip *sgpio;
- struct sirfsoc_gpio_bank *bank;
- void __iomem *regs;
- struct platform_device *pdev;
- struct gpio_irq_chip *girq;
-
- u32 pullups[SIRFSOC_GPIO_NO_OF_BANKS], pulldowns[SIRFSOC_GPIO_NO_OF_BANKS];
-
- pdev = of_find_device_by_node(np);
- if (!pdev)
- return -ENODEV;
-
- sgpio = devm_kzalloc(&pdev->dev, sizeof(*sgpio), GFP_KERNEL);
- if (!sgpio) {
- err = -ENOMEM;
- goto out_put_device;
- }
- spin_lock_init(&sgpio->lock);
-
- regs = of_iomap(np, 0);
- if (!regs) {
- err = -ENOMEM;
- goto out_put_device;
- }
-
- sgpio->chip.gc.request = sirfsoc_gpio_request;
- sgpio->chip.gc.free = sirfsoc_gpio_free;
- sgpio->chip.gc.direction_input = sirfsoc_gpio_direction_input;
- sgpio->chip.gc.get = sirfsoc_gpio_get_value;
- sgpio->chip.gc.direction_output = sirfsoc_gpio_direction_output;
- sgpio->chip.gc.set = sirfsoc_gpio_set_value;
- sgpio->chip.gc.base = 0;
- sgpio->chip.gc.ngpio = SIRFSOC_GPIO_BANK_SIZE * SIRFSOC_GPIO_NO_OF_BANKS;
- sgpio->chip.gc.label = kasprintf(GFP_KERNEL, "%pOF", np);
- sgpio->chip.gc.of_node = np;
- sgpio->chip.gc.of_xlate = sirfsoc_gpio_of_xlate;
- sgpio->chip.gc.of_gpio_n_cells = 2;
- sgpio->chip.gc.parent = &pdev->dev;
- sgpio->chip.regs = regs;
-
- girq = &sgpio->chip.gc.irq;
- girq->chip = &sirfsoc_irq_chip;
- girq->parent_handler = sirfsoc_gpio_handle_irq;
- girq->num_parents = SIRFSOC_GPIO_NO_OF_BANKS;
- girq->parents = devm_kcalloc(&pdev->dev, SIRFSOC_GPIO_NO_OF_BANKS,
- sizeof(*girq->parents),
- GFP_KERNEL);
- if (!girq->parents) {
- err = -ENOMEM;
- goto out_put_device;
- }
- for (i = 0; i < SIRFSOC_GPIO_NO_OF_BANKS; i++) {
- bank = &sgpio->sgpio_bank[i];
- spin_lock_init(&bank->lock);
- bank->parent_irq = platform_get_irq(pdev, i);
- if (bank->parent_irq < 0) {
- err = bank->parent_irq;
- goto out;
- }
- girq->parents[i] = bank->parent_irq;
- }
- girq->default_type = IRQ_TYPE_NONE;
- girq->handler = handle_level_irq;
-
- err = gpiochip_add_data(&sgpio->chip.gc, sgpio);
- if (err) {
- dev_err(&pdev->dev, "%pOF: error in probe function with status %d\n",
- np, err);
- goto out;
- }
-
- err = gpiochip_add_pin_range(&sgpio->chip.gc, dev_name(&pdev->dev),
- 0, 0, SIRFSOC_GPIO_BANK_SIZE * SIRFSOC_GPIO_NO_OF_BANKS);
- if (err) {
- dev_err(&pdev->dev,
- "could not add gpiochip pin range\n");
- goto out_no_range;
- }
-
- if (!of_property_read_u32_array(np, "sirf,pullups", pullups,
- SIRFSOC_GPIO_NO_OF_BANKS))
- sirfsoc_gpio_set_pullup(sgpio, pullups);
-
- if (!of_property_read_u32_array(np, "sirf,pulldowns", pulldowns,
- SIRFSOC_GPIO_NO_OF_BANKS))
- sirfsoc_gpio_set_pulldown(sgpio, pulldowns);
-
- return 0;
-
-out_no_range:
- gpiochip_remove(&sgpio->chip.gc);
-out:
- iounmap(regs);
-out_put_device:
- put_device(&pdev->dev);
- return err;
-}
-
-static int __init sirfsoc_gpio_init(void)
-{
-
- struct device_node *np;
-
- np = of_find_matching_node(NULL, pinmux_ids);
-
- if (!np)
- return -ENODEV;
-
- return sirfsoc_gpio_probe(np);
-}
-subsys_initcall(sirfsoc_gpio_init);
diff --git a/drivers/pinctrl/sirf/pinctrl-sirf.h b/drivers/pinctrl/sirf/pinctrl-sirf.h
deleted file mode 100644
index d7125b8..0000000
--- a/drivers/pinctrl/sirf/pinctrl-sirf.h
+++ /dev/null
@@ -1,116 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-/*
- * pinmux driver shared headfile for CSR SiRFsoc
- *
- * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
- */
-
-#ifndef __PINMUX_SIRF_H__
-#define __PINMUX_SIRF_H__
-
-#define SIRFSOC_NUM_PADS 622
-#define SIRFSOC_RSC_USB_UART_SHARE 0
-#define SIRFSOC_RSC_PIN_MUX 0x4
-
-#define SIRFSOC_GPIO_PAD_EN(g) ((g)*0x100 + 0x84)
-#define SIRFSOC_GPIO_PAD_EN_CLR(g) ((g)*0x100 + 0x90)
-#define SIRFSOC_GPIO_CTRL(g, i) ((g)*0x100 + (i)*4)
-#define SIRFSOC_GPIO_DSP_EN0 (0x80)
-#define SIRFSOC_GPIO_INT_STATUS(g) ((g)*0x100 + 0x8C)
-
-#define SIRFSOC_GPIO_CTL_INTR_LOW_MASK 0x1
-#define SIRFSOC_GPIO_CTL_INTR_HIGH_MASK 0x2
-#define SIRFSOC_GPIO_CTL_INTR_TYPE_MASK 0x4
-#define SIRFSOC_GPIO_CTL_INTR_EN_MASK 0x8
-#define SIRFSOC_GPIO_CTL_INTR_STS_MASK 0x10
-#define SIRFSOC_GPIO_CTL_OUT_EN_MASK 0x20
-#define SIRFSOC_GPIO_CTL_DATAOUT_MASK 0x40
-#define SIRFSOC_GPIO_CTL_DATAIN_MASK 0x80
-#define SIRFSOC_GPIO_CTL_PULL_MASK 0x100
-#define SIRFSOC_GPIO_CTL_PULL_HIGH 0x200
-#define SIRFSOC_GPIO_CTL_DSP_INT 0x400
-
-#define SIRFSOC_GPIO_NO_OF_BANKS 5
-#define SIRFSOC_GPIO_BANK_SIZE 32
-#define SIRFSOC_GPIO_NUM(bank, index) (((bank)*(32)) + (index))
-
-/**
- * @dev: a pointer back to containing device
- * @virtbase: the offset to the controller in virtual memory
- */
-struct sirfsoc_pmx {
- struct device *dev;
- struct pinctrl_dev *pmx;
- void __iomem *gpio_virtbase;
- void __iomem *rsc_virtbase;
- u32 gpio_regs[SIRFSOC_GPIO_NO_OF_BANKS][SIRFSOC_GPIO_BANK_SIZE];
- u32 ints_regs[SIRFSOC_GPIO_NO_OF_BANKS];
- u32 paden_regs[SIRFSOC_GPIO_NO_OF_BANKS];
- u32 dspen_regs;
- u32 rsc_regs[3];
-};
-
-/* SIRFSOC_GPIO_PAD_EN set */
-struct sirfsoc_muxmask {
- unsigned long group;
- unsigned long mask;
-};
-
-struct sirfsoc_padmux {
- unsigned long muxmask_counts;
- const struct sirfsoc_muxmask *muxmask;
- /* RSC_PIN_MUX set */
- unsigned long ctrlreg;
- unsigned long funcmask;
- unsigned long funcval;
-};
-
- /**
- * struct sirfsoc_pin_group - describes a SiRFprimaII pin group
- * @name: the name of this specific pin group
- * @pins: an array of discrete physical pins used in this group, taken
- * from the driver-local pin enumeration space
- * @num_pins: the number of pins in this group array, i.e. the number of
- * elements in .pins so we can iterate over that array
- */
-struct sirfsoc_pin_group {
- const char *name;
- const unsigned int *pins;
- const unsigned num_pins;
-};
-
-#define SIRFSOC_PIN_GROUP(n, p) \
- { \
- .name = n, \
- .pins = p, \
- .num_pins = ARRAY_SIZE(p), \
- }
-
-struct sirfsoc_pmx_func {
- const char *name;
- const char * const *groups;
- const unsigned num_groups;
- const struct sirfsoc_padmux *padmux;
-};
-
-#define SIRFSOC_PMX_FUNCTION(n, g, m) \
- { \
- .name = n, \
- .groups = g, \
- .num_groups = ARRAY_SIZE(g), \
- .padmux = &m, \
- }
-
-struct sirfsoc_pinctrl_data {
- struct pinctrl_pin_desc *pads;
- int pads_cnt;
- struct sirfsoc_pin_group *grps;
- int grps_cnt;
- struct sirfsoc_pmx_func *funcs;
- int funcs_cnt;
-};
-
-extern struct sirfsoc_pinctrl_data prima2_pinctrl_data;
-extern struct sirfsoc_pinctrl_data atlas6_pinctrl_data;
-
-#endif
diff --git a/drivers/pinctrl/sprd/pinctrl-sprd.c b/drivers/pinctrl/sprd/pinctrl-sprd.c
index 08dc193..dca7a50 100644
--- a/drivers/pinctrl/sprd/pinctrl-sprd.c
+++ b/drivers/pinctrl/sprd/pinctrl-sprd.c
@@ -687,7 +687,7 @@
shift = INPUT_SCHMITT_SHIFT;
break;
case PIN_CONFIG_BIAS_PULL_UP:
- if (is_sleep_config == true) {
+ if (is_sleep_config) {
val |= SLEEP_PULL_UP;
mask = SLEEP_PULL_UP_MASK;
shift = SLEEP_PULL_UP_SHIFT;
diff --git a/drivers/pinctrl/sunxi/Kconfig b/drivers/pinctrl/sunxi/Kconfig
index 5932935..33751a6 100644
--- a/drivers/pinctrl/sunxi/Kconfig
+++ b/drivers/pinctrl/sunxi/Kconfig
@@ -119,4 +119,14 @@
default ARM64 && ARCH_SUNXI
select PINCTRL_SUNXI
+config PINCTRL_SUN50I_H616
+ bool "Support for the Allwinner H616 PIO"
+ default ARM64 && ARCH_SUNXI
+ select PINCTRL_SUNXI
+
+config PINCTRL_SUN50I_H616_R
+ bool "Support for the Allwinner H616 R-PIO"
+ default ARM64 && ARCH_SUNXI
+ select PINCTRL_SUNXI
+
endif
diff --git a/drivers/pinctrl/sunxi/Makefile b/drivers/pinctrl/sunxi/Makefile
index 8b7ff0d..d3440c4 100644
--- a/drivers/pinctrl/sunxi/Makefile
+++ b/drivers/pinctrl/sunxi/Makefile
@@ -23,5 +23,7 @@
obj-$(CONFIG_PINCTRL_SUN50I_H5) += pinctrl-sun50i-h5.o
obj-$(CONFIG_PINCTRL_SUN50I_H6) += pinctrl-sun50i-h6.o
obj-$(CONFIG_PINCTRL_SUN50I_H6_R) += pinctrl-sun50i-h6-r.o
+obj-$(CONFIG_PINCTRL_SUN50I_H616) += pinctrl-sun50i-h616.o
+obj-$(CONFIG_PINCTRL_SUN50I_H616_R) += pinctrl-sun50i-h616-r.o
obj-$(CONFIG_PINCTRL_SUN9I_A80) += pinctrl-sun9i-a80.o
obj-$(CONFIG_PINCTRL_SUN9I_A80_R) += pinctrl-sun9i-a80-r.o
diff --git a/drivers/pinctrl/sunxi/pinctrl-sun50i-h6-r.c b/drivers/pinctrl/sunxi/pinctrl-sun50i-h6-r.c
index 4557e18..c7d90c4 100644
--- a/drivers/pinctrl/sunxi/pinctrl-sun50i-h6-r.c
+++ b/drivers/pinctrl/sunxi/pinctrl-sun50i-h6-r.c
@@ -24,11 +24,13 @@
SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 0),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "s_rsb"), /* SCK */
SUNXI_FUNCTION(0x3, "s_i2c"), /* SCK */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)), /* PL_EINT0 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 1),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "s_rsb"), /* SDA */
SUNXI_FUNCTION(0x3, "s_i2c"), /* SDA */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 1)), /* PL_EINT1 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 2),
diff --git a/drivers/pinctrl/sunxi/pinctrl-sun50i-h616-r.c b/drivers/pinctrl/sunxi/pinctrl-sun50i-h616-r.c
new file mode 100644
index 0000000..8e4f10a
--- /dev/null
+++ b/drivers/pinctrl/sunxi/pinctrl-sun50i-h616-r.c
@@ -0,0 +1,56 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Allwinner H616 R_PIO pin controller driver
+ *
+ * Copyright (C) 2020 Arm Ltd.
+ * Based on former work, which is:
+ * Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>
+ */
+
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/pinctrl/pinctrl.h>
+#include <linux/reset.h>
+
+#include "pinctrl-sunxi.h"
+
+static const struct sunxi_desc_pin sun50i_h616_r_pins[] = {
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 0),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "s_rsb"), /* SCK */
+ SUNXI_FUNCTION(0x3, "s_i2c")), /* SCK */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 1),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "s_rsb"), /* SDA */
+ SUNXI_FUNCTION(0x3, "s_i2c")), /* SDA */
+};
+
+static const struct sunxi_pinctrl_desc sun50i_h616_r_pinctrl_data = {
+ .pins = sun50i_h616_r_pins,
+ .npins = ARRAY_SIZE(sun50i_h616_r_pins),
+ .pin_base = PL_BASE,
+};
+
+static int sun50i_h616_r_pinctrl_probe(struct platform_device *pdev)
+{
+ return sunxi_pinctrl_init(pdev,
+ &sun50i_h616_r_pinctrl_data);
+}
+
+static const struct of_device_id sun50i_h616_r_pinctrl_match[] = {
+ { .compatible = "allwinner,sun50i-h616-r-pinctrl", },
+ {}
+};
+
+static struct platform_driver sun50i_h616_r_pinctrl_driver = {
+ .probe = sun50i_h616_r_pinctrl_probe,
+ .driver = {
+ .name = "sun50i-h616-r-pinctrl",
+ .of_match_table = sun50i_h616_r_pinctrl_match,
+ },
+};
+builtin_platform_driver(sun50i_h616_r_pinctrl_driver);
diff --git a/drivers/pinctrl/sunxi/pinctrl-sun50i-h616.c b/drivers/pinctrl/sunxi/pinctrl-sun50i-h616.c
new file mode 100644
index 0000000..ce1917e
--- /dev/null
+++ b/drivers/pinctrl/sunxi/pinctrl-sun50i-h616.c
@@ -0,0 +1,548 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Allwinner H616 SoC pinctrl driver.
+ *
+ * Copyright (C) 2020 Arm Ltd.
+ * based on the H6 pinctrl driver
+ * Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>
+ */
+
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/pinctrl/pinctrl.h>
+
+#include "pinctrl-sunxi.h"
+
+static const struct sunxi_desc_pin h616_pins[] = {
+ /* Internal connection to the AC200 part */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 0),
+ SUNXI_FUNCTION(0x2, "emac1")), /* ERXD1 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 1),
+ SUNXI_FUNCTION(0x2, "emac1")), /* ERXD0 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 2),
+ SUNXI_FUNCTION(0x2, "emac1")), /* ECRS_DV */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 3),
+ SUNXI_FUNCTION(0x2, "emac1")), /* ERXERR */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 4),
+ SUNXI_FUNCTION(0x2, "emac1")), /* ETXD1 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 5),
+ SUNXI_FUNCTION(0x2, "emac1")), /* ETXD0 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 6),
+ SUNXI_FUNCTION(0x2, "emac1")), /* ETXCK */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 7),
+ SUNXI_FUNCTION(0x2, "emac1")), /* ETXEN */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 8),
+ SUNXI_FUNCTION(0x2, "emac1")), /* EMDC */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 9),
+ SUNXI_FUNCTION(0x2, "emac1")), /* EMDIO */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 10),
+ SUNXI_FUNCTION(0x2, "i2c3")), /* SCK */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 11),
+ SUNXI_FUNCTION(0x2, "i2c3")), /* SDA */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 12),
+ SUNXI_FUNCTION(0x2, "pwm5")),
+ /* Hole */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0"), /* WE */
+ SUNXI_FUNCTION(0x3, "mmc2"), /* DS */
+ SUNXI_FUNCTION(0x4, "spi0"), /* CLK */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 0)), /* PC_EINT0 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 1),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0"), /* ALE */
+ SUNXI_FUNCTION(0x3, "mmc2"), /* RST */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 1)), /* PC_EINT1 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 2),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0"), /* CLE */
+ SUNXI_FUNCTION(0x4, "spi0"), /* MOSI */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 2)), /* PC_EINT2 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 3),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0"), /* CE1 */
+ SUNXI_FUNCTION(0x4, "spi0"), /* CS0 */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 3)), /* PC_EINT3 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 4),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0"), /* CE0 */
+ SUNXI_FUNCTION(0x4, "spi0"), /* MISO */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 4)), /* PC_EINT4 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 5),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0"), /* RE */
+ SUNXI_FUNCTION(0x3, "mmc2"), /* CLK */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 5)), /* PC_EINT5 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 6),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0"), /* RB0 */
+ SUNXI_FUNCTION(0x3, "mmc2"), /* CMD */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 6)), /* PC_EINT6 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 7),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0"), /* RB1 */
+ SUNXI_FUNCTION(0x4, "spi0"), /* CS1 */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 7)), /* PC_EINT7 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 8),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0"), /* DQ7 */
+ SUNXI_FUNCTION(0x3, "mmc2"), /* D3 */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 8)), /* PC_EINT8 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 9),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0"), /* DQ6 */
+ SUNXI_FUNCTION(0x3, "mmc2"), /* D4 */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 9)), /* PC_EINT9 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 10),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0"), /* DQ5 */
+ SUNXI_FUNCTION(0x3, "mmc2"), /* D0 */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 10)), /* PC_EINT10 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 11),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0"), /* DQ4 */
+ SUNXI_FUNCTION(0x3, "mmc2"), /* D5 */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 11)), /* PC_EINT11 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 12),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0"), /* DQS */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 12)), /* PC_EINT12 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 13),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0"), /* DQ3 */
+ SUNXI_FUNCTION(0x3, "mmc2"), /* D1 */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 13)), /* PC_EINT13 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 14),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0"), /* DQ2 */
+ SUNXI_FUNCTION(0x3, "mmc2"), /* D6 */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 14)), /* PC_EINT14 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 15),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0"), /* DQ1 */
+ SUNXI_FUNCTION(0x3, "mmc2"), /* D2 */
+ SUNXI_FUNCTION(0x4, "spi0"), /* WP */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 15)), /* PC_EINT15 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 16),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0"), /* DQ0 */
+ SUNXI_FUNCTION(0x3, "mmc2"), /* D7 */
+ SUNXI_FUNCTION(0x4, "spi0"), /* HOLD */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 16)), /* PC_EINT16 */
+ /* Hole */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 0),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "mmc0"), /* D1 */
+ SUNXI_FUNCTION(0x3, "jtag"), /* MS */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 4, 0)), /* PF_EINT0 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 1),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "mmc0"), /* D0 */
+ SUNXI_FUNCTION(0x3, "jtag"), /* DI */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 4, 1)), /* PF_EINT1 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 2),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "mmc0"), /* CLK */
+ SUNXI_FUNCTION(0x3, "uart0"), /* TX */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 4, 2)), /* PF_EINT2 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 3),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "mmc0"), /* CMD */
+ SUNXI_FUNCTION(0x3, "jtag"), /* DO */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 4, 3)), /* PF_EINT3 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 4),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "mmc0"), /* D3 */
+ SUNXI_FUNCTION(0x3, "uart0"), /* RX */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 4, 4)), /* PF_EINT4 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 5),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "mmc0"), /* D2 */
+ SUNXI_FUNCTION(0x3, "jtag"), /* CK */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 4, 5)), /* PF_EINT5 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 6),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 4, 6)), /* PF_EINT6 */
+ /* Hole */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 0),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "mmc1"), /* CLK */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 0)), /* PG_EINT0 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 1),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "mmc1"), /* CMD */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 1)), /* PG_EINT1 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 2),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "mmc1"), /* D0 */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 2)), /* PG_EINT2 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 3),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "mmc1"), /* D1 */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 3)), /* PG_EINT3 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 4),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "mmc1"), /* D2 */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 4)), /* PG_EINT4 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 5),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "mmc1"), /* D3 */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 5)), /* PG_EINT5 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 6),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "uart1"), /* TX */
+ SUNXI_FUNCTION(0x4, "jtag"), /* MS */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 6)), /* PG_EINT6 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 7),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "uart1"), /* RX */
+ SUNXI_FUNCTION(0x4, "jtag"), /* CK */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 7)), /* PG_EINT7 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 8),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "uart1"), /* RTS */
+ SUNXI_FUNCTION(0x3, "clock"), /* PLL_LOCK_DEBUG */
+ SUNXI_FUNCTION(0x4, "jtag"), /* DO */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 8)), /* PG_EINT8 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 9),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "uart1"), /* CTS */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 9)), /* PG_EINT9 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 10),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "i2s2"), /* MCLK */
+ SUNXI_FUNCTION(0x3, "clock"), /* X32KFOUT */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 10)), /* PG_EINT10 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 11),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "i2s2"), /* BCLK */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 11)), /* PG_EINT11 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 12),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "i2s2"), /* SYNC */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 12)), /* PG_EINT12 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 13),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "i2s2"), /* DOUT */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 13)), /* PG_EINT13 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 14),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "i2s2"), /* DIN */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 14)), /* PG_EINT14 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 15),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "uart2"), /* TX */
+ SUNXI_FUNCTION(0x5, "i2c4"), /* SCK */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 15)), /* PG_EINT15 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 16),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "uart2"), /* RX */
+ SUNXI_FUNCTION(0x5, "i2c4"), /* SDA */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 16)), /* PG_EINT16 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 17),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "uart2"), /* RTS */
+ SUNXI_FUNCTION(0x5, "i2c3"), /* SCK */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 17)), /* PG_EINT17 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 18),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "uart2"), /* CTS */
+ SUNXI_FUNCTION(0x5, "i2c3"), /* SDA */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 18)), /* PG_EINT18 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 19),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x4, "pwm1"),
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 19)), /* PG_EINT19 */
+ /* Hole */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 0),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "uart0"), /* TX */
+ SUNXI_FUNCTION(0x4, "pwm3"),
+ SUNXI_FUNCTION(0x5, "i2c1"), /* SCK */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 0)), /* PH_EINT0 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 1),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "uart0"), /* RX */
+ SUNXI_FUNCTION(0x4, "pwm4"),
+ SUNXI_FUNCTION(0x5, "i2c1"), /* SDA */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 1)), /* PH_EINT1 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 2),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "uart5"), /* TX */
+ SUNXI_FUNCTION(0x3, "spdif"), /* MCLK */
+ SUNXI_FUNCTION(0x4, "pwm2"),
+ SUNXI_FUNCTION(0x5, "i2c2"), /* SCK */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 2)), /* PH_EINT2 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 3),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "uart5"), /* RX */
+ SUNXI_FUNCTION(0x4, "pwm1"),
+ SUNXI_FUNCTION(0x5, "i2c2"), /* SDA */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 3)), /* PH_EINT3 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 4),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x3, "spdif"), /* OUT */
+ SUNXI_FUNCTION(0x5, "i2c3"), /* SCK */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 4)), /* PH_EINT4 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 5),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "uart2"), /* TX */
+ SUNXI_FUNCTION(0x3, "i2s3"), /* MCLK */
+ SUNXI_FUNCTION(0x4, "spi1"), /* CS0 */
+ SUNXI_FUNCTION(0x5, "i2c3"), /* SDA */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 5)), /* PH_EINT5 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 6),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "uart2"), /* RX */
+ SUNXI_FUNCTION(0x3, "i2s3"), /* BCLK */
+ SUNXI_FUNCTION(0x4, "spi1"), /* CLK */
+ SUNXI_FUNCTION(0x5, "i2c4"), /* SCK */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 6)), /* PH_EINT6 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 7),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "uart2"), /* RTS */
+ SUNXI_FUNCTION(0x3, "i2s3"), /* SYNC */
+ SUNXI_FUNCTION(0x4, "spi1"), /* MOSI */
+ SUNXI_FUNCTION(0x5, "i2c4"), /* SDA */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 7)), /* PH_EINT7 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 8),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "uart2"), /* CTS */
+ SUNXI_FUNCTION(0x3, "i2s3"), /* DO0 */
+ SUNXI_FUNCTION(0x4, "spi1"), /* MISO */
+ SUNXI_FUNCTION(0x5, "i2s3"), /* DI1 */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 8)), /* PH_EINT8 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 9),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x3, "i2s3"), /* DI0 */
+ SUNXI_FUNCTION(0x4, "spi1"), /* CS1 */
+ SUNXI_FUNCTION(0x3, "i2s3"), /* DO1 */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 9)), /* PH_EINT9 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 10),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x3, "ir_rx"),
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 10)), /* PH_EINT10 */
+ /* Hole */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 0),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "emac0"), /* ERXD3 */
+ SUNXI_FUNCTION(0x3, "dmic"), /* CLK */
+ SUNXI_FUNCTION(0x4, "i2s0"), /* MCLK */
+ SUNXI_FUNCTION(0x5, "hdmi"), /* HSCL */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 7, 0)), /* PI_EINT0 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 1),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "emac0"), /* ERXD2 */
+ SUNXI_FUNCTION(0x3, "dmic"), /* DATA0 */
+ SUNXI_FUNCTION(0x4, "i2s0"), /* BCLK */
+ SUNXI_FUNCTION(0x5, "hdmi"), /* HSDA */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 7, 1)), /* PI_EINT1 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 2),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "emac0"), /* ERXD1 */
+ SUNXI_FUNCTION(0x3, "dmic"), /* DATA1 */
+ SUNXI_FUNCTION(0x4, "i2s0"), /* SYNC */
+ SUNXI_FUNCTION(0x5, "hdmi"), /* HCEC */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 7, 2)), /* PI_EINT2 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 3),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "emac0"), /* ERXD0 */
+ SUNXI_FUNCTION(0x3, "dmic"), /* DATA2 */
+ SUNXI_FUNCTION(0x4, "i2s0_dout0"), /* DO0 */
+ SUNXI_FUNCTION(0x5, "i2s0_din1"), /* DI1 */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 7, 3)), /* PI_EINT3 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 4),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "emac0"), /* ERXCK */
+ SUNXI_FUNCTION(0x3, "dmic"), /* DATA3 */
+ SUNXI_FUNCTION(0x4, "i2s0_din0"), /* DI0 */
+ SUNXI_FUNCTION(0x5, "i2s0_dout1"), /* DO1 */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 7, 4)), /* PI_EINT4 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 5),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "emac0"), /* ERXCTL */
+ SUNXI_FUNCTION(0x3, "uart2"), /* TX */
+ SUNXI_FUNCTION(0x4, "ts0"), /* CLK */
+ SUNXI_FUNCTION(0x5, "i2c0"), /* SCK */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 7, 5)), /* PI_EINT5 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 6),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "emac0"), /* ENULL */
+ SUNXI_FUNCTION(0x3, "uart2"), /* RX */
+ SUNXI_FUNCTION(0x4, "ts0"), /* ERR */
+ SUNXI_FUNCTION(0x5, "i2c0"), /* SDA */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 7, 6)), /* PI_EINT6 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 7),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "emac0"), /* ETXD3 */
+ SUNXI_FUNCTION(0x3, "uart2"), /* RTS */
+ SUNXI_FUNCTION(0x4, "ts0"), /* SYNC */
+ SUNXI_FUNCTION(0x5, "i2c1"), /* SCK */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 7, 7)), /* PI_EINT7 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 8),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "emac0"), /* ETXD2 */
+ SUNXI_FUNCTION(0x3, "uart2"), /* CTS */
+ SUNXI_FUNCTION(0x4, "ts0"), /* DVLD */
+ SUNXI_FUNCTION(0x5, "i2c1"), /* SDA */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 7, 8)), /* PI_EINT8 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 9),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "emac0"), /* ETXD1 */
+ SUNXI_FUNCTION(0x3, "uart3"), /* TX */
+ SUNXI_FUNCTION(0x4, "ts0"), /* D0 */
+ SUNXI_FUNCTION(0x5, "i2c2"), /* SCK */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 7, 9)), /* PI_EINT9 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 10),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "emac0"), /* ETXD0 */
+ SUNXI_FUNCTION(0x3, "uart3"), /* RX */
+ SUNXI_FUNCTION(0x4, "ts0"), /* D1 */
+ SUNXI_FUNCTION(0x5, "i2c2"), /* SDA */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 7, 10)), /* PI_EINT10 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 11),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "emac0"), /* ETXCK */
+ SUNXI_FUNCTION(0x3, "uart3"), /* RTS */
+ SUNXI_FUNCTION(0x4, "ts0"), /* D2 */
+ SUNXI_FUNCTION(0x5, "pwm1"),
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 7, 11)), /* PI_EINT11 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 12),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "emac0"), /* ETXCTL */
+ SUNXI_FUNCTION(0x3, "uart3"), /* CTS */
+ SUNXI_FUNCTION(0x4, "ts0"), /* D3 */
+ SUNXI_FUNCTION(0x5, "pwm2"),
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 7, 12)), /* PI_EINT12 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 13),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "emac0"), /* ECLKIN */
+ SUNXI_FUNCTION(0x3, "uart4"), /* TX */
+ SUNXI_FUNCTION(0x4, "ts0"), /* D4 */
+ SUNXI_FUNCTION(0x5, "pwm3"),
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 7, 13)), /* PI_EINT13 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 14),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "emac0"), /* MDC */
+ SUNXI_FUNCTION(0x3, "uart4"), /* RX */
+ SUNXI_FUNCTION(0x4, "ts0"), /* D5 */
+ SUNXI_FUNCTION(0x5, "pwm4"),
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 7, 14)), /* PI_EINT14 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 15),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "emac0"), /* MDIO */
+ SUNXI_FUNCTION(0x3, "uart4"), /* RTS */
+ SUNXI_FUNCTION(0x4, "ts0"), /* D6 */
+ SUNXI_FUNCTION(0x5, "clock"), /* CLK_FANOUT0 */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 7, 15)), /* PI_EINT15 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 16),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "emac0"), /* EPHY_CLK */
+ SUNXI_FUNCTION(0x3, "uart4"), /* CTS */
+ SUNXI_FUNCTION(0x4, "ts0"), /* D7 */
+ SUNXI_FUNCTION(0x5, "clock"), /* CLK_FANOUT1 */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 7, 16)), /* PI_EINT16 */
+};
+static const unsigned int h616_irq_bank_map[] = { 0, 2, 3, 4, 5, 6, 7, 8 };
+
+static const struct sunxi_pinctrl_desc h616_pinctrl_data = {
+ .pins = h616_pins,
+ .npins = ARRAY_SIZE(h616_pins),
+ .irq_banks = ARRAY_SIZE(h616_irq_bank_map),
+ .irq_bank_map = h616_irq_bank_map,
+ .irq_read_needs_mux = true,
+ .io_bias_cfg_variant = BIAS_VOLTAGE_PIO_POW_MODE_SEL,
+};
+
+static int h616_pinctrl_probe(struct platform_device *pdev)
+{
+ return sunxi_pinctrl_init(pdev, &h616_pinctrl_data);
+}
+
+static const struct of_device_id h616_pinctrl_match[] = {
+ { .compatible = "allwinner,sun50i-h616-pinctrl", },
+ {}
+};
+
+static struct platform_driver h616_pinctrl_driver = {
+ .probe = h616_pinctrl_probe,
+ .driver = {
+ .name = "sun50i-h616-pinctrl",
+ .of_match_table = h616_pinctrl_match,
+ },
+};
+builtin_platform_driver(h616_pinctrl_driver);
diff --git a/drivers/pinctrl/ti/pinctrl-ti-iodelay.c b/drivers/pinctrl/ti/pinctrl-ti-iodelay.c
index cfb9242..60a6713 100644
--- a/drivers/pinctrl/ti/pinctrl-ti-iodelay.c
+++ b/drivers/pinctrl/ti/pinctrl-ti-iodelay.c
@@ -704,10 +704,9 @@
u32 reg = 0;
cfg = &group->cfg[i];
- regmap_read(iod->regmap, cfg->offset, ®),
- seq_printf(s, "\n\t0x%08x = 0x%08x (%3d, %3d)",
- cfg->offset, reg, cfg->a_delay,
- cfg->g_delay);
+ regmap_read(iod->regmap, cfg->offset, ®);
+ seq_printf(s, "\n\t0x%08x = 0x%08x (%3d, %3d)",
+ cfg->offset, reg, cfg->a_delay, cfg->g_delay);
}
}
#endif
diff --git a/drivers/pinctrl/zte/Kconfig b/drivers/pinctrl/zte/Kconfig
deleted file mode 100644
index 4fdc705..0000000
--- a/drivers/pinctrl/zte/Kconfig
+++ /dev/null
@@ -1,14 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0-only
-config PINCTRL_ZX
- bool
- select PINMUX
- select GENERIC_PINCONF
- select GENERIC_PINCTRL_GROUPS
- select GENERIC_PINMUX_FUNCTIONS
-
-config PINCTRL_ZX296718
- bool "ZTE ZX296718 pinctrl driver"
- depends on OF && ARCH_ZX
- select PINCTRL_ZX
- help
- Say Y here to enable the ZX296718 pinctrl driver
diff --git a/drivers/pinctrl/zte/Makefile b/drivers/pinctrl/zte/Makefile
deleted file mode 100644
index 2084c78..0000000
--- a/drivers/pinctrl/zte/Makefile
+++ /dev/null
@@ -1,3 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0-only
-obj-$(CONFIG_PINCTRL_ZX) += pinctrl-zx.o
-obj-$(CONFIG_PINCTRL_ZX296718) += pinctrl-zx296718.o
diff --git a/drivers/pinctrl/zte/pinctrl-zx.c b/drivers/pinctrl/zte/pinctrl-zx.c
deleted file mode 100644
index 80d00ab..0000000
--- a/drivers/pinctrl/zte/pinctrl-zx.c
+++ /dev/null
@@ -1,445 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Copyright (C) 2017 Sanechips Technology Co., Ltd.
- * Copyright 2017 Linaro Ltd.
- */
-
-#include <linux/io.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-#include <linux/of_device.h>
-#include <linux/pinctrl/pinctrl.h>
-#include <linux/pinctrl/pinconf-generic.h>
-#include <linux/pinctrl/pinmux.h>
-#include <linux/platform_device.h>
-#include <linux/slab.h>
-
-#include "../core.h"
-#include "../pinctrl-utils.h"
-#include "../pinmux.h"
-#include "pinctrl-zx.h"
-
-#define ZX_PULL_DOWN BIT(0)
-#define ZX_PULL_UP BIT(1)
-#define ZX_INPUT_ENABLE BIT(3)
-#define ZX_DS_SHIFT 4
-#define ZX_DS_MASK (0x7 << ZX_DS_SHIFT)
-#define ZX_DS_VALUE(x) (((x) << ZX_DS_SHIFT) & ZX_DS_MASK)
-#define ZX_SLEW BIT(8)
-
-struct zx_pinctrl {
- struct pinctrl_dev *pctldev;
- struct device *dev;
- void __iomem *base;
- void __iomem *aux_base;
- spinlock_t lock;
- struct zx_pinctrl_soc_info *info;
-};
-
-static int zx_dt_node_to_map(struct pinctrl_dev *pctldev,
- struct device_node *np_config,
- struct pinctrl_map **map, u32 *num_maps)
-{
- return pinconf_generic_dt_node_to_map(pctldev, np_config, map,
- num_maps, PIN_MAP_TYPE_INVALID);
-}
-
-static const struct pinctrl_ops zx_pinctrl_ops = {
- .dt_node_to_map = zx_dt_node_to_map,
- .dt_free_map = pinctrl_utils_free_map,
- .get_groups_count = pinctrl_generic_get_group_count,
- .get_group_name = pinctrl_generic_get_group_name,
- .get_group_pins = pinctrl_generic_get_group_pins,
-};
-
-#define NONAON_MVAL 2
-
-static int zx_set_mux(struct pinctrl_dev *pctldev, unsigned int func_selector,
- unsigned int group_selector)
-{
- struct zx_pinctrl *zpctl = pinctrl_dev_get_drvdata(pctldev);
- struct zx_pinctrl_soc_info *info = zpctl->info;
- const struct pinctrl_pin_desc *pindesc = info->pins + group_selector;
- struct zx_pin_data *data = pindesc->drv_data;
- struct zx_mux_desc *mux;
- u32 mask, offset, bitpos;
- struct function_desc *func;
- unsigned long flags;
- u32 val, mval;
-
- /* Skip reserved pin */
- if (!data)
- return -EINVAL;
-
- mux = data->muxes;
- mask = (1 << data->width) - 1;
- offset = data->offset;
- bitpos = data->bitpos;
-
- func = pinmux_generic_get_function(pctldev, func_selector);
- if (!func)
- return -EINVAL;
-
- while (mux->name) {
- if (strcmp(mux->name, func->name) == 0)
- break;
- mux++;
- }
-
- /* Found mux value to be written */
- mval = mux->muxval;
-
- spin_lock_irqsave(&zpctl->lock, flags);
-
- if (data->aon_pin) {
- /*
- * It's an AON pin, whose mux register offset and bit position
- * can be calculated from pin number. Each register covers 16
- * pins, and each pin occupies 2 bits.
- */
- u16 aoffset = pindesc->number / 16 * 4;
- u16 abitpos = (pindesc->number % 16) * 2;
-
- if (mval & AON_MUX_FLAG) {
- /*
- * This is a mux value that needs to be written into
- * AON pinmux register. Write it and then we're done.
- */
- val = readl(zpctl->aux_base + aoffset);
- val &= ~(0x3 << abitpos);
- val |= (mval & 0x3) << abitpos;
- writel(val, zpctl->aux_base + aoffset);
- } else {
- /*
- * It's a mux value that needs to be written into TOP
- * pinmux register.
- */
- val = readl(zpctl->base + offset);
- val &= ~(mask << bitpos);
- val |= (mval & mask) << bitpos;
- writel(val, zpctl->base + offset);
-
- /*
- * In this case, the AON pinmux register needs to be
- * set up to select non-AON function.
- */
- val = readl(zpctl->aux_base + aoffset);
- val &= ~(0x3 << abitpos);
- val |= NONAON_MVAL << abitpos;
- writel(val, zpctl->aux_base + aoffset);
- }
-
- } else {
- /*
- * This is a TOP pin, and we only need to set up TOP pinmux
- * register and then we're done with it.
- */
- val = readl(zpctl->base + offset);
- val &= ~(mask << bitpos);
- val |= (mval & mask) << bitpos;
- writel(val, zpctl->base + offset);
- }
-
- spin_unlock_irqrestore(&zpctl->lock, flags);
-
- return 0;
-}
-
-static const struct pinmux_ops zx_pinmux_ops = {
- .get_functions_count = pinmux_generic_get_function_count,
- .get_function_name = pinmux_generic_get_function_name,
- .get_function_groups = pinmux_generic_get_function_groups,
- .set_mux = zx_set_mux,
-};
-
-static int zx_pin_config_get(struct pinctrl_dev *pctldev, unsigned int pin,
- unsigned long *config)
-{
- struct zx_pinctrl *zpctl = pinctrl_dev_get_drvdata(pctldev);
- struct zx_pinctrl_soc_info *info = zpctl->info;
- const struct pinctrl_pin_desc *pindesc = info->pins + pin;
- struct zx_pin_data *data = pindesc->drv_data;
- enum pin_config_param param = pinconf_to_config_param(*config);
- u32 val;
-
- /* Skip reserved pin */
- if (!data)
- return -EINVAL;
-
- val = readl(zpctl->aux_base + data->coffset);
- val = val >> data->cbitpos;
-
- switch (param) {
- case PIN_CONFIG_BIAS_PULL_DOWN:
- val &= ZX_PULL_DOWN;
- val = !!val;
- if (val == 0)
- return -EINVAL;
- break;
- case PIN_CONFIG_BIAS_PULL_UP:
- val &= ZX_PULL_UP;
- val = !!val;
- if (val == 0)
- return -EINVAL;
- break;
- case PIN_CONFIG_INPUT_ENABLE:
- val &= ZX_INPUT_ENABLE;
- val = !!val;
- if (val == 0)
- return -EINVAL;
- break;
- case PIN_CONFIG_DRIVE_STRENGTH:
- val &= ZX_DS_MASK;
- val = val >> ZX_DS_SHIFT;
- break;
- case PIN_CONFIG_SLEW_RATE:
- val &= ZX_SLEW;
- val = !!val;
- break;
- default:
- return -ENOTSUPP;
- }
-
- *config = pinconf_to_config_packed(param, val);
-
- return 0;
-}
-
-static int zx_pin_config_set(struct pinctrl_dev *pctldev, unsigned int pin,
- unsigned long *configs, unsigned int num_configs)
-{
- struct zx_pinctrl *zpctl = pinctrl_dev_get_drvdata(pctldev);
- struct zx_pinctrl_soc_info *info = zpctl->info;
- const struct pinctrl_pin_desc *pindesc = info->pins + pin;
- struct zx_pin_data *data = pindesc->drv_data;
- enum pin_config_param param;
- u32 val, arg;
- int i;
-
- /* Skip reserved pin */
- if (!data)
- return -EINVAL;
-
- val = readl(zpctl->aux_base + data->coffset);
-
- for (i = 0; i < num_configs; i++) {
- param = pinconf_to_config_param(configs[i]);
- arg = pinconf_to_config_argument(configs[i]);
-
- switch (param) {
- case PIN_CONFIG_BIAS_PULL_DOWN:
- val |= ZX_PULL_DOWN << data->cbitpos;
- break;
- case PIN_CONFIG_BIAS_PULL_UP:
- val |= ZX_PULL_UP << data->cbitpos;
- break;
- case PIN_CONFIG_INPUT_ENABLE:
- val |= ZX_INPUT_ENABLE << data->cbitpos;
- break;
- case PIN_CONFIG_DRIVE_STRENGTH:
- val &= ~(ZX_DS_MASK << data->cbitpos);
- val |= ZX_DS_VALUE(arg) << data->cbitpos;
- break;
- case PIN_CONFIG_SLEW_RATE:
- if (arg)
- val |= ZX_SLEW << data->cbitpos;
- else
- val &= ~ZX_SLEW << data->cbitpos;
- break;
- default:
- return -ENOTSUPP;
- }
- }
-
- writel(val, zpctl->aux_base + data->coffset);
- return 0;
-}
-
-static const struct pinconf_ops zx_pinconf_ops = {
- .pin_config_set = zx_pin_config_set,
- .pin_config_get = zx_pin_config_get,
- .is_generic = true,
-};
-
-static int zx_pinctrl_build_state(struct platform_device *pdev)
-{
- struct zx_pinctrl *zpctl = platform_get_drvdata(pdev);
- struct zx_pinctrl_soc_info *info = zpctl->info;
- struct pinctrl_dev *pctldev = zpctl->pctldev;
- struct function_desc *functions;
- int nfunctions;
- struct group_desc *groups;
- int ngroups;
- int i;
-
- /* Every single pin composes a group */
- ngroups = info->npins;
- groups = devm_kcalloc(&pdev->dev, ngroups, sizeof(*groups),
- GFP_KERNEL);
- if (!groups)
- return -ENOMEM;
-
- for (i = 0; i < ngroups; i++) {
- const struct pinctrl_pin_desc *pindesc = info->pins + i;
- struct group_desc *group = groups + i;
-
- group->name = pindesc->name;
- group->pins = (int *) &pindesc->number;
- group->num_pins = 1;
- radix_tree_insert(&pctldev->pin_group_tree, i, group);
- }
-
- pctldev->num_groups = ngroups;
-
- /* Build function list from pin mux functions */
- functions = kcalloc(info->npins, sizeof(*functions), GFP_KERNEL);
- if (!functions)
- return -ENOMEM;
-
- nfunctions = 0;
- for (i = 0; i < info->npins; i++) {
- const struct pinctrl_pin_desc *pindesc = info->pins + i;
- struct zx_pin_data *data = pindesc->drv_data;
- struct zx_mux_desc *mux;
-
- /* Reserved pins do not have a drv_data at all */
- if (!data)
- continue;
-
- /* Loop over all muxes for the pin */
- mux = data->muxes;
- while (mux->name) {
- struct function_desc *func = functions;
-
- /* Search function list for given mux */
- while (func->name) {
- if (strcmp(mux->name, func->name) == 0) {
- /* Function exists */
- func->num_group_names++;
- break;
- }
- func++;
- }
-
- if (!func->name) {
- /* New function */
- func->name = mux->name;
- func->num_group_names = 1;
- radix_tree_insert(&pctldev->pin_function_tree,
- nfunctions++, func);
- }
-
- mux++;
- }
- }
-
- pctldev->num_functions = nfunctions;
- functions = krealloc(functions, nfunctions * sizeof(*functions),
- GFP_KERNEL);
-
- /* Find pin groups for every single function */
- for (i = 0; i < info->npins; i++) {
- const struct pinctrl_pin_desc *pindesc = info->pins + i;
- struct zx_pin_data *data = pindesc->drv_data;
- struct zx_mux_desc *mux;
-
- if (!data)
- continue;
-
- mux = data->muxes;
- while (mux->name) {
- struct function_desc *func;
- const char **group;
- int j;
-
- /* Find function for given mux */
- for (j = 0; j < nfunctions; j++)
- if (strcmp(functions[j].name, mux->name) == 0)
- break;
-
- func = functions + j;
- if (!func->group_names) {
- func->group_names = devm_kcalloc(&pdev->dev,
- func->num_group_names,
- sizeof(*func->group_names),
- GFP_KERNEL);
- if (!func->group_names) {
- kfree(functions);
- return -ENOMEM;
- }
- }
-
- group = func->group_names;
- while (*group)
- group++;
- *group = pindesc->name;
-
- mux++;
- }
- }
-
- return 0;
-}
-
-int zx_pinctrl_init(struct platform_device *pdev,
- struct zx_pinctrl_soc_info *info)
-{
- struct pinctrl_desc *pctldesc;
- struct zx_pinctrl *zpctl;
- struct device_node *np;
- int ret;
-
- zpctl = devm_kzalloc(&pdev->dev, sizeof(*zpctl), GFP_KERNEL);
- if (!zpctl)
- return -ENOMEM;
-
- spin_lock_init(&zpctl->lock);
-
- zpctl->base = devm_platform_ioremap_resource(pdev, 0);
- if (IS_ERR(zpctl->base))
- return PTR_ERR(zpctl->base);
-
- np = of_parse_phandle(pdev->dev.of_node, "zte,auxiliary-controller", 0);
- if (!np) {
- dev_err(&pdev->dev, "failed to find auxiliary controller\n");
- return -ENODEV;
- }
-
- zpctl->aux_base = of_iomap(np, 0);
- of_node_put(np);
- if (!zpctl->aux_base)
- return -ENOMEM;
-
- zpctl->dev = &pdev->dev;
- zpctl->info = info;
-
- pctldesc = devm_kzalloc(&pdev->dev, sizeof(*pctldesc), GFP_KERNEL);
- if (!pctldesc)
- return -ENOMEM;
-
- pctldesc->name = dev_name(&pdev->dev);
- pctldesc->owner = THIS_MODULE;
- pctldesc->pins = info->pins;
- pctldesc->npins = info->npins;
- pctldesc->pctlops = &zx_pinctrl_ops;
- pctldesc->pmxops = &zx_pinmux_ops;
- pctldesc->confops = &zx_pinconf_ops;
-
- zpctl->pctldev = devm_pinctrl_register(&pdev->dev, pctldesc, zpctl);
- if (IS_ERR(zpctl->pctldev)) {
- ret = PTR_ERR(zpctl->pctldev);
- dev_err(&pdev->dev, "failed to register pinctrl: %d\n", ret);
- return ret;
- }
-
- platform_set_drvdata(pdev, zpctl);
-
- ret = zx_pinctrl_build_state(pdev);
- if (ret) {
- dev_err(&pdev->dev, "failed to build state: %d\n", ret);
- return ret;
- }
-
- dev_info(&pdev->dev, "initialized pinctrl driver\n");
- return 0;
-}
diff --git a/drivers/pinctrl/zte/pinctrl-zx.h b/drivers/pinctrl/zte/pinctrl-zx.h
deleted file mode 100644
index a0692e2..0000000
--- a/drivers/pinctrl/zte/pinctrl-zx.h
+++ /dev/null
@@ -1,102 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * Copyright (C) 2017 Sanechips Technology Co., Ltd.
- * Copyright 2017 Linaro Ltd.
- */
-
-#ifndef __PINCTRL_ZX_H
-#define __PINCTRL_ZX_H
-
-/**
- * struct zx_mux_desc - hardware mux descriptor
- * @name: mux function name
- * @muxval: mux register bit value
- */
-struct zx_mux_desc {
- const char *name;
- u8 muxval;
-};
-
-/**
- * struct zx_pin_data - hardware per-pin data
- * @aon_pin: whether it's an AON pin
- * @offset: register offset within TOP pinmux controller
- * @bitpos: bit position within TOP pinmux register
- * @width: bit width within TOP pinmux register
- * @coffset: pinconf register offset within AON controller
- * @cbitpos: pinconf bit position within AON register
- * @muxes: available mux function names and corresponding register values
- *
- * Unlike TOP pinmux and AON pinconf registers which are arranged pretty
- * arbitrarily, AON pinmux register bits are well organized per pin id, and
- * each pin occupies two bits, so that we can calculate the AON register offset
- * and bit position from pin id. Thus, we only need to define TOP pinmux and
- * AON pinconf register data for the pin.
- */
-struct zx_pin_data {
- bool aon_pin;
- u16 offset;
- u16 bitpos;
- u16 width;
- u16 coffset;
- u16 cbitpos;
- struct zx_mux_desc *muxes;
-};
-
-struct zx_pinctrl_soc_info {
- const struct pinctrl_pin_desc *pins;
- unsigned int npins;
-};
-
-#define TOP_PIN(pin, off, bp, wd, coff, cbp, ...) { \
- .number = pin, \
- .name = #pin, \
- .drv_data = &(struct zx_pin_data) { \
- .aon_pin = false, \
- .offset = off, \
- .bitpos = bp, \
- .width = wd, \
- .coffset = coff, \
- .cbitpos = cbp, \
- .muxes = (struct zx_mux_desc[]) { \
- __VA_ARGS__, { } }, \
- }, \
-}
-
-#define AON_PIN(pin, off, bp, wd, coff, cbp, ...) { \
- .number = pin, \
- .name = #pin, \
- .drv_data = &(struct zx_pin_data) { \
- .aon_pin = true, \
- .offset = off, \
- .bitpos = bp, \
- .width = wd, \
- .coffset = coff, \
- .cbitpos = cbp, \
- .muxes = (struct zx_mux_desc[]) { \
- __VA_ARGS__, { } }, \
- }, \
-}
-
-#define ZX_RESERVED(pin) PINCTRL_PIN(pin, #pin)
-
-#define TOP_MUX(_val, _name) { \
- .name = _name, \
- .muxval = _val, \
-}
-
-/*
- * When the flag is set, it's a mux configuration for an AON pin that sits in
- * AON register. Otherwise, it's one for AON pin but sitting in TOP register.
- */
-#define AON_MUX_FLAG BIT(7)
-
-#define AON_MUX(_val, _name) { \
- .name = _name, \
- .muxval = _val | AON_MUX_FLAG, \
-}
-
-int zx_pinctrl_init(struct platform_device *pdev,
- struct zx_pinctrl_soc_info *info);
-
-#endif /* __PINCTRL_ZX_H */
diff --git a/drivers/pinctrl/zte/pinctrl-zx296718.c b/drivers/pinctrl/zte/pinctrl-zx296718.c
deleted file mode 100644
index c980aec..0000000
--- a/drivers/pinctrl/zte/pinctrl-zx296718.c
+++ /dev/null
@@ -1,1024 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Copyright (C) 2017 Sanechips Technology Co., Ltd.
- * Copyright 2017 Linaro Ltd.
- */
-
-#include <linux/module.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-#include <linux/of_device.h>
-#include <linux/pinctrl/pinctrl.h>
-#include <linux/platform_device.h>
-
-#include "pinctrl-zx.h"
-
-#define TOP_REG0 0x00
-#define TOP_REG1 0x04
-#define TOP_REG2 0x08
-#define TOP_REG3 0x0c
-#define TOP_REG4 0x10
-#define TOP_REG5 0x14
-#define TOP_REG6 0x18
-#define TOP_REG7 0x1c
-#define TOP_REG8 0x20
-
-/*
- * The pin numbering starts from AON pins with reserved ones included,
- * so that register data like offset and bit position for AON pins can
- * be calculated from pin number.
- */
-enum zx296718_pin {
- /* aon_pmm_reg_0 */
- I2C3_SCL = 0,
- I2C3_SDA = 1,
- AON_RESERVED0 = 2,
- AON_RESERVED1 = 3,
- SEC_EN = 4,
- UART0_RXD = 5,
- UART0_TXD = 6,
- IR_IN = 7,
- SPI0_CLK = 8,
- SPI0_CS = 9,
- SPI0_TXD = 10,
- SPI0_RXD = 11,
- KEY_COL0 = 12,
- KEY_COL1 = 13,
- KEY_COL2 = 14,
- KEY_ROW0 = 15,
-
- /* aon_pmm_reg_1 */
- KEY_ROW1 = 16,
- KEY_ROW2 = 17,
- HDMI_SCL = 18,
- HDMI_SDA = 19,
- JTAG_TCK = 20,
- JTAG_TRSTN = 21,
- JTAG_TMS = 22,
- JTAG_TDI = 23,
- JTAG_TDO = 24,
- I2C0_SCL = 25,
- I2C0_SDA = 26,
- I2C1_SCL = 27,
- I2C1_SDA = 28,
- AON_RESERVED2 = 29,
- AON_RESERVED3 = 30,
- AON_RESERVED4 = 31,
-
- /* aon_pmm_reg_2 */
- SPI1_CLK = 32,
- SPI1_CS = 33,
- SPI1_TXD = 34,
- SPI1_RXD = 35,
- AON_RESERVED5 = 36,
- AON_RESERVED6 = 37,
- AUDIO_DET = 38,
- SPDIF_OUT = 39,
- HDMI_CEC = 40,
- HDMI_HPD = 41,
- GMAC_25M_OUT = 42,
- BOOT_SEL0 = 43,
- BOOT_SEL1 = 44,
- BOOT_SEL2 = 45,
- DEEP_SLEEP_OUT_N = 46,
- AON_RESERVED7 = 47,
-
- /* top_pmm_reg_0 */
- GMII_GTX_CLK = 48,
- GMII_TX_CLK = 49,
- GMII_TXD0 = 50,
- GMII_TXD1 = 51,
- GMII_TXD2 = 52,
- GMII_TXD3 = 53,
- GMII_TXD4 = 54,
- GMII_TXD5 = 55,
- GMII_TXD6 = 56,
- GMII_TXD7 = 57,
- GMII_TX_ER = 58,
- GMII_TX_EN = 59,
- GMII_RX_CLK = 60,
- GMII_RXD0 = 61,
- GMII_RXD1 = 62,
- GMII_RXD2 = 63,
-
- /* top_pmm_reg_1 */
- GMII_RXD3 = 64,
- GMII_RXD4 = 65,
- GMII_RXD5 = 66,
- GMII_RXD6 = 67,
- GMII_RXD7 = 68,
- GMII_RX_ER = 69,
- GMII_RX_DV = 70,
- GMII_COL = 71,
- GMII_CRS = 72,
- GMII_MDC = 73,
- GMII_MDIO = 74,
- SDIO1_CLK = 75,
- SDIO1_CMD = 76,
- SDIO1_DATA0 = 77,
- SDIO1_DATA1 = 78,
- SDIO1_DATA2 = 79,
-
- /* top_pmm_reg_2 */
- SDIO1_DATA3 = 80,
- SDIO1_CD = 81,
- SDIO1_WP = 82,
- USIM1_CD = 83,
- USIM1_CLK = 84,
- USIM1_RST = 85,
-
- /* top_pmm_reg_3 */
- USIM1_DATA = 86,
- SDIO0_CLK = 87,
- SDIO0_CMD = 88,
- SDIO0_DATA0 = 89,
- SDIO0_DATA1 = 90,
- SDIO0_DATA2 = 91,
- SDIO0_DATA3 = 92,
- SDIO0_CD = 93,
- SDIO0_WP = 94,
-
- /* top_pmm_reg_4 */
- TSI0_DATA0 = 95,
- SPINOR_CLK = 96,
- TSI2_DATA = 97,
- TSI2_CLK = 98,
- TSI2_SYNC = 99,
- TSI2_VALID = 100,
- SPINOR_CS = 101,
- SPINOR_DQ0 = 102,
- SPINOR_DQ1 = 103,
- SPINOR_DQ2 = 104,
- SPINOR_DQ3 = 105,
- VGA_HS = 106,
- VGA_VS = 107,
- TSI3_DATA = 108,
-
- /* top_pmm_reg_5 */
- TSI3_CLK = 109,
- TSI3_SYNC = 110,
- TSI3_VALID = 111,
- I2S1_WS = 112,
- I2S1_BCLK = 113,
- I2S1_MCLK = 114,
- I2S1_DIN0 = 115,
- I2S1_DOUT0 = 116,
- SPI3_CLK = 117,
- SPI3_CS = 118,
- SPI3_TXD = 119,
- NAND_LDO_MS18_SEL = 120,
-
- /* top_pmm_reg_6 */
- SPI3_RXD = 121,
- I2S0_MCLK = 122,
- I2S0_BCLK = 123,
- I2S0_WS = 124,
- I2S0_DIN0 = 125,
- I2S0_DOUT0 = 126,
- I2C5_SCL = 127,
- I2C5_SDA = 128,
- SPI2_CLK = 129,
- SPI2_CS = 130,
- SPI2_TXD = 131,
-
- /* top_pmm_reg_7 */
- SPI2_RXD = 132,
- NAND_WP_N = 133,
- NAND_PAGE_SIZE0 = 134,
- NAND_PAGE_SIZE1 = 135,
- NAND_ADDR_CYCLE = 136,
- NAND_RB0 = 137,
- NAND_RB1 = 138,
- NAND_RB2 = 139,
- NAND_RB3 = 140,
-
- /* top_pmm_reg_8 */
- GMAC_125M_IN = 141,
- GMAC_50M_OUT = 142,
- SPINOR_SSCLK_LOOPBACK = 143,
- SPINOR_SDIO1CLK_LOOPBACK = 144,
-};
-
-static const struct pinctrl_pin_desc zx296718_pins[] = {
- /* aon_pmm_reg_0 */
- AON_PIN(I2C3_SCL, TOP_REG2, 18, 2, 0x48, 0,
- AON_MUX(0x0, "ANMI"), /* anmi */
- AON_MUX(0x1, "AGPIO"), /* agpio29 */
- AON_MUX(0x2, "nonAON"), /* pin0 */
- AON_MUX(0x3, "EXT_INT"), /* int4 */
- TOP_MUX(0x0, "I2C3"), /* scl */
- TOP_MUX(0x1, "SPI2"), /* txd */
- TOP_MUX(0x2, "I2S1")), /* din0 */
- AON_PIN(I2C3_SDA, TOP_REG2, 20, 2, 0x48, 9,
- AON_MUX(0x0, "WD"), /* rst_b */
- AON_MUX(0x1, "AGPIO"), /* agpio30 */
- AON_MUX(0x2, "nonAON"), /* pin1 */
- AON_MUX(0x3, "EXT_INT"), /* int5 */
- TOP_MUX(0x0, "I2C3"), /* sda */
- TOP_MUX(0x1, "SPI2"), /* rxd */
- TOP_MUX(0x2, "I2S0")), /* mclk */
- ZX_RESERVED(AON_RESERVED0),
- ZX_RESERVED(AON_RESERVED1),
- AON_PIN(SEC_EN, TOP_REG3, 5, 1, 0x50, 0,
- AON_MUX(0x0, "SEC"), /* en */
- AON_MUX(0x1, "AGPIO"), /* agpio28 */
- AON_MUX(0x2, "nonAON"), /* pin3 */
- AON_MUX(0x3, "EXT_INT"), /* int7 */
- TOP_MUX(0x0, "I2C2"), /* sda */
- TOP_MUX(0x1, "SPI2")), /* cs */
- AON_PIN(UART0_RXD, 0, 0, 0, 0x50, 9,
- AON_MUX(0x0, "UART0"), /* rxd */
- AON_MUX(0x1, "AGPIO"), /* agpio20 */
- AON_MUX(0x2, "nonAON")), /* pin34 */
- AON_PIN(UART0_TXD, 0, 0, 0, 0x50, 18,
- AON_MUX(0x0, "UART0"), /* txd */
- AON_MUX(0x1, "AGPIO"), /* agpio21 */
- AON_MUX(0x2, "nonAON")), /* pin32 */
- AON_PIN(IR_IN, 0, 0, 0, 0x64, 0,
- AON_MUX(0x0, "IR"), /* in */
- AON_MUX(0x1, "AGPIO"), /* agpio0 */
- AON_MUX(0x2, "nonAON")), /* pin27 */
- AON_PIN(SPI0_CLK, TOP_REG3, 16, 1, 0x64, 9,
- AON_MUX(0x0, "EXT_INT"), /* int0 */
- AON_MUX(0x1, "AGPIO"), /* agpio23 */
- AON_MUX(0x2, "nonAON"), /* pin5 */
- AON_MUX(0x3, "PCU"), /* test6 */
- TOP_MUX(0x0, "SPI0"), /* clk */
- TOP_MUX(0x1, "ISP")), /* flash_trig */
- AON_PIN(SPI0_CS, TOP_REG3, 17, 1, 0x64, 18,
- AON_MUX(0x0, "EXT_INT"), /* int1 */
- AON_MUX(0x1, "AGPIO"), /* agpio24 */
- AON_MUX(0x2, "nonAON"), /* pin6 */
- AON_MUX(0x3, "PCU"), /* test0 */
- TOP_MUX(0x0, "SPI0"), /* cs */
- TOP_MUX(0x1, "ISP")), /* prelight_trig */
- AON_PIN(SPI0_TXD, TOP_REG3, 18, 1, 0x68, 0,
- AON_MUX(0x0, "EXT_INT"), /* int2 */
- AON_MUX(0x1, "AGPIO"), /* agpio25 */
- AON_MUX(0x2, "nonAON"), /* pin7 */
- AON_MUX(0x3, "PCU"), /* test1 */
- TOP_MUX(0x0, "SPI0"), /* txd */
- TOP_MUX(0x1, "ISP")), /* shutter_trig */
- AON_PIN(SPI0_RXD, TOP_REG3, 19, 1, 0x68, 9,
- AON_MUX(0x0, "EXT_INT"), /* int3 */
- AON_MUX(0x1, "AGPIO"), /* agpio26 */
- AON_MUX(0x2, "nonAON"), /* pin8 */
- AON_MUX(0x3, "PCU"), /* test2 */
- TOP_MUX(0x0, "SPI0"), /* rxd */
- TOP_MUX(0x1, "ISP")), /* shutter_open */
- AON_PIN(KEY_COL0, TOP_REG3, 20, 1, 0x68, 18,
- AON_MUX(0x0, "KEY"), /* col0 */
- AON_MUX(0x1, "AGPIO"), /* agpio5 */
- AON_MUX(0x2, "nonAON"), /* pin9 */
- AON_MUX(0x3, "PCU"), /* test3 */
- TOP_MUX(0x0, "UART3"), /* rxd */
- TOP_MUX(0x1, "I2S0")), /* din1 */
- AON_PIN(KEY_COL1, TOP_REG3, 21, 2, 0x6c, 0,
- AON_MUX(0x0, "KEY"), /* col1 */
- AON_MUX(0x1, "AGPIO"), /* agpio6 */
- AON_MUX(0x2, "nonAON"), /* pin10 */
- TOP_MUX(0x0, "UART3"), /* txd */
- TOP_MUX(0x1, "I2S0"), /* din2 */
- TOP_MUX(0x2, "VGA")), /* scl */
- AON_PIN(KEY_COL2, TOP_REG3, 23, 2, 0x6c, 9,
- AON_MUX(0x0, "KEY"), /* col2 */
- AON_MUX(0x1, "AGPIO"), /* agpio7 */
- AON_MUX(0x2, "nonAON"), /* pin11 */
- TOP_MUX(0x0, "PWM"), /* out1 */
- TOP_MUX(0x1, "I2S0"), /* din3 */
- TOP_MUX(0x2, "VGA")), /* sda */
- AON_PIN(KEY_ROW0, 0, 0, 0, 0x6c, 18,
- AON_MUX(0x0, "KEY"), /* row0 */
- AON_MUX(0x1, "AGPIO"), /* agpio8 */
- AON_MUX(0x2, "nonAON"), /* pin33 */
- AON_MUX(0x3, "WD")), /* rst_b */
-
- /* aon_pmm_reg_1 */
- AON_PIN(KEY_ROW1, TOP_REG3, 25, 2, 0x70, 0,
- AON_MUX(0x0, "KEY"), /* row1 */
- AON_MUX(0x1, "AGPIO"), /* agpio9 */
- AON_MUX(0x2, "nonAON"), /* pin12 */
- TOP_MUX(0x0, "LCD"), /* port0 lcd_te */
- TOP_MUX(0x1, "I2S0"), /* dout2 */
- TOP_MUX(0x2, "PWM"), /* out2 */
- TOP_MUX(0x3, "VGA")), /* hs1 */
- AON_PIN(KEY_ROW2, TOP_REG3, 27, 2, 0x70, 9,
- AON_MUX(0x0, "KEY"), /* row2 */
- AON_MUX(0x1, "AGPIO"), /* agpio10 */
- AON_MUX(0x2, "nonAON"), /* pin13 */
- TOP_MUX(0x0, "LCD"), /* port1 lcd_te */
- TOP_MUX(0x1, "I2S0"), /* dout3 */
- TOP_MUX(0x2, "PWM"), /* out3 */
- TOP_MUX(0x3, "VGA")), /* vs1 */
- AON_PIN(HDMI_SCL, TOP_REG3, 29, 1, 0x70, 18,
- AON_MUX(0x0, "PCU"), /* test7 */
- AON_MUX(0x1, "AGPIO"), /* agpio3 */
- AON_MUX(0x2, "nonAON"), /* pin14 */
- TOP_MUX(0x0, "HDMI"), /* scl */
- TOP_MUX(0x1, "UART3")), /* rxd */
- AON_PIN(HDMI_SDA, TOP_REG3, 30, 1, 0x74, 0,
- AON_MUX(0x0, "PCU"), /* test8 */
- AON_MUX(0x1, "AGPIO"), /* agpio4 */
- AON_MUX(0x2, "nonAON"), /* pin15 */
- TOP_MUX(0x0, "HDMI"), /* sda */
- TOP_MUX(0x1, "UART3")), /* txd */
- AON_PIN(JTAG_TCK, TOP_REG7, 3, 1, 0x78, 18,
- AON_MUX(0x0, "JTAG"), /* tck */
- AON_MUX(0x1, "AGPIO"), /* agpio11 */
- AON_MUX(0x2, "nonAON"), /* pin22 */
- AON_MUX(0x3, "EXT_INT"), /* int4 */
- TOP_MUX(0x0, "SPI4"), /* clk */
- TOP_MUX(0x1, "UART1")), /* rxd */
- AON_PIN(JTAG_TRSTN, TOP_REG7, 4, 1, 0xac, 0,
- AON_MUX(0x0, "JTAG"), /* trstn */
- AON_MUX(0x1, "AGPIO"), /* agpio12 */
- AON_MUX(0x2, "nonAON"), /* pin23 */
- AON_MUX(0x3, "EXT_INT"), /* int5 */
- TOP_MUX(0x0, "SPI4"), /* cs */
- TOP_MUX(0x1, "UART1")), /* txd */
- AON_PIN(JTAG_TMS, TOP_REG7, 5, 1, 0xac, 9,
- AON_MUX(0x0, "JTAG"), /* tms */
- AON_MUX(0x1, "AGPIO"), /* agpio13 */
- AON_MUX(0x2, "nonAON"), /* pin24 */
- AON_MUX(0x3, "EXT_INT"), /* int6 */
- TOP_MUX(0x0, "SPI4"), /* txd */
- TOP_MUX(0x1, "UART2")), /* rxd */
- AON_PIN(JTAG_TDI, TOP_REG7, 6, 1, 0xac, 18,
- AON_MUX(0x0, "JTAG"), /* tdi */
- AON_MUX(0x1, "AGPIO"), /* agpio14 */
- AON_MUX(0x2, "nonAON"), /* pin25 */
- AON_MUX(0x3, "EXT_INT"), /* int7 */
- TOP_MUX(0x0, "SPI4"), /* rxd */
- TOP_MUX(0x1, "UART2")), /* txd */
- AON_PIN(JTAG_TDO, 0, 0, 0, 0xb0, 0,
- AON_MUX(0x0, "JTAG"), /* tdo */
- AON_MUX(0x1, "AGPIO"), /* agpio15 */
- AON_MUX(0x2, "nonAON")), /* pin26 */
- AON_PIN(I2C0_SCL, 0, 0, 0, 0xb0, 9,
- AON_MUX(0x0, "I2C0"), /* scl */
- AON_MUX(0x1, "AGPIO"), /* agpio16 */
- AON_MUX(0x2, "nonAON")), /* pin28 */
- AON_PIN(I2C0_SDA, 0, 0, 0, 0xb0, 18,
- AON_MUX(0x0, "I2C0"), /* sda */
- AON_MUX(0x1, "AGPIO"), /* agpio17 */
- AON_MUX(0x2, "nonAON")), /* pin29 */
- AON_PIN(I2C1_SCL, TOP_REG8, 4, 1, 0xb4, 0,
- AON_MUX(0x0, "I2C1"), /* scl */
- AON_MUX(0x1, "AGPIO"), /* agpio18 */
- AON_MUX(0x2, "nonAON"), /* pin30 */
- TOP_MUX(0x0, "LCD")), /* port0 lcd_te */
- AON_PIN(I2C1_SDA, TOP_REG8, 5, 1, 0xb4, 9,
- AON_MUX(0x0, "I2C1"), /* sda */
- AON_MUX(0x1, "AGPIO"), /* agpio19 */
- AON_MUX(0x2, "nonAON"), /* pin31 */
- TOP_MUX(0x0, "LCD")), /* port1 lcd_te */
- ZX_RESERVED(AON_RESERVED2),
- ZX_RESERVED(AON_RESERVED3),
- ZX_RESERVED(AON_RESERVED4),
-
- /* aon_pmm_reg_2 */
- AON_PIN(SPI1_CLK, TOP_REG2, 6, 3, 0x40, 9,
- AON_MUX(0x0, "EXT_INT"), /* int0 */
- AON_MUX(0x1, "PCU"), /* test12 */
- AON_MUX(0x2, "nonAON"), /* pin39 */
- TOP_MUX(0x0, "SPI1"), /* clk */
- TOP_MUX(0x1, "PCM"), /* clk */
- TOP_MUX(0x2, "BGPIO"), /* gpio35 */
- TOP_MUX(0x3, "I2C4"), /* scl */
- TOP_MUX(0x4, "I2S1"), /* mclk */
- TOP_MUX(0x5, "ISP")), /* flash_trig */
- AON_PIN(SPI1_CS, TOP_REG2, 9, 3, 0x40, 18,
- AON_MUX(0x0, "EXT_INT"), /* int1 */
- AON_MUX(0x1, "PCU"), /* test13 */
- AON_MUX(0x2, "nonAON"), /* pin40 */
- TOP_MUX(0x0, "SPI1"), /* cs */
- TOP_MUX(0x1, "PCM"), /* fs */
- TOP_MUX(0x2, "BGPIO"), /* gpio36 */
- TOP_MUX(0x3, "I2C4"), /* sda */
- TOP_MUX(0x4, "I2S1"), /* bclk */
- TOP_MUX(0x5, "ISP")), /* prelight_trig */
- AON_PIN(SPI1_TXD, TOP_REG2, 12, 3, 0x44, 0,
- AON_MUX(0x0, "EXT_INT"), /* int2 */
- AON_MUX(0x1, "PCU"), /* test14 */
- AON_MUX(0x2, "nonAON"), /* pin41 */
- TOP_MUX(0x0, "SPI1"), /* txd */
- TOP_MUX(0x1, "PCM"), /* txd */
- TOP_MUX(0x2, "BGPIO"), /* gpio37 */
- TOP_MUX(0x3, "UART5"), /* rxd */
- TOP_MUX(0x4, "I2S1"), /* ws */
- TOP_MUX(0x5, "ISP")), /* shutter_trig */
- AON_PIN(SPI1_RXD, TOP_REG2, 15, 3, 0x44, 9,
- AON_MUX(0x0, "EXT_INT"), /* int3 */
- AON_MUX(0x1, "PCU"), /* test15 */
- AON_MUX(0x2, "nonAON"), /* pin42 */
- TOP_MUX(0x0, "SPI1"), /* rxd */
- TOP_MUX(0x1, "PCM"), /* rxd */
- TOP_MUX(0x2, "BGPIO"), /* gpio38 */
- TOP_MUX(0x3, "UART5"), /* txd */
- TOP_MUX(0x4, "I2S1"), /* dout0 */
- TOP_MUX(0x5, "ISP")), /* shutter_open */
- ZX_RESERVED(AON_RESERVED5),
- ZX_RESERVED(AON_RESERVED6),
- AON_PIN(AUDIO_DET, TOP_REG3, 3, 2, 0x48, 18,
- AON_MUX(0x0, "PCU"), /* test4 */
- AON_MUX(0x1, "AGPIO"), /* agpio27 */
- AON_MUX(0x2, "nonAON"), /* pin2 */
- AON_MUX(0x3, "EXT_INT"), /* int16 */
- TOP_MUX(0x0, "AUDIO"), /* detect */
- TOP_MUX(0x1, "I2C2"), /* scl */
- TOP_MUX(0x2, "SPI2")), /* clk */
- AON_PIN(SPDIF_OUT, TOP_REG3, 14, 2, 0x78, 9,
- AON_MUX(0x0, "PCU"), /* test5 */
- AON_MUX(0x1, "AGPIO"), /* agpio22 */
- AON_MUX(0x2, "nonAON"), /* pin4 */
- TOP_MUX(0x0, "SPDIF"), /* out */
- TOP_MUX(0x1, "PWM"), /* out0 */
- TOP_MUX(0x2, "ISP")), /* fl_trig */
- AON_PIN(HDMI_CEC, 0, 0, 0, 0x74, 9,
- AON_MUX(0x0, "PCU"), /* test9 */
- AON_MUX(0x1, "AGPIO"), /* agpio1 */
- AON_MUX(0x2, "nonAON")), /* pin16 */
- AON_PIN(HDMI_HPD, 0, 0, 0, 0x74, 18,
- AON_MUX(0x0, "PCU"), /* test10 */
- AON_MUX(0x1, "AGPIO"), /* agpio2 */
- AON_MUX(0x2, "nonAON")), /* pin17 */
- AON_PIN(GMAC_25M_OUT, 0, 0, 0, 0x78, 0,
- AON_MUX(0x0, "PCU"), /* test11 */
- AON_MUX(0x1, "AGPIO"), /* agpio31 */
- AON_MUX(0x2, "nonAON")), /* pin43 */
- AON_PIN(BOOT_SEL0, 0, 0, 0, 0xc0, 9,
- AON_MUX(0x0, "BOOT"), /* sel0 */
- AON_MUX(0x1, "AGPIO"), /* agpio18 */
- AON_MUX(0x2, "nonAON")), /* pin18 */
- AON_PIN(BOOT_SEL1, 0, 0, 0, 0xc0, 18,
- AON_MUX(0x0, "BOOT"), /* sel1 */
- AON_MUX(0x1, "AGPIO"), /* agpio19 */
- AON_MUX(0x2, "nonAON")), /* pin19 */
- AON_PIN(BOOT_SEL2, 0, 0, 0, 0xc4, 0,
- AON_MUX(0x0, "BOOT"), /* sel2 */
- AON_MUX(0x1, "AGPIO"), /* agpio20 */
- AON_MUX(0x2, "nonAON")), /* pin20 */
- AON_PIN(DEEP_SLEEP_OUT_N, 0, 0, 0, 0xc4, 9,
- AON_MUX(0x0, "DEEPSLP"), /* deep sleep out_n */
- AON_MUX(0x1, "AGPIO"), /* agpio21 */
- AON_MUX(0x2, "nonAON")), /* pin21 */
- ZX_RESERVED(AON_RESERVED7),
-
- /* top_pmm_reg_0 */
- TOP_PIN(GMII_GTX_CLK, TOP_REG0, 0, 2, 0x10, 0,
- TOP_MUX(0x0, "GMII"), /* gtx_clk */
- TOP_MUX(0x1, "DVI0"), /* clk */
- TOP_MUX(0x2, "BGPIO")), /* gpio0 */
- TOP_PIN(GMII_TX_CLK, TOP_REG0, 2, 2, 0x10, 9,
- TOP_MUX(0x0, "GMII"), /* tx_clk */
- TOP_MUX(0x1, "DVI0"), /* vs */
- TOP_MUX(0x2, "BGPIO")), /* gpio1 */
- TOP_PIN(GMII_TXD0, TOP_REG0, 4, 2, 0x10, 18,
- TOP_MUX(0x0, "GMII"), /* txd0 */
- TOP_MUX(0x1, "DVI0"), /* hs */
- TOP_MUX(0x2, "BGPIO")), /* gpio2 */
- TOP_PIN(GMII_TXD1, TOP_REG0, 6, 2, 0x14, 0,
- TOP_MUX(0x0, "GMII"), /* txd1 */
- TOP_MUX(0x1, "DVI0"), /* d0 */
- TOP_MUX(0x2, "BGPIO")), /* gpio3 */
- TOP_PIN(GMII_TXD2, TOP_REG0, 8, 2, 0x14, 9,
- TOP_MUX(0x0, "GMII"), /* txd2 */
- TOP_MUX(0x1, "DVI0"), /* d1 */
- TOP_MUX(0x2, "BGPIO")), /* gpio4 */
- TOP_PIN(GMII_TXD3, TOP_REG0, 10, 2, 0x14, 18,
- TOP_MUX(0x0, "GMII"), /* txd3 */
- TOP_MUX(0x1, "DVI0"), /* d2 */
- TOP_MUX(0x2, "BGPIO")), /* gpio5 */
- TOP_PIN(GMII_TXD4, TOP_REG0, 12, 2, 0x18, 0,
- TOP_MUX(0x0, "GMII"), /* txd4 */
- TOP_MUX(0x1, "DVI0"), /* d3 */
- TOP_MUX(0x2, "BGPIO")), /* gpio6 */
- TOP_PIN(GMII_TXD5, TOP_REG0, 14, 2, 0x18, 9,
- TOP_MUX(0x0, "GMII"), /* txd5 */
- TOP_MUX(0x1, "DVI0"), /* d4 */
- TOP_MUX(0x2, "BGPIO")), /* gpio7 */
- TOP_PIN(GMII_TXD6, TOP_REG0, 16, 2, 0x18, 18,
- TOP_MUX(0x0, "GMII"), /* txd6 */
- TOP_MUX(0x1, "DVI0"), /* d5 */
- TOP_MUX(0x2, "BGPIO")), /* gpio8 */
- TOP_PIN(GMII_TXD7, TOP_REG0, 18, 2, 0x1c, 0,
- TOP_MUX(0x0, "GMII"), /* txd7 */
- TOP_MUX(0x1, "DVI0"), /* d6 */
- TOP_MUX(0x2, "BGPIO")), /* gpio9 */
- TOP_PIN(GMII_TX_ER, TOP_REG0, 20, 2, 0x1c, 9,
- TOP_MUX(0x0, "GMII"), /* tx_er */
- TOP_MUX(0x1, "DVI0"), /* d7 */
- TOP_MUX(0x2, "BGPIO")), /* gpio10 */
- TOP_PIN(GMII_TX_EN, TOP_REG0, 22, 2, 0x1c, 18,
- TOP_MUX(0x0, "GMII"), /* tx_en */
- TOP_MUX(0x1, "DVI0"), /* d8 */
- TOP_MUX(0x3, "BGPIO")), /* gpio11 */
- TOP_PIN(GMII_RX_CLK, TOP_REG0, 24, 2, 0x20, 0,
- TOP_MUX(0x0, "GMII"), /* rx_clk */
- TOP_MUX(0x1, "DVI0"), /* d9 */
- TOP_MUX(0x3, "BGPIO")), /* gpio12 */
- TOP_PIN(GMII_RXD0, TOP_REG0, 26, 2, 0x20, 9,
- TOP_MUX(0x0, "GMII"), /* rxd0 */
- TOP_MUX(0x1, "DVI0"), /* d10 */
- TOP_MUX(0x3, "BGPIO")), /* gpio13 */
- TOP_PIN(GMII_RXD1, TOP_REG0, 28, 2, 0x20, 18,
- TOP_MUX(0x0, "GMII"), /* rxd1 */
- TOP_MUX(0x1, "DVI0"), /* d11 */
- TOP_MUX(0x2, "BGPIO")), /* gpio14 */
- TOP_PIN(GMII_RXD2, TOP_REG0, 30, 2, 0x24, 0,
- TOP_MUX(0x0, "GMII"), /* rxd2 */
- TOP_MUX(0x1, "DVI1"), /* clk */
- TOP_MUX(0x2, "BGPIO")), /* gpio15 */
-
- /* top_pmm_reg_1 */
- TOP_PIN(GMII_RXD3, TOP_REG1, 0, 2, 0x24, 9,
- TOP_MUX(0x0, "GMII"), /* rxd3 */
- TOP_MUX(0x1, "DVI1"), /* hs */
- TOP_MUX(0x2, "BGPIO")), /* gpio16 */
- TOP_PIN(GMII_RXD4, TOP_REG1, 2, 2, 0x24, 18,
- TOP_MUX(0x0, "GMII"), /* rxd4 */
- TOP_MUX(0x1, "DVI1"), /* vs */
- TOP_MUX(0x2, "BGPIO")), /* gpio17 */
- TOP_PIN(GMII_RXD5, TOP_REG1, 4, 2, 0x28, 0,
- TOP_MUX(0x0, "GMII"), /* rxd5 */
- TOP_MUX(0x1, "DVI1"), /* d0 */
- TOP_MUX(0x2, "BGPIO"), /* gpio18 */
- TOP_MUX(0x3, "TSI0")), /* dat0 */
- TOP_PIN(GMII_RXD6, TOP_REG1, 6, 2, 0x28, 9,
- TOP_MUX(0x0, "GMII"), /* rxd6 */
- TOP_MUX(0x1, "DVI1"), /* d1 */
- TOP_MUX(0x2, "BGPIO"), /* gpio19 */
- TOP_MUX(0x3, "TSI0")), /* clk */
- TOP_PIN(GMII_RXD7, TOP_REG1, 8, 2, 0x28, 18,
- TOP_MUX(0x0, "GMII"), /* rxd7 */
- TOP_MUX(0x1, "DVI1"), /* d2 */
- TOP_MUX(0x2, "BGPIO"), /* gpio20 */
- TOP_MUX(0x3, "TSI0")), /* sync */
- TOP_PIN(GMII_RX_ER, TOP_REG1, 10, 2, 0x2c, 0,
- TOP_MUX(0x0, "GMII"), /* rx_er */
- TOP_MUX(0x1, "DVI1"), /* d3 */
- TOP_MUX(0x2, "BGPIO"), /* gpio21 */
- TOP_MUX(0x3, "TSI0")), /* valid */
- TOP_PIN(GMII_RX_DV, TOP_REG1, 12, 2, 0x2c, 9,
- TOP_MUX(0x0, "GMII"), /* rx_dv */
- TOP_MUX(0x1, "DVI1"), /* d4 */
- TOP_MUX(0x2, "BGPIO"), /* gpio22 */
- TOP_MUX(0x3, "TSI1")), /* dat0 */
- TOP_PIN(GMII_COL, TOP_REG1, 14, 2, 0x2c, 18,
- TOP_MUX(0x0, "GMII"), /* col */
- TOP_MUX(0x1, "DVI1"), /* d5 */
- TOP_MUX(0x2, "BGPIO"), /* gpio23 */
- TOP_MUX(0x3, "TSI1")), /* clk */
- TOP_PIN(GMII_CRS, TOP_REG1, 16, 2, 0x30, 0,
- TOP_MUX(0x0, "GMII"), /* crs */
- TOP_MUX(0x1, "DVI1"), /* d6 */
- TOP_MUX(0x2, "BGPIO"), /* gpio24 */
- TOP_MUX(0x3, "TSI1")), /* sync */
- TOP_PIN(GMII_MDC, TOP_REG1, 18, 2, 0x30, 9,
- TOP_MUX(0x0, "GMII"), /* mdc */
- TOP_MUX(0x1, "DVI1"), /* d7 */
- TOP_MUX(0x2, "BGPIO"), /* gpio25 */
- TOP_MUX(0x3, "TSI1")), /* valid */
- TOP_PIN(GMII_MDIO, TOP_REG1, 20, 1, 0x30, 18,
- TOP_MUX(0x0, "GMII"), /* mdio */
- TOP_MUX(0x2, "BGPIO")), /* gpio26 */
- TOP_PIN(SDIO1_CLK, TOP_REG1, 21, 2, 0x34, 18,
- TOP_MUX(0x0, "SDIO1"), /* clk */
- TOP_MUX(0x1, "USIM0"), /* clk */
- TOP_MUX(0x2, "BGPIO"), /* gpio27 */
- TOP_MUX(0x3, "SPINOR")), /* clk */
- TOP_PIN(SDIO1_CMD, TOP_REG1, 23, 2, 0x38, 0,
- TOP_MUX(0x0, "SDIO1"), /* cmd */
- TOP_MUX(0x1, "USIM0"), /* cd */
- TOP_MUX(0x2, "BGPIO"), /* gpio28 */
- TOP_MUX(0x3, "SPINOR")), /* cs */
- TOP_PIN(SDIO1_DATA0, TOP_REG1, 25, 2, 0x38, 9,
- TOP_MUX(0x0, "SDIO1"), /* dat0 */
- TOP_MUX(0x1, "USIM0"), /* rst */
- TOP_MUX(0x2, "BGPIO"), /* gpio29 */
- TOP_MUX(0x3, "SPINOR")), /* dq0 */
- TOP_PIN(SDIO1_DATA1, TOP_REG1, 27, 2, 0x38, 18,
- TOP_MUX(0x0, "SDIO1"), /* dat1 */
- TOP_MUX(0x1, "USIM0"), /* data */
- TOP_MUX(0x2, "BGPIO"), /* gpio30 */
- TOP_MUX(0x3, "SPINOR")), /* dq1 */
- TOP_PIN(SDIO1_DATA2, TOP_REG1, 29, 2, 0x3c, 0,
- TOP_MUX(0x0, "SDIO1"), /* dat2 */
- TOP_MUX(0x1, "BGPIO"), /* gpio31 */
- TOP_MUX(0x2, "SPINOR")), /* dq2 */
-
- /* top_pmm_reg_2 */
- TOP_PIN(SDIO1_DATA3, TOP_REG2, 0, 2, 0x3c, 9,
- TOP_MUX(0x0, "SDIO1"), /* dat3 */
- TOP_MUX(0x1, "BGPIO"), /* gpio32 */
- TOP_MUX(0x2, "SPINOR")), /* dq3 */
- TOP_PIN(SDIO1_CD, TOP_REG2, 2, 2, 0x3c, 18,
- TOP_MUX(0x0, "SDIO1"), /* cd */
- TOP_MUX(0x1, "BGPIO"), /* gpio33 */
- TOP_MUX(0x2, "ISP")), /* fl_trig */
- TOP_PIN(SDIO1_WP, TOP_REG2, 4, 2, 0x40, 0,
- TOP_MUX(0x0, "SDIO1"), /* wp */
- TOP_MUX(0x1, "BGPIO"), /* gpio34 */
- TOP_MUX(0x2, "ISP")), /* ref_clk */
- TOP_PIN(USIM1_CD, TOP_REG2, 22, 3, 0x44, 18,
- TOP_MUX(0x0, "USIM1"), /* cd */
- TOP_MUX(0x1, "UART4"), /* rxd */
- TOP_MUX(0x2, "BGPIO"), /* gpio39 */
- TOP_MUX(0x3, "SPI3"), /* clk */
- TOP_MUX(0x4, "I2S0"), /* bclk */
- TOP_MUX(0x5, "B_DVI0")), /* d8 */
- TOP_PIN(USIM1_CLK, TOP_REG2, 25, 3, 0x4c, 18,
- TOP_MUX(0x0, "USIM1"), /* clk */
- TOP_MUX(0x1, "UART4"), /* txd */
- TOP_MUX(0x2, "BGPIO"), /* gpio40 */
- TOP_MUX(0x3, "SPI3"), /* cs */
- TOP_MUX(0x4, "I2S0"), /* ws */
- TOP_MUX(0x5, "B_DVI0")), /* d9 */
- TOP_PIN(USIM1_RST, TOP_REG2, 28, 3, 0x4c, 0,
- TOP_MUX(0x0, "USIM1"), /* rst */
- TOP_MUX(0x1, "UART4"), /* cts */
- TOP_MUX(0x2, "BGPIO"), /* gpio41 */
- TOP_MUX(0x3, "SPI3"), /* txd */
- TOP_MUX(0x4, "I2S0"), /* dout0 */
- TOP_MUX(0x5, "B_DVI0")), /* d10 */
-
- /* top_pmm_reg_3 */
- TOP_PIN(USIM1_DATA, TOP_REG3, 0, 3, 0x4c, 9,
- TOP_MUX(0x0, "USIM1"), /* dat */
- TOP_MUX(0x1, "UART4"), /* rst */
- TOP_MUX(0x2, "BGPIO"), /* gpio42 */
- TOP_MUX(0x3, "SPI3"), /* rxd */
- TOP_MUX(0x4, "I2S0"), /* din0 */
- TOP_MUX(0x5, "B_DVI0")), /* d11 */
- TOP_PIN(SDIO0_CLK, TOP_REG3, 6, 1, 0x58, 0,
- TOP_MUX(0x0, "SDIO0"), /* clk */
- TOP_MUX(0x1, "GPIO")), /* gpio43 */
- TOP_PIN(SDIO0_CMD, TOP_REG3, 7, 1, 0x58, 9,
- TOP_MUX(0x0, "SDIO0"), /* cmd */
- TOP_MUX(0x1, "GPIO")), /* gpio44 */
- TOP_PIN(SDIO0_DATA0, TOP_REG3, 8, 1, 0x58, 18,
- TOP_MUX(0x0, "SDIO0"), /* dat0 */
- TOP_MUX(0x1, "GPIO")), /* gpio45 */
- TOP_PIN(SDIO0_DATA1, TOP_REG3, 9, 1, 0x5c, 0,
- TOP_MUX(0x0, "SDIO0"), /* dat1 */
- TOP_MUX(0x1, "GPIO")), /* gpio46 */
- TOP_PIN(SDIO0_DATA2, TOP_REG3, 10, 1, 0x5c, 9,
- TOP_MUX(0x0, "SDIO0"), /* dat2 */
- TOP_MUX(0x1, "GPIO")), /* gpio47 */
- TOP_PIN(SDIO0_DATA3, TOP_REG3, 11, 1, 0x5c, 18,
- TOP_MUX(0x0, "SDIO0"), /* dat3 */
- TOP_MUX(0x1, "GPIO")), /* gpio48 */
- TOP_PIN(SDIO0_CD, TOP_REG3, 12, 1, 0x60, 0,
- TOP_MUX(0x0, "SDIO0"), /* cd */
- TOP_MUX(0x1, "GPIO")), /* gpio49 */
- TOP_PIN(SDIO0_WP, TOP_REG3, 13, 1, 0x60, 9,
- TOP_MUX(0x0, "SDIO0"), /* wp */
- TOP_MUX(0x1, "GPIO")), /* gpio50 */
-
- /* top_pmm_reg_4 */
- TOP_PIN(TSI0_DATA0, TOP_REG4, 0, 2, 0x60, 18,
- TOP_MUX(0x0, "TSI0"), /* dat0 */
- TOP_MUX(0x1, "LCD"), /* clk */
- TOP_MUX(0x2, "BGPIO")), /* gpio51 */
- TOP_PIN(SPINOR_CLK, TOP_REG4, 2, 2, 0xa8, 18,
- TOP_MUX(0x0, "SPINOR"), /* clk */
- TOP_MUX(0x1, "TSI0"), /* dat1 */
- TOP_MUX(0x2, "LCD"), /* dat0 */
- TOP_MUX(0x3, "BGPIO")), /* gpio52 */
- TOP_PIN(TSI2_DATA, TOP_REG4, 4, 2, 0x7c, 0,
- TOP_MUX(0x0, "TSI2"), /* dat */
- TOP_MUX(0x1, "TSI0"), /* dat2 */
- TOP_MUX(0x2, "LCD"), /* dat1 */
- TOP_MUX(0x3, "BGPIO")), /* gpio53 */
- TOP_PIN(TSI2_CLK, TOP_REG4, 6, 2, 0x7c, 9,
- TOP_MUX(0x0, "TSI2"), /* clk */
- TOP_MUX(0x1, "TSI0"), /* dat3 */
- TOP_MUX(0x2, "LCD"), /* dat2 */
- TOP_MUX(0x3, "BGPIO")), /* gpio54 */
- TOP_PIN(TSI2_SYNC, TOP_REG4, 8, 2, 0x7c, 18,
- TOP_MUX(0x0, "TSI2"), /* sync */
- TOP_MUX(0x1, "TSI0"), /* dat4 */
- TOP_MUX(0x2, "LCD"), /* dat3 */
- TOP_MUX(0x3, "BGPIO")), /* gpio55 */
- TOP_PIN(TSI2_VALID, TOP_REG4, 10, 2, 0x80, 0,
- TOP_MUX(0x0, "TSI2"), /* valid */
- TOP_MUX(0x1, "TSI0"), /* dat5 */
- TOP_MUX(0x2, "LCD"), /* dat4 */
- TOP_MUX(0x3, "BGPIO")), /* gpio56 */
- TOP_PIN(SPINOR_CS, TOP_REG4, 12, 2, 0x80, 9,
- TOP_MUX(0x0, "SPINOR"), /* cs */
- TOP_MUX(0x1, "TSI0"), /* dat6 */
- TOP_MUX(0x2, "LCD"), /* dat5 */
- TOP_MUX(0x3, "BGPIO")), /* gpio57 */
- TOP_PIN(SPINOR_DQ0, TOP_REG4, 14, 2, 0x80, 18,
- TOP_MUX(0x0, "SPINOR"), /* dq0 */
- TOP_MUX(0x1, "TSI0"), /* dat7 */
- TOP_MUX(0x2, "LCD"), /* dat6 */
- TOP_MUX(0x3, "BGPIO")), /* gpio58 */
- TOP_PIN(SPINOR_DQ1, TOP_REG4, 16, 2, 0x84, 0,
- TOP_MUX(0x0, "SPINOR"), /* dq1 */
- TOP_MUX(0x1, "TSI0"), /* clk */
- TOP_MUX(0x2, "LCD"), /* dat7 */
- TOP_MUX(0x3, "BGPIO")), /* gpio59 */
- TOP_PIN(SPINOR_DQ2, TOP_REG4, 18, 2, 0x84, 9,
- TOP_MUX(0x0, "SPINOR"), /* dq2 */
- TOP_MUX(0x1, "TSI0"), /* sync */
- TOP_MUX(0x2, "LCD"), /* dat8 */
- TOP_MUX(0x3, "BGPIO")), /* gpio60 */
- TOP_PIN(SPINOR_DQ3, TOP_REG4, 20, 2, 0x84, 18,
- TOP_MUX(0x0, "SPINOR"), /* dq3 */
- TOP_MUX(0x1, "TSI0"), /* valid */
- TOP_MUX(0x2, "LCD"), /* dat9 */
- TOP_MUX(0x3, "BGPIO")), /* gpio61 */
- TOP_PIN(VGA_HS, TOP_REG4, 22, 3, 0x88, 0,
- TOP_MUX(0x0, "VGA"), /* hs */
- TOP_MUX(0x1, "TSI1"), /* dat0 */
- TOP_MUX(0x2, "LCD"), /* dat10 */
- TOP_MUX(0x3, "BGPIO"), /* gpio62 */
- TOP_MUX(0x4, "I2S1"), /* din1 */
- TOP_MUX(0x5, "B_DVI0")), /* clk */
- TOP_PIN(VGA_VS, TOP_REG4, 25, 3, 0x88, 9,
- TOP_MUX(0x0, "VGA"), /* vs0 */
- TOP_MUX(0x1, "TSI1"), /* dat1 */
- TOP_MUX(0x2, "LCD"), /* dat11 */
- TOP_MUX(0x3, "BGPIO"), /* gpio63 */
- TOP_MUX(0x4, "I2S1"), /* din2 */
- TOP_MUX(0x5, "B_DVI0")), /* vs */
- TOP_PIN(TSI3_DATA, TOP_REG4, 28, 3, 0x88, 18,
- TOP_MUX(0x0, "TSI3"), /* dat */
- TOP_MUX(0x1, "TSI1"), /* dat2 */
- TOP_MUX(0x2, "LCD"), /* dat12 */
- TOP_MUX(0x3, "BGPIO"), /* gpio64 */
- TOP_MUX(0x4, "I2S1"), /* din3 */
- TOP_MUX(0x5, "B_DVI0")), /* hs */
-
- /* top_pmm_reg_5 */
- TOP_PIN(TSI3_CLK, TOP_REG5, 0, 3, 0x8c, 0,
- TOP_MUX(0x0, "TSI3"), /* clk */
- TOP_MUX(0x1, "TSI1"), /* dat3 */
- TOP_MUX(0x2, "LCD"), /* dat13 */
- TOP_MUX(0x3, "BGPIO"), /* gpio65 */
- TOP_MUX(0x4, "I2S1"), /* dout1 */
- TOP_MUX(0x5, "B_DVI0")), /* d0 */
- TOP_PIN(TSI3_SYNC, TOP_REG5, 3, 3, 0x8c, 9,
- TOP_MUX(0x0, "TSI3"), /* sync */
- TOP_MUX(0x1, "TSI1"), /* dat4 */
- TOP_MUX(0x2, "LCD"), /* dat14 */
- TOP_MUX(0x3, "BGPIO"), /* gpio66 */
- TOP_MUX(0x4, "I2S1"), /* dout2 */
- TOP_MUX(0x5, "B_DVI0")), /* d1 */
- TOP_PIN(TSI3_VALID, TOP_REG5, 6, 3, 0x8c, 18,
- TOP_MUX(0x0, "TSI3"), /* valid */
- TOP_MUX(0x1, "TSI1"), /* dat5 */
- TOP_MUX(0x2, "LCD"), /* dat15 */
- TOP_MUX(0x3, "BGPIO"), /* gpio67 */
- TOP_MUX(0x4, "I2S1"), /* dout3 */
- TOP_MUX(0x5, "B_DVI0")), /* d2 */
- TOP_PIN(I2S1_WS, TOP_REG5, 9, 3, 0x90, 0,
- TOP_MUX(0x0, "I2S1"), /* ws */
- TOP_MUX(0x1, "TSI1"), /* dat6 */
- TOP_MUX(0x2, "LCD"), /* dat16 */
- TOP_MUX(0x3, "BGPIO"), /* gpio68 */
- TOP_MUX(0x4, "VGA"), /* scl */
- TOP_MUX(0x5, "B_DVI0")), /* d3 */
- TOP_PIN(I2S1_BCLK, TOP_REG5, 12, 3, 0x90, 9,
- TOP_MUX(0x0, "I2S1"), /* bclk */
- TOP_MUX(0x1, "TSI1"), /* dat7 */
- TOP_MUX(0x2, "LCD"), /* dat17 */
- TOP_MUX(0x3, "BGPIO"), /* gpio69 */
- TOP_MUX(0x4, "VGA"), /* sda */
- TOP_MUX(0x5, "B_DVI0")), /* d4 */
- TOP_PIN(I2S1_MCLK, TOP_REG5, 15, 2, 0x90, 18,
- TOP_MUX(0x0, "I2S1"), /* mclk */
- TOP_MUX(0x1, "TSI1"), /* clk */
- TOP_MUX(0x2, "LCD"), /* dat18 */
- TOP_MUX(0x3, "BGPIO")), /* gpio70 */
- TOP_PIN(I2S1_DIN0, TOP_REG5, 17, 2, 0x94, 0,
- TOP_MUX(0x0, "I2S1"), /* din0 */
- TOP_MUX(0x1, "TSI1"), /* sync */
- TOP_MUX(0x2, "LCD"), /* dat19 */
- TOP_MUX(0x3, "BGPIO")), /* gpio71 */
- TOP_PIN(I2S1_DOUT0, TOP_REG5, 19, 2, 0x94, 9,
- TOP_MUX(0x0, "I2S1"), /* dout0 */
- TOP_MUX(0x1, "TSI1"), /* valid */
- TOP_MUX(0x2, "LCD"), /* dat20 */
- TOP_MUX(0x3, "BGPIO")), /* gpio72 */
- TOP_PIN(SPI3_CLK, TOP_REG5, 21, 3, 0x94, 18,
- TOP_MUX(0x0, "SPI3"), /* clk */
- TOP_MUX(0x1, "TSO1"), /* clk */
- TOP_MUX(0x2, "LCD"), /* dat21 */
- TOP_MUX(0x3, "BGPIO"), /* gpio73 */
- TOP_MUX(0x4, "UART5"), /* rxd */
- TOP_MUX(0x5, "PCM"), /* fs */
- TOP_MUX(0x6, "I2S0"), /* din1 */
- TOP_MUX(0x7, "B_DVI0")), /* d5 */
- TOP_PIN(SPI3_CS, TOP_REG5, 24, 3, 0x98, 0,
- TOP_MUX(0x0, "SPI3"), /* cs */
- TOP_MUX(0x1, "TSO1"), /* dat0 */
- TOP_MUX(0x2, "LCD"), /* dat22 */
- TOP_MUX(0x3, "BGPIO"), /* gpio74 */
- TOP_MUX(0x4, "UART5"), /* txd */
- TOP_MUX(0x5, "PCM"), /* clk */
- TOP_MUX(0x6, "I2S0"), /* din2 */
- TOP_MUX(0x7, "B_DVI0")), /* d6 */
- TOP_PIN(SPI3_TXD, TOP_REG5, 27, 3, 0x98, 9,
- TOP_MUX(0x0, "SPI3"), /* txd */
- TOP_MUX(0x1, "TSO1"), /* dat1 */
- TOP_MUX(0x2, "LCD"), /* dat23 */
- TOP_MUX(0x3, "BGPIO"), /* gpio75 */
- TOP_MUX(0x4, "UART5"), /* cts */
- TOP_MUX(0x5, "PCM"), /* txd */
- TOP_MUX(0x6, "I2S0"), /* din3 */
- TOP_MUX(0x7, "B_DVI0")), /* d7 */
- TOP_PIN(NAND_LDO_MS18_SEL, TOP_REG5, 30, 1, 0xe4, 0,
- TOP_MUX(0x0, "NAND"), /* ldo_ms18_sel */
- TOP_MUX(0x1, "BGPIO")), /* gpio99 */
-
- /* top_pmm_reg_6 */
- TOP_PIN(SPI3_RXD, TOP_REG6, 0, 3, 0x98, 18,
- TOP_MUX(0x0, "SPI3"), /* rxd */
- TOP_MUX(0x1, "TSO1"), /* dat2 */
- TOP_MUX(0x2, "LCD"), /* stvu_vsync */
- TOP_MUX(0x3, "BGPIO"), /* gpio76 */
- TOP_MUX(0x4, "UART5"), /* rts */
- TOP_MUX(0x5, "PCM"), /* rxd */
- TOP_MUX(0x6, "I2S0"), /* dout1 */
- TOP_MUX(0x7, "B_DVI1")), /* clk */
- TOP_PIN(I2S0_MCLK, TOP_REG6, 3, 3, 0x9c, 0,
- TOP_MUX(0x0, "I2S0"), /* mclk */
- TOP_MUX(0x1, "TSO1"), /* dat3 */
- TOP_MUX(0x2, "LCD"), /* stvd */
- TOP_MUX(0x3, "BGPIO"), /* gpio77 */
- TOP_MUX(0x4, "USIM0"), /* cd */
- TOP_MUX(0x5, "B_DVI1")), /* vs */
- TOP_PIN(I2S0_BCLK, TOP_REG6, 6, 3, 0x9c, 9,
- TOP_MUX(0x0, "I2S0"), /* bclk */
- TOP_MUX(0x1, "TSO1"), /* dat4 */
- TOP_MUX(0x2, "LCD"), /* sthl_hsync */
- TOP_MUX(0x3, "BGPIO"), /* gpio78 */
- TOP_MUX(0x4, "USIM0"), /* clk */
- TOP_MUX(0x5, "B_DVI1")), /* hs */
- TOP_PIN(I2S0_WS, TOP_REG6, 9, 3, 0x9c, 18,
- TOP_MUX(0x0, "I2S0"), /* ws */
- TOP_MUX(0x1, "TSO1"), /* dat5 */
- TOP_MUX(0x2, "LCD"), /* sthr */
- TOP_MUX(0x3, "BGPIO"), /* gpio79 */
- TOP_MUX(0x4, "USIM0"), /* rst */
- TOP_MUX(0x5, "B_DVI1")), /* d0 */
- TOP_PIN(I2S0_DIN0, TOP_REG6, 12, 3, 0xa0, 0,
- TOP_MUX(0x0, "I2S0"), /* din0 */
- TOP_MUX(0x1, "TSO1"), /* dat6 */
- TOP_MUX(0x2, "LCD"), /* oev_dataen */
- TOP_MUX(0x3, "BGPIO"), /* gpio80 */
- TOP_MUX(0x4, "USIM0"), /* dat */
- TOP_MUX(0x5, "B_DVI1")), /* d1 */
- TOP_PIN(I2S0_DOUT0, TOP_REG6, 15, 2, 0xa0, 9,
- TOP_MUX(0x0, "I2S0"), /* dout0 */
- TOP_MUX(0x1, "TSO1"), /* dat7 */
- TOP_MUX(0x2, "LCD"), /* ckv */
- TOP_MUX(0x3, "BGPIO")), /* gpio81 */
- TOP_PIN(I2C5_SCL, TOP_REG6, 17, 3, 0xa0, 18,
- TOP_MUX(0x0, "I2C5"), /* scl */
- TOP_MUX(0x1, "TSO1"), /* sync */
- TOP_MUX(0x2, "LCD"), /* ld */
- TOP_MUX(0x3, "BGPIO"), /* gpio82 */
- TOP_MUX(0x4, "PWM"), /* out2 */
- TOP_MUX(0x5, "I2S0"), /* dout2 */
- TOP_MUX(0x6, "B_DVI1")), /* d2 */
- TOP_PIN(I2C5_SDA, TOP_REG6, 20, 3, 0xa4, 0,
- TOP_MUX(0x0, "I2C5"), /* sda */
- TOP_MUX(0x1, "TSO1"), /* vld */
- TOP_MUX(0x2, "LCD"), /* pol */
- TOP_MUX(0x3, "BGPIO"), /* gpio83 */
- TOP_MUX(0x4, "PWM"), /* out3 */
- TOP_MUX(0x5, "I2S0"), /* dout3 */
- TOP_MUX(0x6, "B_DVI1")), /* d3 */
- TOP_PIN(SPI2_CLK, TOP_REG6, 23, 3, 0xa4, 9,
- TOP_MUX(0x0, "SPI2"), /* clk */
- TOP_MUX(0x1, "TSO0"), /* clk */
- TOP_MUX(0x2, "LCD"), /* degsl */
- TOP_MUX(0x3, "BGPIO"), /* gpio84 */
- TOP_MUX(0x4, "I2C4"), /* scl */
- TOP_MUX(0x5, "B_DVI1")), /* d4 */
- TOP_PIN(SPI2_CS, TOP_REG6, 26, 3, 0xa4, 18,
- TOP_MUX(0x0, "SPI2"), /* cs */
- TOP_MUX(0x1, "TSO0"), /* data */
- TOP_MUX(0x2, "LCD"), /* rev */
- TOP_MUX(0x3, "BGPIO"), /* gpio85 */
- TOP_MUX(0x4, "I2C4"), /* sda */
- TOP_MUX(0x5, "B_DVI1")), /* d5 */
- TOP_PIN(SPI2_TXD, TOP_REG6, 29, 3, 0xa8, 0,
- TOP_MUX(0x0, "SPI2"), /* txd */
- TOP_MUX(0x1, "TSO0"), /* sync */
- TOP_MUX(0x2, "LCD"), /* u_d */
- TOP_MUX(0x3, "BGPIO"), /* gpio86 */
- TOP_MUX(0x4, "I2C4"), /* scl */
- TOP_MUX(0x5, "B_DVI1")), /* d6 */
-
- /* top_pmm_reg_7 */
- TOP_PIN(SPI2_RXD, TOP_REG7, 0, 3, 0xa8, 9,
- TOP_MUX(0x0, "SPI2"), /* rxd */
- TOP_MUX(0x1, "TSO0"), /* vld */
- TOP_MUX(0x2, "LCD"), /* r_l */
- TOP_MUX(0x3, "BGPIO"), /* gpio87 */
- TOP_MUX(0x4, "I2C3"), /* sda */
- TOP_MUX(0x5, "B_DVI1")), /* d7 */
- TOP_PIN(NAND_WP_N, TOP_REG7, 7, 3, 0x54, 9,
- TOP_MUX(0x0, "NAND"), /* wp */
- TOP_MUX(0x1, "PWM"), /* out2 */
- TOP_MUX(0x2, "SPI2"), /* clk */
- TOP_MUX(0x3, "BGPIO"), /* gpio88 */
- TOP_MUX(0x4, "TSI0"), /* dat0 */
- TOP_MUX(0x5, "I2S1")), /* din1 */
- TOP_PIN(NAND_PAGE_SIZE0, TOP_REG7, 10, 3, 0xb8, 0,
- TOP_MUX(0x0, "NAND"), /* boot_pagesize0 */
- TOP_MUX(0x1, "PWM"), /* out3 */
- TOP_MUX(0x2, "SPI2"), /* cs */
- TOP_MUX(0x3, "BGPIO"), /* gpio89 */
- TOP_MUX(0x4, "TSI0"), /* clk */
- TOP_MUX(0x5, "I2S1")), /* din2 */
- TOP_PIN(NAND_PAGE_SIZE1, TOP_REG7, 13, 3, 0xb8, 9,
- TOP_MUX(0x0, "NAND"), /* boot_pagesize1 */
- TOP_MUX(0x1, "I2C4"), /* scl */
- TOP_MUX(0x2, "SPI2"), /* txd */
- TOP_MUX(0x3, "BGPIO"), /* gpio90 */
- TOP_MUX(0x4, "TSI0"), /* sync */
- TOP_MUX(0x5, "I2S1")), /* din3 */
- TOP_PIN(NAND_ADDR_CYCLE, TOP_REG7, 16, 3, 0xb8, 18,
- TOP_MUX(0x0, "NAND"), /* boot_addr_cycles */
- TOP_MUX(0x1, "I2C4"), /* sda */
- TOP_MUX(0x2, "SPI2"), /* rxd */
- TOP_MUX(0x3, "BGPIO"), /* gpio91 */
- TOP_MUX(0x4, "TSI0"), /* valid */
- TOP_MUX(0x5, "I2S1")), /* dout1 */
- TOP_PIN(NAND_RB0, TOP_REG7, 19, 3, 0xbc, 0,
- TOP_MUX(0x0, "NAND"), /* rdy_busy0 */
- TOP_MUX(0x1, "I2C2"), /* scl */
- TOP_MUX(0x2, "USIM0"), /* cd */
- TOP_MUX(0x3, "BGPIO"), /* gpio92 */
- TOP_MUX(0x4, "TSI1")), /* data0 */
- TOP_PIN(NAND_RB1, TOP_REG7, 22, 3, 0xbc, 9,
- TOP_MUX(0x0, "NAND"), /* rdy_busy1 */
- TOP_MUX(0x1, "I2C2"), /* sda */
- TOP_MUX(0x2, "USIM0"), /* clk */
- TOP_MUX(0x3, "BGPIO"), /* gpio93 */
- TOP_MUX(0x4, "TSI1")), /* clk */
- TOP_PIN(NAND_RB2, TOP_REG7, 25, 3, 0xbc, 18,
- TOP_MUX(0x0, "NAND"), /* rdy_busy2 */
- TOP_MUX(0x1, "UART5"), /* rxd */
- TOP_MUX(0x2, "USIM0"), /* rst */
- TOP_MUX(0x3, "BGPIO"), /* gpio94 */
- TOP_MUX(0x4, "TSI1"), /* sync */
- TOP_MUX(0x4, "I2S1")), /* dout2 */
- TOP_PIN(NAND_RB3, TOP_REG7, 28, 3, 0x54, 18,
- TOP_MUX(0x0, "NAND"), /* rdy_busy3 */
- TOP_MUX(0x1, "UART5"), /* txd */
- TOP_MUX(0x2, "USIM0"), /* dat */
- TOP_MUX(0x3, "BGPIO"), /* gpio95 */
- TOP_MUX(0x4, "TSI1"), /* valid */
- TOP_MUX(0x4, "I2S1")), /* dout3 */
-
- /* top_pmm_reg_8 */
- TOP_PIN(GMAC_125M_IN, TOP_REG8, 0, 2, 0x34, 0,
- TOP_MUX(0x0, "GMII"), /* 125m_in */
- TOP_MUX(0x1, "USB2"), /* 0_drvvbus */
- TOP_MUX(0x2, "ISP"), /* ref_clk */
- TOP_MUX(0x3, "BGPIO")), /* gpio96 */
- TOP_PIN(GMAC_50M_OUT, TOP_REG8, 2, 2, 0x34, 9,
- TOP_MUX(0x0, "GMII"), /* 50m_out */
- TOP_MUX(0x1, "USB2"), /* 1_drvvbus */
- TOP_MUX(0x2, "BGPIO"), /* gpio97 */
- TOP_MUX(0x3, "USB2")), /* 0_drvvbus */
- TOP_PIN(SPINOR_SSCLK_LOOPBACK, TOP_REG8, 6, 1, 0xc8, 9,
- TOP_MUX(0x0, "SPINOR")), /* sdio1_clk_i */
- TOP_PIN(SPINOR_SDIO1CLK_LOOPBACK, TOP_REG8, 7, 1, 0xc8, 18,
- TOP_MUX(0x0, "SPINOR")), /* ssclk_i */
-};
-
-static struct zx_pinctrl_soc_info zx296718_pinctrl_info = {
- .pins = zx296718_pins,
- .npins = ARRAY_SIZE(zx296718_pins),
-};
-
-static int zx296718_pinctrl_probe(struct platform_device *pdev)
-{
- return zx_pinctrl_init(pdev, &zx296718_pinctrl_info);
-}
-
-static const struct of_device_id zx296718_pinctrl_match[] = {
- { .compatible = "zte,zx296718-pmm", },
- {}
-};
-MODULE_DEVICE_TABLE(of, zx296718_pinctrl_match);
-
-static struct platform_driver zx296718_pinctrl_driver = {
- .probe = zx296718_pinctrl_probe,
- .driver = {
- .name = "zx296718-pinctrl",
- .of_match_table = zx296718_pinctrl_match,
- },
-};
-builtin_platform_driver(zx296718_pinctrl_driver);
-
-MODULE_DESCRIPTION("ZTE ZX296718 pinctrl driver");
-MODULE_LICENSE("GPL");
diff --git a/include/linux/kconfig.h b/include/linux/kconfig.h
index 9d12c97..e78e17a 100644
--- a/include/linux/kconfig.h
+++ b/include/linux/kconfig.h
@@ -72,4 +72,10 @@
*/
#define IS_ENABLED(option) __or(IS_BUILTIN(option), IS_MODULE(option))
+/*
+ * IF_ENABLED(CONFIG_FOO, ptr) evaluates to (ptr) if CONFIG_FOO is set to 'y'
+ * or 'm', NULL otherwise.
+ */
+#define IF_ENABLED(option, ptr) (IS_ENABLED(option) ? (ptr) : NULL)
+
#endif /* __LINUX_KCONFIG_H */
