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Amlogic SD / eMMC controller for S905/GXBB family SoCs
The MMC 5.1 compliant host controller on Amlogic provides the
interface for SD, eMMC and SDIO devices.
This file documents the properties in addition to those available in
the MMC core bindings, documented by mmc.txt.
Required properties:
- compatible : contains one of:
- "amlogic,meson-gx-mmc"
- "amlogic,meson-gxbb-mmc"
- "amlogic,meson-gxl-mmc"
- "amlogic,meson-gxm-mmc"
- "amlogic,meson-axg-mmc"
- clocks : A list of phandle + clock-specifier pairs for the clocks listed in clock-names.
- clock-names: Should contain the following:
"core" - Main peripheral bus clock
"clkin0" - Parent clock of internal mux
"clkin1" - Other parent clock of internal mux
The driver has an internal mux clock which switches between clkin0 and clkin1 depending on the
clock rate requested by the MMC core.
- resets : phandle of the internal reset line
Optional properties:
- amlogic,dram-access-quirk: set when controller's internal DMA engine cannot access the
DRAM memory, like on the G12A dedicated SDIO controller.
sd_emmc_a: mmc@70000 {
compatible = "amlogic,meson-gxbb-mmc";
reg = <0x0 0x70000 0x0 0x2000>;
interrupts = < GIC_SPI 216 IRQ_TYPE_EDGE_RISING>;
clocks = <&clkc CLKID_SD_EMMC_A>, <&xtal>, <&clkc CLKID_FCLK_DIV2>;
clock-names = "core", "clkin0", "clkin1";
pinctrl-0 = <&emmc_pins>;
resets = <&reset RESET_SD_EMMC_A>;