UniPhier glue reset controller


Peripheral core reset in glue layer
-----------------------------------

Some peripheral core reset belongs to its own glue layer. Before using
this core reset, it is necessary to control the clocks and resets to enable
this layer. These clocks and resets should be described in each property.

Required properties:
- compatible: Should be
    "socionext,uniphier-pro4-usb3-reset" - for Pro4 SoC USB3
    "socionext,uniphier-pro5-usb3-reset" - for Pro5 SoC USB3
    "socionext,uniphier-pxs2-usb3-reset" - for PXs2 SoC USB3
    "socionext,uniphier-ld20-usb3-reset" - for LD20 SoC USB3
    "socionext,uniphier-pxs3-usb3-reset" - for PXs3 SoC USB3
    "socionext,uniphier-pro4-ahci-reset" - for Pro4 SoC AHCI
    "socionext,uniphier-pxs2-ahci-reset" - for PXs2 SoC AHCI
    "socionext,uniphier-pxs3-ahci-reset" - for PXs3 SoC AHCI
- #reset-cells: Should be 1.
- reg: Specifies offset and length of the register set for the device.
- clocks: A list of phandles to the clock gate for the glue layer.
	According to the clock-names, appropriate clocks are required.
- clock-names: Should contain
    "gio", "link" - for Pro4 and Pro5 SoCs
    "link"        - for others
- resets: A list of phandles to the reset control for the glue layer.
	According to the reset-names, appropriate resets are required.
- reset-names: Should contain
    "gio", "link" - for Pro4 and Pro5 SoCs
    "link"        - for others

Example:

	usb-glue@65b00000 {
		compatible = "socionext,uniphier-ld20-dwc3-glue",
			     "simple-mfd";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0 0x65b00000 0x400>;

		usb_rst: reset@0 {
			compatible = "socionext,uniphier-ld20-usb3-reset";
			reg = <0x0 0x4>;
			#reset-cells = <1>;
			clock-names = "link";
			clocks = <&sys_clk 14>;
			reset-names = "link";
			resets = <&sys_rst 14>;
		};

		regulator {
			...
		};

		phy {
			...
		};
		...
	};