tree 0b4be4bd5091b398a875f5d0cc75245109bc8e6d
parent 5f9e832c137075045d15cd6899ab0505cfb2ca4b
parent 65818ad0815f3a2ba6a41327cce8b600ee04be32
author Stephen Boyd <sboyd@kernel.org> 1567620891 -0700
committer Stephen Boyd <sboyd@kernel.org> 1567620891 -0700
mergetag object 65818ad0815f3a2ba6a41327cce8b600ee04be32
 type commit
 tag sunxi-clk-for-5.4-1
 tagger Maxime Ripard <maxime.ripard@bootlin.com> 1566570536 +0200
 
 Allwinner clock changes for 5.4
 
 A few patches to enable the V3 SoC and fix the i2s clock for the H6.
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Merge tag 'sunxi-clk-for-5.4-1' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into clk-allwinner

Pull Allwinner clock changes from Maxime Ripard:

A few patches to enable the V3 SoC and fix the i2s clock for the H6.

* tag 'sunxi-clk-for-5.4-1' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
  clk: sunxi-ng: h6: Allow I2S to change parent rate
  clk: sunxi-ng: v3s: add Allwinner V3 support
  clk: sunxi-ng: v3s: add missing clock slices for MMC2 module clocks
  dt-bindings: clk: sunxi-ccu: add compatible string for V3 CCU
  clk: sunxi-ng: v3s: add the missing PLL_DDR1