Documentation/devicetree/bindings/net/wireless/qcom,ath10k.txt

* Qualcomm Atheros ath10k wireless devices

Required properties:
- compatible: Should be one of the following:
	* "qcom,ath10k"
	* "qcom,ipq4019-wifi"
	* "qcom,wcn3990-wifi"

PCI based devices uses compatible string "qcom,ath10k" and takes calibration
data along with board specific data via "qcom,ath10k-calibration-data".
Rest of the properties are not applicable for PCI based devices.

AHB based devices (i.e. ipq4019) uses compatible string "qcom,ipq4019-wifi"
and also uses most of the properties defined in this doc (except
"qcom,ath10k-calibration-data"). It uses "qcom,ath10k-pre-calibration-data"
to carry pre calibration data.

In general, entry "qcom,ath10k-pre-calibration-data" and
"qcom,ath10k-calibration-data" conflict with each other and only one
can be provided per device.

SNOC based devices (i.e. wcn3990) uses compatible string "qcom,wcn3990-wifi".

- reg: Address and length of the register set for the device.
- reg-names: Must include the list of following reg names,
	     "membase"
- interrupts: reference to the list of 17 interrupt numbers for "qcom,ipq4019-wifi"
	      compatible target.
	      reference to the list of 12 interrupt numbers for "qcom,wcn3990-wifi"
	      compatible target.
	      Must contain interrupt-names property per entry for
	      "qcom,ath10k", "qcom,ipq4019-wifi" compatible targets.

- interrupt-names: Must include the entries for MSI interrupt
		   names ("msi0" to "msi15") and legacy interrupt
		   name ("legacy") for "qcom,ath10k", "qcom,ipq4019-wifi"
		   compatible targets.

Optional properties:
- resets: Must contain an entry for each entry in reset-names.
          See ../reset/reseti.txt for details.
- reset-names: Must include the list of following reset names,
	       "wifi_cpu_init"
	       "wifi_radio_srif"
	       "wifi_radio_warm"
	       "wifi_radio_cold"
	       "wifi_core_warm"
	       "wifi_core_cold"
- clocks: List of clock specifiers, must contain an entry for each required
          entry in clock-names.
- clock-names: Should contain the clock names "wifi_wcss_cmd", "wifi_wcss_ref",
	       "wifi_wcss_rtc" for "qcom,ipq4019-wifi" compatible target and
	       "cxo_ref_clk_pin" for "qcom,wcn3990-wifi"
	       compatible target.
- qcom,msi_addr: MSI interrupt address.
- qcom,msi_base: Base value to add before writing MSI data into
		MSI address register.
- qcom,ath10k-calibration-variant: string to search for in the board-2.bin
				   variant list with the same bus and device
				   specific ids
- qcom,ath10k-calibration-data : calibration data + board specific data
				 as an array, the length can vary between
				 hw versions.
- qcom,ath10k-pre-calibration-data : pre calibration data as an array,
				     the length can vary between hw versions.
- <supply-name>-supply: handle to the regulator device tree node
			   optional "supply-name" are "vdd-0.8-cx-mx",
			   "vdd-1.8-xo", "vdd-1.3-rfa" and "vdd-3.3-ch0".
- memory-region:
	Usage: optional
	Value type: <phandle>
	Definition: reference to the reserved-memory for the msa region
		    used by the wifi firmware running in Q6.
- iommus:
	Usage: optional
	Value type: <prop-encoded-array>
	Definition: A list of phandle and IOMMU specifier pairs.
- ext-fem-name:
	Usage: Optional
	Value type: string
	Definition: Name of external front end module used. Some valid FEM names
		    for example: "microsemi-lx5586", "sky85703-11"
		    and "sky85803" etc.

Example (to supply PCI based wifi block details):

In this example, the node is defined as child node of the PCI controller.

pci {
	pcie@0 {
		reg = <0 0 0 0 0>;
		#interrupt-cells = <1>;
		#size-cells = <2>;
		#address-cells = <3>;
		device_type = "pci";

		wifi@0,0 {
			reg = <0 0 0 0 0>;
			qcom,ath10k-calibration-data = [ 01 02 03 ... ];
			ext-fem-name = "microsemi-lx5586";
		};
	};
};

Example (to supply ipq4019 SoC wifi block details):

wifi0: wifi@a000000 {
	compatible = "qcom,ipq4019-wifi";
	reg = <0xa000000 0x200000>;
	resets = <&gcc WIFI0_CPU_INIT_RESET>,
		 <&gcc WIFI0_RADIO_SRIF_RESET>,
		 <&gcc WIFI0_RADIO_WARM_RESET>,
		 <&gcc WIFI0_RADIO_COLD_RESET>,
		 <&gcc WIFI0_CORE_WARM_RESET>,
		 <&gcc WIFI0_CORE_COLD_RESET>;
	reset-names = "wifi_cpu_init",
		      "wifi_radio_srif",
		      "wifi_radio_warm",
		      "wifi_radio_cold",
		      "wifi_core_warm",
		      "wifi_core_cold";
	clocks = <&gcc GCC_WCSS2G_CLK>,
		 <&gcc GCC_WCSS2G_REF_CLK>,
		 <&gcc GCC_WCSS2G_RTC_CLK>;
	clock-names = "wifi_wcss_cmd",
		      "wifi_wcss_ref",
		      "wifi_wcss_rtc";
	interrupts = <0 0x20 0x1>,
		     <0 0x21 0x1>,
		     <0 0x22 0x1>,
		     <0 0x23 0x1>,
		     <0 0x24 0x1>,
		     <0 0x25 0x1>,
		     <0 0x26 0x1>,
		     <0 0x27 0x1>,
		     <0 0x28 0x1>,
		     <0 0x29 0x1>,
		     <0 0x2a 0x1>,
		     <0 0x2b 0x1>,
		     <0 0x2c 0x1>,
		     <0 0x2d 0x1>,
		     <0 0x2e 0x1>,
		     <0 0x2f 0x1>,
		     <0 0xa8 0x0>;
	interrupt-names = "msi0",  "msi1",  "msi2",  "msi3",
			  "msi4",  "msi5",  "msi6",  "msi7",
			  "msi8",  "msi9",  "msi10", "msi11",
			  "msi12", "msi13", "msi14", "msi15",
			  "legacy";
	qcom,msi_addr = <0x0b006040>;
	qcom,msi_base = <0x40>;
	qcom,ath10k-pre-calibration-data = [ 01 02 03 ... ];
};

Example (to supply wcn3990 SoC wifi block details):

wifi@18000000 {
		compatible = "qcom,wcn3990-wifi";
		reg = <0x18800000 0x800000>;
		reg-names = "membase";
		clocks = <&clock_gcc clk_rf_clk2_pin>;
		clock-names = "cxo_ref_clk_pin";
		interrupts =
			<GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>;
		vdd-0.8-cx-mx-supply = <&pm8998_l5>;
		vdd-1.8-xo-supply = <&vreg_l7a_1p8>;
		vdd-1.3-rfa-supply = <&vreg_l17a_1p3>;
		vdd-3.3-ch0-supply = <&vreg_l25a_3p3>;
		memory-region = <&wifi_msa_mem>;
		iommus = <&apps_smmu 0x0040 0x1>;
};