| commit | a13b9d0b97211579ea63b96c606de79b963c0f47 | [log] [tgz] |
|---|---|---|
| author | Kees Cook <keescook@chromium.org> | Mon Jun 08 20:15:09 2020 -0700 |
| committer | Thomas Gleixner <tglx@linutronix.de> | Thu Jun 18 11:41:32 2020 +0200 |
| tree | 6cc00b548d67524d637c808aeb2d74fea61d8f4c | |
| parent | cc5277fe66cf3ad68f41f1c539b2ef0d5e432974 [diff] |
x86/cpu: Use pinning mask for CR4 bits needing to be 0 The X86_CR4_FSGSBASE bit of CR4 should not change after boot[1]. Older kernels should enforce this bit to zero, and newer kernels need to enforce it depending on boot-time configuration (e.g. "nofsgsbase"). To support a pinned bit being either 1 or 0, use an explicit mask in combination with the expected pinned bit values. [1] https://lore.kernel.org/lkml/20200527103147.GI325280@hirez.programming.kicks-ass.net Signed-off-by: Kees Cook <keescook@chromium.org> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: stable@vger.kernel.org Link: https://lkml.kernel.org/r/202006082013.71E29A42@keescook