blob: 3133f3ba756748da6514f7b666ac29d63baadaf4 [file] [log] [blame]
* ARM System MMU Architecture Implementation
ARM SoCs may contain an implementation of the ARM System Memory
Management Unit Architecture, which can be used to provide 1 or 2 stages
of address translation to bus masters external to the CPU.
The SMMU may also raise interrupts in response to various fault
** System MMU required properties:
- compatible : Should be one of:
depending on the particular implementation and/or the
version of the architecture implemented.
Qcom SoCs must contain, as below, SoC-specific compatibles
along with "qcom,smmu-v2":
"qcom,msm8996-smmu-v2", "qcom,smmu-v2",
"qcom,sdm845-smmu-v2", "qcom,smmu-v2".
Qcom SoCs implementing "arm,mmu-500" must also include,
as below, SoC-specific compatibles:
"qcom,sdm845-smmu-500", "arm,mmu-500"
- reg : Base address and size of the SMMU.
- #global-interrupts : The number of global interrupts exposed by the
- interrupts : Interrupt list, with the first #global-irqs entries
corresponding to the global interrupts and any
following entries corresponding to context interrupts,
specified in order of their indexing by the SMMU.
For SMMUv2 implementations, there must be exactly one
interrupt per context bank. In the case of a single,
combined interrupt, it must be listed multiple times.
- #iommu-cells : See Documentation/devicetree/bindings/iommu/iommu.txt
for details. With a value of 1, each IOMMU specifier
represents a distinct stream ID emitted by that device
into the relevant SMMU.
SMMUs with stream matching support and complex masters
may use a value of 2, where the second cell of the
IOMMU specifier represents an SMR mask to combine with
the ID in the first cell. Care must be taken to ensure
the set of matched IDs does not result in conflicts.
** System MMU optional properties:
- dma-coherent : Present if page table walks made by the SMMU are
cache coherent with the CPU.
NOTE: this only applies to the SMMU itself, not
masters connected upstream of the SMMU.
- calxeda,smmu-secure-config-access : Enable proper handling of buggy
implementations that always use secure access to
SMMU configuration registers. In this case non-secure
aliases of secure registers have to be used during
SMMU configuration.
- stream-match-mask : For SMMUs supporting stream matching and using
#iommu-cells = <1>, specifies a mask of bits to ignore
when matching stream IDs (e.g. this may be programmed
into the SMRn.MASK field of every stream match register
used). For cases where it is desirable to ignore some
portion of every Stream ID (e.g. for certain MMU-500
configurations given globally unique input IDs). This
property is not valid for SMMUs using stream indexing,
or using stream matching with #iommu-cells = <2>, and
may be ignored if present in such cases.
- clock-names: List of the names of clocks input to the device. The
required list depends on particular implementation and
is as follows:
- for "qcom,smmu-v2":
- "bus": clock required for downstream bus access and
for the smmu ptw,
- "iface": clock required to access smmu's registers
through the TCU's programming interface.
- unspecified for other implementations.
- clocks: Specifiers for all clocks listed in the clock-names property,
as per generic clock bindings.
- power-domains: Specifiers for power domains required to be powered on for
the SMMU to operate, as per generic power domain bindings.
** Deprecated properties:
- mmu-masters (deprecated in favour of the generic "iommus" binding) :
A list of phandles to device nodes representing bus
masters for which the SMMU can provide a translation
and their corresponding Stream IDs. Each device node
linked from this list must have a "#stream-id-cells"
property, indicating the number of Stream ID
arguments associated with its phandle.
** Examples:
/* SMMU with stream matching or stream indexing */
smmu1: iommu {
compatible = "arm,smmu-v1";
reg = <0xba5e0000 0x10000>;
#global-interrupts = <2>;
interrupts = <0 32 4>,
<0 33 4>,
<0 34 4>, /* This is the first context interrupt */
<0 35 4>,
<0 36 4>,
<0 37 4>;
#iommu-cells = <1>;
/* device with two stream IDs, 0 and 7 */
master1 {
iommus = <&smmu1 0>,
<&smmu1 7>;
/* SMMU with stream matching */
smmu2: iommu {
#iommu-cells = <2>;
/* device with stream IDs 0 and 7 */
master2 {
iommus = <&smmu2 0 0>,
<&smmu2 7 0>;
/* device with stream IDs 1, 17, 33 and 49 */
master3 {
iommus = <&smmu2 1 0x30>;
/* ARM MMU-500 with 10-bit stream ID input configuration */
smmu3: iommu {
compatible = "arm,mmu-500", "arm,smmu-v2";
#iommu-cells = <1>;
/* always ignore appended 5-bit TBU number */
stream-match-mask = 0x7c00;
bus {
/* bus whose child devices emit one unique 10-bit stream
ID each, but may master through multiple SMMU TBUs */
iommu-map = <0 &smmu3 0 0x400>;
/* Qcom's arm,smmu-v2 implementation */
smmu4: iommu@d00000 {
compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
reg = <0xd00000 0x10000>;
#global-interrupts = <1>;
interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
#iommu-cells = <1>;
power-domains = <&mmcc MDSS_GDSC>;
clocks = <&mmcc SMMU_MDP_AXI_CLK>,
clock-names = "bus", "iface";