| // SPDX-License-Identifier: GPL-2.0-only |
| /******************************************************************************* |
| This is the driver for the ST MAC 10/100/1000 on-chip Ethernet controllers. |
| ST Ethernet IPs are built around a Synopsys IP Core. |
| |
| Copyright(C) 2007-2011 STMicroelectronics Ltd |
| |
| |
| Author: Giuseppe Cavallaro <peppe.cavallaro@st.com> |
| |
| Documentation available at: |
| http://www.stlinux.com |
| Support available at: |
| https://bugzilla.stlinux.com/ |
| *******************************************************************************/ |
| |
| #include <linux/clk.h> |
| #include <linux/kernel.h> |
| #include <linux/interrupt.h> |
| #include <linux/ip.h> |
| #include <linux/tcp.h> |
| #include <linux/skbuff.h> |
| #include <linux/ethtool.h> |
| #include <linux/if_ether.h> |
| #include <linux/crc32.h> |
| #include <linux/mii.h> |
| #include <linux/if.h> |
| #include <linux/if_vlan.h> |
| #include <linux/dma-mapping.h> |
| #include <linux/slab.h> |
| #include <linux/prefetch.h> |
| #include <linux/pinctrl/consumer.h> |
| #ifdef CONFIG_DEBUG_FS |
| #include <linux/debugfs.h> |
| #include <linux/seq_file.h> |
| #endif /* CONFIG_DEBUG_FS */ |
| #include <linux/net_tstamp.h> |
| #include <linux/phylink.h> |
| #include <linux/udp.h> |
| #include <net/pkt_cls.h> |
| #include "stmmac_ptp.h" |
| #include "stmmac.h" |
| #include <linux/reset.h> |
| #include <linux/of_mdio.h> |
| #include "dwmac1000.h" |
| #include "dwxgmac2.h" |
| #include "hwif.h" |
| |
| #define STMMAC_ALIGN(x) ALIGN(ALIGN(x, SMP_CACHE_BYTES), 16) |
| #define TSO_MAX_BUFF_SIZE (SZ_16K - 1) |
| |
| /* Module parameters */ |
| #define TX_TIMEO 5000 |
| static int watchdog = TX_TIMEO; |
| module_param(watchdog, int, 0644); |
| MODULE_PARM_DESC(watchdog, "Transmit timeout in milliseconds (default 5s)"); |
| |
| static int debug = -1; |
| module_param(debug, int, 0644); |
| MODULE_PARM_DESC(debug, "Message Level (-1: default, 0: no output, 16: all)"); |
| |
| static int phyaddr = -1; |
| module_param(phyaddr, int, 0444); |
| MODULE_PARM_DESC(phyaddr, "Physical device address"); |
| |
| #define STMMAC_TX_THRESH (DMA_TX_SIZE / 4) |
| #define STMMAC_RX_THRESH (DMA_RX_SIZE / 4) |
| |
| static int flow_ctrl = FLOW_AUTO; |
| module_param(flow_ctrl, int, 0644); |
| MODULE_PARM_DESC(flow_ctrl, "Flow control ability [on/off]"); |
| |
| static int pause = PAUSE_TIME; |
| module_param(pause, int, 0644); |
| MODULE_PARM_DESC(pause, "Flow Control Pause Time"); |
| |
| #define TC_DEFAULT 64 |
| static int tc = TC_DEFAULT; |
| module_param(tc, int, 0644); |
| MODULE_PARM_DESC(tc, "DMA threshold control value"); |
| |
| #define DEFAULT_BUFSIZE 1536 |
| static int buf_sz = DEFAULT_BUFSIZE; |
| module_param(buf_sz, int, 0644); |
| MODULE_PARM_DESC(buf_sz, "DMA buffer size"); |
| |
| #define STMMAC_RX_COPYBREAK 256 |
| |
| static const u32 default_msg_level = (NETIF_MSG_DRV | NETIF_MSG_PROBE | |
| NETIF_MSG_LINK | NETIF_MSG_IFUP | |
| NETIF_MSG_IFDOWN | NETIF_MSG_TIMER); |
| |
| #define STMMAC_DEFAULT_LPI_TIMER 1000 |
| static int eee_timer = STMMAC_DEFAULT_LPI_TIMER; |
| module_param(eee_timer, int, 0644); |
| MODULE_PARM_DESC(eee_timer, "LPI tx expiration time in msec"); |
| #define STMMAC_LPI_T(x) (jiffies + msecs_to_jiffies(x)) |
| |
| /* By default the driver will use the ring mode to manage tx and rx descriptors, |
| * but allow user to force to use the chain instead of the ring |
| */ |
| static unsigned int chain_mode; |
| module_param(chain_mode, int, 0444); |
| MODULE_PARM_DESC(chain_mode, "To use chain instead of ring mode"); |
| |
| static irqreturn_t stmmac_interrupt(int irq, void *dev_id); |
| |
| #ifdef CONFIG_DEBUG_FS |
| static const struct net_device_ops stmmac_netdev_ops; |
| static void stmmac_init_fs(struct net_device *dev); |
| static void stmmac_exit_fs(struct net_device *dev); |
| #endif |
| |
| #define STMMAC_COAL_TIMER(x) (jiffies + usecs_to_jiffies(x)) |
| |
| /** |
| * stmmac_verify_args - verify the driver parameters. |
| * Description: it checks the driver parameters and set a default in case of |
| * errors. |
| */ |
| static void stmmac_verify_args(void) |
| { |
| if (unlikely(watchdog < 0)) |
| watchdog = TX_TIMEO; |
| if (unlikely((buf_sz < DEFAULT_BUFSIZE) || (buf_sz > BUF_SIZE_16KiB))) |
| buf_sz = DEFAULT_BUFSIZE; |
| if (unlikely(flow_ctrl > 1)) |
| flow_ctrl = FLOW_AUTO; |
| else if (likely(flow_ctrl < 0)) |
| flow_ctrl = FLOW_OFF; |
| if (unlikely((pause < 0) || (pause > 0xffff))) |
| pause = PAUSE_TIME; |
| if (eee_timer < 0) |
| eee_timer = STMMAC_DEFAULT_LPI_TIMER; |
| } |
| |
| /** |
| * stmmac_disable_all_queues - Disable all queues |
| * @priv: driver private structure |
| */ |
| static void stmmac_disable_all_queues(struct stmmac_priv *priv) |
| { |
| u32 rx_queues_cnt = priv->plat->rx_queues_to_use; |
| u32 tx_queues_cnt = priv->plat->tx_queues_to_use; |
| u32 maxq = max(rx_queues_cnt, tx_queues_cnt); |
| u32 queue; |
| |
| for (queue = 0; queue < maxq; queue++) { |
| struct stmmac_channel *ch = &priv->channel[queue]; |
| |
| if (queue < rx_queues_cnt) |
| napi_disable(&ch->rx_napi); |
| if (queue < tx_queues_cnt) |
| napi_disable(&ch->tx_napi); |
| } |
| } |
| |
| /** |
| * stmmac_enable_all_queues - Enable all queues |
| * @priv: driver private structure |
| */ |
| static void stmmac_enable_all_queues(struct stmmac_priv *priv) |
| { |
| u32 rx_queues_cnt = priv->plat->rx_queues_to_use; |
| u32 tx_queues_cnt = priv->plat->tx_queues_to_use; |
| u32 maxq = max(rx_queues_cnt, tx_queues_cnt); |
| u32 queue; |
| |
| for (queue = 0; queue < maxq; queue++) { |
| struct stmmac_channel *ch = &priv->channel[queue]; |
| |
| if (queue < rx_queues_cnt) |
| napi_enable(&ch->rx_napi); |
| if (queue < tx_queues_cnt) |
| napi_enable(&ch->tx_napi); |
| } |
| } |
| |
| /** |
| * stmmac_stop_all_queues - Stop all queues |
| * @priv: driver private structure |
| */ |
| static void stmmac_stop_all_queues(struct stmmac_priv *priv) |
| { |
| u32 tx_queues_cnt = priv->plat->tx_queues_to_use; |
| u32 queue; |
| |
| for (queue = 0; queue < tx_queues_cnt; queue++) |
| netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, queue)); |
| } |
| |
| /** |
| * stmmac_start_all_queues - Start all queues |
| * @priv: driver private structure |
| */ |
| static void stmmac_start_all_queues(struct stmmac_priv *priv) |
| { |
| u32 tx_queues_cnt = priv->plat->tx_queues_to_use; |
| u32 queue; |
| |
| for (queue = 0; queue < tx_queues_cnt; queue++) |
| netif_tx_start_queue(netdev_get_tx_queue(priv->dev, queue)); |
| } |
| |
| static void stmmac_service_event_schedule(struct stmmac_priv *priv) |
| { |
| if (!test_bit(STMMAC_DOWN, &priv->state) && |
| !test_and_set_bit(STMMAC_SERVICE_SCHED, &priv->state)) |
| queue_work(priv->wq, &priv->service_task); |
| } |
| |
| static void stmmac_global_err(struct stmmac_priv *priv) |
| { |
| netif_carrier_off(priv->dev); |
| set_bit(STMMAC_RESET_REQUESTED, &priv->state); |
| stmmac_service_event_schedule(priv); |
| } |
| |
| /** |
| * stmmac_clk_csr_set - dynamically set the MDC clock |
| * @priv: driver private structure |
| * Description: this is to dynamically set the MDC clock according to the csr |
| * clock input. |
| * Note: |
| * If a specific clk_csr value is passed from the platform |
| * this means that the CSR Clock Range selection cannot be |
| * changed at run-time and it is fixed (as reported in the driver |
| * documentation). Viceversa the driver will try to set the MDC |
| * clock dynamically according to the actual clock input. |
| */ |
| static void stmmac_clk_csr_set(struct stmmac_priv *priv) |
| { |
| u32 clk_rate; |
| |
| clk_rate = clk_get_rate(priv->plat->stmmac_clk); |
| |
| /* Platform provided default clk_csr would be assumed valid |
| * for all other cases except for the below mentioned ones. |
| * For values higher than the IEEE 802.3 specified frequency |
| * we can not estimate the proper divider as it is not known |
| * the frequency of clk_csr_i. So we do not change the default |
| * divider. |
| */ |
| if (!(priv->clk_csr & MAC_CSR_H_FRQ_MASK)) { |
| if (clk_rate < CSR_F_35M) |
| priv->clk_csr = STMMAC_CSR_20_35M; |
| else if ((clk_rate >= CSR_F_35M) && (clk_rate < CSR_F_60M)) |
| priv->clk_csr = STMMAC_CSR_35_60M; |
| else if ((clk_rate >= CSR_F_60M) && (clk_rate < CSR_F_100M)) |
| priv->clk_csr = STMMAC_CSR_60_100M; |
| else if ((clk_rate >= CSR_F_100M) && (clk_rate < CSR_F_150M)) |
| priv->clk_csr = STMMAC_CSR_100_150M; |
| else if ((clk_rate >= CSR_F_150M) && (clk_rate < CSR_F_250M)) |
| priv->clk_csr = STMMAC_CSR_150_250M; |
| else if ((clk_rate >= CSR_F_250M) && (clk_rate < CSR_F_300M)) |
| priv->clk_csr = STMMAC_CSR_250_300M; |
| } |
| |
| if (priv->plat->has_sun8i) { |
| if (clk_rate > 160000000) |
| priv->clk_csr = 0x03; |
| else if (clk_rate > 80000000) |
| priv->clk_csr = 0x02; |
| else if (clk_rate > 40000000) |
| priv->clk_csr = 0x01; |
| else |
| priv->clk_csr = 0; |
| } |
| |
| if (priv->plat->has_xgmac) { |
| if (clk_rate > 400000000) |
| priv->clk_csr = 0x5; |
| else if (clk_rate > 350000000) |
| priv->clk_csr = 0x4; |
| else if (clk_rate > 300000000) |
| priv->clk_csr = 0x3; |
| else if (clk_rate > 250000000) |
| priv->clk_csr = 0x2; |
| else if (clk_rate > 150000000) |
| priv->clk_csr = 0x1; |
| else |
| priv->clk_csr = 0x0; |
| } |
| } |
| |
| static void print_pkt(unsigned char *buf, int len) |
| { |
| pr_debug("len = %d byte, buf addr: 0x%p\n", len, buf); |
| print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, buf, len); |
| } |
| |
| static inline u32 stmmac_tx_avail(struct stmmac_priv *priv, u32 queue) |
| { |
| struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; |
| u32 avail; |
| |
| if (tx_q->dirty_tx > tx_q->cur_tx) |
| avail = tx_q->dirty_tx - tx_q->cur_tx - 1; |
| else |
| avail = DMA_TX_SIZE - tx_q->cur_tx + tx_q->dirty_tx - 1; |
| |
| return avail; |
| } |
| |
| /** |
| * stmmac_rx_dirty - Get RX queue dirty |
| * @priv: driver private structure |
| * @queue: RX queue index |
| */ |
| static inline u32 stmmac_rx_dirty(struct stmmac_priv *priv, u32 queue) |
| { |
| struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; |
| u32 dirty; |
| |
| if (rx_q->dirty_rx <= rx_q->cur_rx) |
| dirty = rx_q->cur_rx - rx_q->dirty_rx; |
| else |
| dirty = DMA_RX_SIZE - rx_q->dirty_rx + rx_q->cur_rx; |
| |
| return dirty; |
| } |
| |
| /** |
| * stmmac_enable_eee_mode - check and enter in LPI mode |
| * @priv: driver private structure |
| * Description: this function is to verify and enter in LPI mode in case of |
| * EEE. |
| */ |
| static void stmmac_enable_eee_mode(struct stmmac_priv *priv) |
| { |
| u32 tx_cnt = priv->plat->tx_queues_to_use; |
| u32 queue; |
| |
| /* check if all TX queues have the work finished */ |
| for (queue = 0; queue < tx_cnt; queue++) { |
| struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; |
| |
| if (tx_q->dirty_tx != tx_q->cur_tx) |
| return; /* still unfinished work */ |
| } |
| |
| /* Check and enter in LPI mode */ |
| if (!priv->tx_path_in_lpi_mode) |
| stmmac_set_eee_mode(priv, priv->hw, |
| priv->plat->en_tx_lpi_clockgating); |
| } |
| |
| /** |
| * stmmac_disable_eee_mode - disable and exit from LPI mode |
| * @priv: driver private structure |
| * Description: this function is to exit and disable EEE in case of |
| * LPI state is true. This is called by the xmit. |
| */ |
| void stmmac_disable_eee_mode(struct stmmac_priv *priv) |
| { |
| stmmac_reset_eee_mode(priv, priv->hw); |
| del_timer_sync(&priv->eee_ctrl_timer); |
| priv->tx_path_in_lpi_mode = false; |
| } |
| |
| /** |
| * stmmac_eee_ctrl_timer - EEE TX SW timer. |
| * @arg : data hook |
| * Description: |
| * if there is no data transfer and if we are not in LPI state, |
| * then MAC Transmitter can be moved to LPI state. |
| */ |
| static void stmmac_eee_ctrl_timer(struct timer_list *t) |
| { |
| struct stmmac_priv *priv = from_timer(priv, t, eee_ctrl_timer); |
| |
| stmmac_enable_eee_mode(priv); |
| mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(eee_timer)); |
| } |
| |
| /** |
| * stmmac_eee_init - init EEE |
| * @priv: driver private structure |
| * Description: |
| * if the GMAC supports the EEE (from the HW cap reg) and the phy device |
| * can also manage EEE, this function enable the LPI state and start related |
| * timer. |
| */ |
| bool stmmac_eee_init(struct stmmac_priv *priv) |
| { |
| int tx_lpi_timer = priv->tx_lpi_timer; |
| |
| /* Using PCS we cannot dial with the phy registers at this stage |
| * so we do not support extra feature like EEE. |
| */ |
| if (priv->hw->pcs == STMMAC_PCS_TBI || |
| priv->hw->pcs == STMMAC_PCS_RTBI) |
| return false; |
| |
| /* Check if MAC core supports the EEE feature. */ |
| if (!priv->dma_cap.eee) |
| return false; |
| |
| mutex_lock(&priv->lock); |
| |
| /* Check if it needs to be deactivated */ |
| if (!priv->eee_active) { |
| if (priv->eee_enabled) { |
| netdev_dbg(priv->dev, "disable EEE\n"); |
| del_timer_sync(&priv->eee_ctrl_timer); |
| stmmac_set_eee_timer(priv, priv->hw, 0, tx_lpi_timer); |
| } |
| mutex_unlock(&priv->lock); |
| return false; |
| } |
| |
| if (priv->eee_active && !priv->eee_enabled) { |
| timer_setup(&priv->eee_ctrl_timer, stmmac_eee_ctrl_timer, 0); |
| mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(eee_timer)); |
| stmmac_set_eee_timer(priv, priv->hw, STMMAC_DEFAULT_LIT_LS, |
| tx_lpi_timer); |
| } |
| |
| mutex_unlock(&priv->lock); |
| netdev_dbg(priv->dev, "Energy-Efficient Ethernet initialized\n"); |
| return true; |
| } |
| |
| /* stmmac_get_tx_hwtstamp - get HW TX timestamps |
| * @priv: driver private structure |
| * @p : descriptor pointer |
| * @skb : the socket buffer |
| * Description : |
| * This function will read timestamp from the descriptor & pass it to stack. |
| * and also perform some sanity checks. |
| */ |
| static void stmmac_get_tx_hwtstamp(struct stmmac_priv *priv, |
| struct dma_desc *p, struct sk_buff *skb) |
| { |
| struct skb_shared_hwtstamps shhwtstamp; |
| bool found = false; |
| u64 ns = 0; |
| |
| if (!priv->hwts_tx_en) |
| return; |
| |
| /* exit if skb doesn't support hw tstamp */ |
| if (likely(!skb || !(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS))) |
| return; |
| |
| /* check tx tstamp status */ |
| if (stmmac_get_tx_timestamp_status(priv, p)) { |
| stmmac_get_timestamp(priv, p, priv->adv_ts, &ns); |
| found = true; |
| } else if (!stmmac_get_mac_tx_timestamp(priv, priv->hw, &ns)) { |
| found = true; |
| } |
| |
| if (found) { |
| memset(&shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps)); |
| shhwtstamp.hwtstamp = ns_to_ktime(ns); |
| |
| netdev_dbg(priv->dev, "get valid TX hw timestamp %llu\n", ns); |
| /* pass tstamp to stack */ |
| skb_tstamp_tx(skb, &shhwtstamp); |
| } |
| } |
| |
| /* stmmac_get_rx_hwtstamp - get HW RX timestamps |
| * @priv: driver private structure |
| * @p : descriptor pointer |
| * @np : next descriptor pointer |
| * @skb : the socket buffer |
| * Description : |
| * This function will read received packet's timestamp from the descriptor |
| * and pass it to stack. It also perform some sanity checks. |
| */ |
| static void stmmac_get_rx_hwtstamp(struct stmmac_priv *priv, struct dma_desc *p, |
| struct dma_desc *np, struct sk_buff *skb) |
| { |
| struct skb_shared_hwtstamps *shhwtstamp = NULL; |
| struct dma_desc *desc = p; |
| u64 ns = 0; |
| |
| if (!priv->hwts_rx_en) |
| return; |
| /* For GMAC4, the valid timestamp is from CTX next desc. */ |
| if (priv->plat->has_gmac4 || priv->plat->has_xgmac) |
| desc = np; |
| |
| /* Check if timestamp is available */ |
| if (stmmac_get_rx_timestamp_status(priv, p, np, priv->adv_ts)) { |
| stmmac_get_timestamp(priv, desc, priv->adv_ts, &ns); |
| netdev_dbg(priv->dev, "get valid RX hw timestamp %llu\n", ns); |
| shhwtstamp = skb_hwtstamps(skb); |
| memset(shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps)); |
| shhwtstamp->hwtstamp = ns_to_ktime(ns); |
| } else { |
| netdev_dbg(priv->dev, "cannot get RX hw timestamp\n"); |
| } |
| } |
| |
| /** |
| * stmmac_hwtstamp_set - control hardware timestamping. |
| * @dev: device pointer. |
| * @ifr: An IOCTL specific structure, that can contain a pointer to |
| * a proprietary structure used to pass information to the driver. |
| * Description: |
| * This function configures the MAC to enable/disable both outgoing(TX) |
| * and incoming(RX) packets time stamping based on user input. |
| * Return Value: |
| * 0 on success and an appropriate -ve integer on failure. |
| */ |
| static int stmmac_hwtstamp_set(struct net_device *dev, struct ifreq *ifr) |
| { |
| struct stmmac_priv *priv = netdev_priv(dev); |
| struct hwtstamp_config config; |
| struct timespec64 now; |
| u64 temp = 0; |
| u32 ptp_v2 = 0; |
| u32 tstamp_all = 0; |
| u32 ptp_over_ipv4_udp = 0; |
| u32 ptp_over_ipv6_udp = 0; |
| u32 ptp_over_ethernet = 0; |
| u32 snap_type_sel = 0; |
| u32 ts_master_en = 0; |
| u32 ts_event_en = 0; |
| u32 sec_inc = 0; |
| u32 value = 0; |
| bool xmac; |
| |
| xmac = priv->plat->has_gmac4 || priv->plat->has_xgmac; |
| |
| if (!(priv->dma_cap.time_stamp || priv->adv_ts)) { |
| netdev_alert(priv->dev, "No support for HW time stamping\n"); |
| priv->hwts_tx_en = 0; |
| priv->hwts_rx_en = 0; |
| |
| return -EOPNOTSUPP; |
| } |
| |
| if (copy_from_user(&config, ifr->ifr_data, |
| sizeof(config))) |
| return -EFAULT; |
| |
| netdev_dbg(priv->dev, "%s config flags:0x%x, tx_type:0x%x, rx_filter:0x%x\n", |
| __func__, config.flags, config.tx_type, config.rx_filter); |
| |
| /* reserved for future extensions */ |
| if (config.flags) |
| return -EINVAL; |
| |
| if (config.tx_type != HWTSTAMP_TX_OFF && |
| config.tx_type != HWTSTAMP_TX_ON) |
| return -ERANGE; |
| |
| if (priv->adv_ts) { |
| switch (config.rx_filter) { |
| case HWTSTAMP_FILTER_NONE: |
| /* time stamp no incoming packet at all */ |
| config.rx_filter = HWTSTAMP_FILTER_NONE; |
| break; |
| |
| case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: |
| /* PTP v1, UDP, any kind of event packet */ |
| config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT; |
| /* 'xmac' hardware can support Sync, Pdelay_Req and |
| * Pdelay_resp by setting bit14 and bits17/16 to 01 |
| * This leaves Delay_Req timestamps out. |
| * Enable all events *and* general purpose message |
| * timestamping |
| */ |
| snap_type_sel = PTP_TCR_SNAPTYPSEL_1; |
| ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; |
| ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; |
| break; |
| |
| case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: |
| /* PTP v1, UDP, Sync packet */ |
| config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_SYNC; |
| /* take time stamp for SYNC messages only */ |
| ts_event_en = PTP_TCR_TSEVNTENA; |
| |
| ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; |
| ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; |
| break; |
| |
| case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: |
| /* PTP v1, UDP, Delay_req packet */ |
| config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ; |
| /* take time stamp for Delay_Req messages only */ |
| ts_master_en = PTP_TCR_TSMSTRENA; |
| ts_event_en = PTP_TCR_TSEVNTENA; |
| |
| ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; |
| ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; |
| break; |
| |
| case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: |
| /* PTP v2, UDP, any kind of event packet */ |
| config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT; |
| ptp_v2 = PTP_TCR_TSVER2ENA; |
| /* take time stamp for all event messages */ |
| snap_type_sel = PTP_TCR_SNAPTYPSEL_1; |
| |
| ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; |
| ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; |
| break; |
| |
| case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: |
| /* PTP v2, UDP, Sync packet */ |
| config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_SYNC; |
| ptp_v2 = PTP_TCR_TSVER2ENA; |
| /* take time stamp for SYNC messages only */ |
| ts_event_en = PTP_TCR_TSEVNTENA; |
| |
| ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; |
| ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; |
| break; |
| |
| case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: |
| /* PTP v2, UDP, Delay_req packet */ |
| config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ; |
| ptp_v2 = PTP_TCR_TSVER2ENA; |
| /* take time stamp for Delay_Req messages only */ |
| ts_master_en = PTP_TCR_TSMSTRENA; |
| ts_event_en = PTP_TCR_TSEVNTENA; |
| |
| ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; |
| ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; |
| break; |
| |
| case HWTSTAMP_FILTER_PTP_V2_EVENT: |
| /* PTP v2/802.AS1 any layer, any kind of event packet */ |
| config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; |
| ptp_v2 = PTP_TCR_TSVER2ENA; |
| snap_type_sel = PTP_TCR_SNAPTYPSEL_1; |
| ts_event_en = PTP_TCR_TSEVNTENA; |
| ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; |
| ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; |
| ptp_over_ethernet = PTP_TCR_TSIPENA; |
| break; |
| |
| case HWTSTAMP_FILTER_PTP_V2_SYNC: |
| /* PTP v2/802.AS1, any layer, Sync packet */ |
| config.rx_filter = HWTSTAMP_FILTER_PTP_V2_SYNC; |
| ptp_v2 = PTP_TCR_TSVER2ENA; |
| /* take time stamp for SYNC messages only */ |
| ts_event_en = PTP_TCR_TSEVNTENA; |
| |
| ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; |
| ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; |
| ptp_over_ethernet = PTP_TCR_TSIPENA; |
| break; |
| |
| case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: |
| /* PTP v2/802.AS1, any layer, Delay_req packet */ |
| config.rx_filter = HWTSTAMP_FILTER_PTP_V2_DELAY_REQ; |
| ptp_v2 = PTP_TCR_TSVER2ENA; |
| /* take time stamp for Delay_Req messages only */ |
| ts_master_en = PTP_TCR_TSMSTRENA; |
| ts_event_en = PTP_TCR_TSEVNTENA; |
| |
| ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; |
| ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; |
| ptp_over_ethernet = PTP_TCR_TSIPENA; |
| break; |
| |
| case HWTSTAMP_FILTER_NTP_ALL: |
| case HWTSTAMP_FILTER_ALL: |
| /* time stamp any incoming packet */ |
| config.rx_filter = HWTSTAMP_FILTER_ALL; |
| tstamp_all = PTP_TCR_TSENALL; |
| break; |
| |
| default: |
| return -ERANGE; |
| } |
| } else { |
| switch (config.rx_filter) { |
| case HWTSTAMP_FILTER_NONE: |
| config.rx_filter = HWTSTAMP_FILTER_NONE; |
| break; |
| default: |
| /* PTP v1, UDP, any kind of event packet */ |
| config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT; |
| break; |
| } |
| } |
| priv->hwts_rx_en = ((config.rx_filter == HWTSTAMP_FILTER_NONE) ? 0 : 1); |
| priv->hwts_tx_en = config.tx_type == HWTSTAMP_TX_ON; |
| |
| if (!priv->hwts_tx_en && !priv->hwts_rx_en) |
| stmmac_config_hw_tstamping(priv, priv->ptpaddr, 0); |
| else { |
| value = (PTP_TCR_TSENA | PTP_TCR_TSCFUPDT | PTP_TCR_TSCTRLSSR | |
| tstamp_all | ptp_v2 | ptp_over_ethernet | |
| ptp_over_ipv6_udp | ptp_over_ipv4_udp | ts_event_en | |
| ts_master_en | snap_type_sel); |
| stmmac_config_hw_tstamping(priv, priv->ptpaddr, value); |
| |
| /* program Sub Second Increment reg */ |
| stmmac_config_sub_second_increment(priv, |
| priv->ptpaddr, priv->plat->clk_ptp_rate, |
| xmac, &sec_inc); |
| temp = div_u64(1000000000ULL, sec_inc); |
| |
| /* Store sub second increment and flags for later use */ |
| priv->sub_second_inc = sec_inc; |
| priv->systime_flags = value; |
| |
| /* calculate default added value: |
| * formula is : |
| * addend = (2^32)/freq_div_ratio; |
| * where, freq_div_ratio = 1e9ns/sec_inc |
| */ |
| temp = (u64)(temp << 32); |
| priv->default_addend = div_u64(temp, priv->plat->clk_ptp_rate); |
| stmmac_config_addend(priv, priv->ptpaddr, priv->default_addend); |
| |
| /* initialize system time */ |
| ktime_get_real_ts64(&now); |
| |
| /* lower 32 bits of tv_sec are safe until y2106 */ |
| stmmac_init_systime(priv, priv->ptpaddr, |
| (u32)now.tv_sec, now.tv_nsec); |
| } |
| |
| memcpy(&priv->tstamp_config, &config, sizeof(config)); |
| |
| return copy_to_user(ifr->ifr_data, &config, |
| sizeof(config)) ? -EFAULT : 0; |
| } |
| |
| /** |
| * stmmac_hwtstamp_get - read hardware timestamping. |
| * @dev: device pointer. |
| * @ifr: An IOCTL specific structure, that can contain a pointer to |
| * a proprietary structure used to pass information to the driver. |
| * Description: |
| * This function obtain the current hardware timestamping settings |
| as requested. |
| */ |
| static int stmmac_hwtstamp_get(struct net_device *dev, struct ifreq *ifr) |
| { |
| struct stmmac_priv *priv = netdev_priv(dev); |
| struct hwtstamp_config *config = &priv->tstamp_config; |
| |
| if (!(priv->dma_cap.time_stamp || priv->dma_cap.atime_stamp)) |
| return -EOPNOTSUPP; |
| |
| return copy_to_user(ifr->ifr_data, config, |
| sizeof(*config)) ? -EFAULT : 0; |
| } |
| |
| /** |
| * stmmac_init_ptp - init PTP |
| * @priv: driver private structure |
| * Description: this is to verify if the HW supports the PTPv1 or PTPv2. |
| * This is done by looking at the HW cap. register. |
| * This function also registers the ptp driver. |
| */ |
| static int stmmac_init_ptp(struct stmmac_priv *priv) |
| { |
| bool xmac = priv->plat->has_gmac4 || priv->plat->has_xgmac; |
| |
| if (!(priv->dma_cap.time_stamp || priv->dma_cap.atime_stamp)) |
| return -EOPNOTSUPP; |
| |
| priv->adv_ts = 0; |
| /* Check if adv_ts can be enabled for dwmac 4.x / xgmac core */ |
| if (xmac && priv->dma_cap.atime_stamp) |
| priv->adv_ts = 1; |
| /* Dwmac 3.x core with extend_desc can support adv_ts */ |
| else if (priv->extend_desc && priv->dma_cap.atime_stamp) |
| priv->adv_ts = 1; |
| |
| if (priv->dma_cap.time_stamp) |
| netdev_info(priv->dev, "IEEE 1588-2002 Timestamp supported\n"); |
| |
| if (priv->adv_ts) |
| netdev_info(priv->dev, |
| "IEEE 1588-2008 Advanced Timestamp supported\n"); |
| |
| priv->hwts_tx_en = 0; |
| priv->hwts_rx_en = 0; |
| |
| stmmac_ptp_register(priv); |
| |
| return 0; |
| } |
| |
| static void stmmac_release_ptp(struct stmmac_priv *priv) |
| { |
| if (priv->plat->clk_ptp_ref) |
| clk_disable_unprepare(priv->plat->clk_ptp_ref); |
| stmmac_ptp_unregister(priv); |
| } |
| |
| /** |
| * stmmac_mac_flow_ctrl - Configure flow control in all queues |
| * @priv: driver private structure |
| * Description: It is used for configuring the flow control in all queues |
| */ |
| static void stmmac_mac_flow_ctrl(struct stmmac_priv *priv, u32 duplex) |
| { |
| u32 tx_cnt = priv->plat->tx_queues_to_use; |
| |
| stmmac_flow_ctrl(priv, priv->hw, duplex, priv->flow_ctrl, |
| priv->pause, tx_cnt); |
| } |
| |
| static void stmmac_validate(struct phylink_config *config, |
| unsigned long *supported, |
| struct phylink_link_state *state) |
| { |
| struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev)); |
| __ETHTOOL_DECLARE_LINK_MODE_MASK(mac_supported) = { 0, }; |
| __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; |
| int tx_cnt = priv->plat->tx_queues_to_use; |
| int max_speed = priv->plat->max_speed; |
| |
| phylink_set(mac_supported, 10baseT_Half); |
| phylink_set(mac_supported, 10baseT_Full); |
| phylink_set(mac_supported, 100baseT_Half); |
| phylink_set(mac_supported, 100baseT_Full); |
| phylink_set(mac_supported, 1000baseT_Half); |
| phylink_set(mac_supported, 1000baseT_Full); |
| phylink_set(mac_supported, 1000baseKX_Full); |
| |
| phylink_set(mac_supported, Autoneg); |
| phylink_set(mac_supported, Pause); |
| phylink_set(mac_supported, Asym_Pause); |
| phylink_set_port_modes(mac_supported); |
| |
| /* Cut down 1G if asked to */ |
| if ((max_speed > 0) && (max_speed < 1000)) { |
| phylink_set(mask, 1000baseT_Full); |
| phylink_set(mask, 1000baseX_Full); |
| } else if (priv->plat->has_xgmac) { |
| if (!max_speed || (max_speed >= 2500)) { |
| phylink_set(mac_supported, 2500baseT_Full); |
| phylink_set(mac_supported, 2500baseX_Full); |
| } |
| if (!max_speed || (max_speed >= 5000)) { |
| phylink_set(mac_supported, 5000baseT_Full); |
| } |
| if (!max_speed || (max_speed >= 10000)) { |
| phylink_set(mac_supported, 10000baseSR_Full); |
| phylink_set(mac_supported, 10000baseLR_Full); |
| phylink_set(mac_supported, 10000baseER_Full); |
| phylink_set(mac_supported, 10000baseLRM_Full); |
| phylink_set(mac_supported, 10000baseT_Full); |
| phylink_set(mac_supported, 10000baseKX4_Full); |
| phylink_set(mac_supported, 10000baseKR_Full); |
| } |
| } |
| |
| /* Half-Duplex can only work with single queue */ |
| if (tx_cnt > 1) { |
| phylink_set(mask, 10baseT_Half); |
| phylink_set(mask, 100baseT_Half); |
| phylink_set(mask, 1000baseT_Half); |
| } |
| |
| bitmap_and(supported, supported, mac_supported, |
| __ETHTOOL_LINK_MODE_MASK_NBITS); |
| bitmap_andnot(supported, supported, mask, |
| __ETHTOOL_LINK_MODE_MASK_NBITS); |
| bitmap_and(state->advertising, state->advertising, mac_supported, |
| __ETHTOOL_LINK_MODE_MASK_NBITS); |
| bitmap_andnot(state->advertising, state->advertising, mask, |
| __ETHTOOL_LINK_MODE_MASK_NBITS); |
| } |
| |
| static void stmmac_mac_pcs_get_state(struct phylink_config *config, |
| struct phylink_link_state *state) |
| { |
| state->link = 0; |
| } |
| |
| static void stmmac_mac_config(struct phylink_config *config, unsigned int mode, |
| const struct phylink_link_state *state) |
| { |
| struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev)); |
| u32 ctrl; |
| |
| ctrl = readl(priv->ioaddr + MAC_CTRL_REG); |
| ctrl &= ~priv->hw->link.speed_mask; |
| |
| if (state->interface == PHY_INTERFACE_MODE_USXGMII) { |
| switch (state->speed) { |
| case SPEED_10000: |
| ctrl |= priv->hw->link.xgmii.speed10000; |
| break; |
| case SPEED_5000: |
| ctrl |= priv->hw->link.xgmii.speed5000; |
| break; |
| case SPEED_2500: |
| ctrl |= priv->hw->link.xgmii.speed2500; |
| break; |
| default: |
| return; |
| } |
| } else { |
| switch (state->speed) { |
| case SPEED_2500: |
| ctrl |= priv->hw->link.speed2500; |
| break; |
| case SPEED_1000: |
| ctrl |= priv->hw->link.speed1000; |
| break; |
| case SPEED_100: |
| ctrl |= priv->hw->link.speed100; |
| break; |
| case SPEED_10: |
| ctrl |= priv->hw->link.speed10; |
| break; |
| default: |
| return; |
| } |
| } |
| |
| priv->speed = state->speed; |
| |
| if (priv->plat->fix_mac_speed) |
| priv->plat->fix_mac_speed(priv->plat->bsp_priv, state->speed); |
| |
| if (!state->duplex) |
| ctrl &= ~priv->hw->link.duplex; |
| else |
| ctrl |= priv->hw->link.duplex; |
| |
| /* Flow Control operation */ |
| if (state->pause) |
| stmmac_mac_flow_ctrl(priv, state->duplex); |
| |
| writel(ctrl, priv->ioaddr + MAC_CTRL_REG); |
| } |
| |
| static void stmmac_mac_an_restart(struct phylink_config *config) |
| { |
| /* Not Supported */ |
| } |
| |
| static void stmmac_mac_link_down(struct phylink_config *config, |
| unsigned int mode, phy_interface_t interface) |
| { |
| struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev)); |
| |
| stmmac_mac_set(priv, priv->ioaddr, false); |
| priv->eee_active = false; |
| stmmac_eee_init(priv); |
| stmmac_set_eee_pls(priv, priv->hw, false); |
| } |
| |
| static void stmmac_mac_link_up(struct phylink_config *config, |
| unsigned int mode, phy_interface_t interface, |
| struct phy_device *phy) |
| { |
| struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev)); |
| |
| stmmac_mac_set(priv, priv->ioaddr, true); |
| if (phy && priv->dma_cap.eee) { |
| priv->eee_active = phy_init_eee(phy, 1) >= 0; |
| priv->eee_enabled = stmmac_eee_init(priv); |
| stmmac_set_eee_pls(priv, priv->hw, true); |
| } |
| } |
| |
| static const struct phylink_mac_ops stmmac_phylink_mac_ops = { |
| .validate = stmmac_validate, |
| .mac_pcs_get_state = stmmac_mac_pcs_get_state, |
| .mac_config = stmmac_mac_config, |
| .mac_an_restart = stmmac_mac_an_restart, |
| .mac_link_down = stmmac_mac_link_down, |
| .mac_link_up = stmmac_mac_link_up, |
| }; |
| |
| /** |
| * stmmac_check_pcs_mode - verify if RGMII/SGMII is supported |
| * @priv: driver private structure |
| * Description: this is to verify if the HW supports the PCS. |
| * Physical Coding Sublayer (PCS) interface that can be used when the MAC is |
| * configured for the TBI, RTBI, or SGMII PHY interface. |
| */ |
| static void stmmac_check_pcs_mode(struct stmmac_priv *priv) |
| { |
| int interface = priv->plat->interface; |
| |
| if (priv->dma_cap.pcs) { |
| if ((interface == PHY_INTERFACE_MODE_RGMII) || |
| (interface == PHY_INTERFACE_MODE_RGMII_ID) || |
| (interface == PHY_INTERFACE_MODE_RGMII_RXID) || |
| (interface == PHY_INTERFACE_MODE_RGMII_TXID)) { |
| netdev_dbg(priv->dev, "PCS RGMII support enabled\n"); |
| priv->hw->pcs = STMMAC_PCS_RGMII; |
| } else if (interface == PHY_INTERFACE_MODE_SGMII) { |
| netdev_dbg(priv->dev, "PCS SGMII support enabled\n"); |
| priv->hw->pcs = STMMAC_PCS_SGMII; |
| } |
| } |
| } |
| |
| /** |
| * stmmac_init_phy - PHY initialization |
| * @dev: net device structure |
| * Description: it initializes the driver's PHY state, and attaches the PHY |
| * to the mac driver. |
| * Return value: |
| * 0 on success |
| */ |
| static int stmmac_init_phy(struct net_device *dev) |
| { |
| struct stmmac_priv *priv = netdev_priv(dev); |
| struct device_node *node; |
| int ret; |
| |
| node = priv->plat->phylink_node; |
| |
| if (node) |
| ret = phylink_of_phy_connect(priv->phylink, node, 0); |
| |
| /* Some DT bindings do not set-up the PHY handle. Let's try to |
| * manually parse it |
| */ |
| if (!node || ret) { |
| int addr = priv->plat->phy_addr; |
| struct phy_device *phydev; |
| |
| phydev = mdiobus_get_phy(priv->mii, addr); |
| if (!phydev) { |
| netdev_err(priv->dev, "no phy at addr %d\n", addr); |
| return -ENODEV; |
| } |
| |
| ret = phylink_connect_phy(priv->phylink, phydev); |
| } |
| |
| return ret; |
| } |
| |
| static int stmmac_phy_setup(struct stmmac_priv *priv) |
| { |
| struct fwnode_handle *fwnode = of_fwnode_handle(priv->plat->phylink_node); |
| int mode = priv->plat->phy_interface; |
| struct phylink *phylink; |
| |
| priv->phylink_config.dev = &priv->dev->dev; |
| priv->phylink_config.type = PHYLINK_NETDEV; |
| |
| phylink = phylink_create(&priv->phylink_config, fwnode, |
| mode, &stmmac_phylink_mac_ops); |
| if (IS_ERR(phylink)) |
| return PTR_ERR(phylink); |
| |
| priv->phylink = phylink; |
| return 0; |
| } |
| |
| static void stmmac_display_rx_rings(struct stmmac_priv *priv) |
| { |
| u32 rx_cnt = priv->plat->rx_queues_to_use; |
| void *head_rx; |
| u32 queue; |
| |
| /* Display RX rings */ |
| for (queue = 0; queue < rx_cnt; queue++) { |
| struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; |
| |
| pr_info("\tRX Queue %u rings\n", queue); |
| |
| if (priv->extend_desc) |
| head_rx = (void *)rx_q->dma_erx; |
| else |
| head_rx = (void *)rx_q->dma_rx; |
| |
| /* Display RX ring */ |
| stmmac_display_ring(priv, head_rx, DMA_RX_SIZE, true); |
| } |
| } |
| |
| static void stmmac_display_tx_rings(struct stmmac_priv *priv) |
| { |
| u32 tx_cnt = priv->plat->tx_queues_to_use; |
| void *head_tx; |
| u32 queue; |
| |
| /* Display TX rings */ |
| for (queue = 0; queue < tx_cnt; queue++) { |
| struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; |
| |
| pr_info("\tTX Queue %d rings\n", queue); |
| |
| if (priv->extend_desc) |
| head_tx = (void *)tx_q->dma_etx; |
| else if (tx_q->tbs & STMMAC_TBS_AVAIL) |
| head_tx = (void *)tx_q->dma_entx; |
| else |
| head_tx = (void *)tx_q->dma_tx; |
| |
| stmmac_display_ring(priv, head_tx, DMA_TX_SIZE, false); |
| } |
| } |
| |
| static void stmmac_display_rings(struct stmmac_priv *priv) |
| { |
| /* Display RX ring */ |
| stmmac_display_rx_rings(priv); |
| |
| /* Display TX ring */ |
| stmmac_display_tx_rings(priv); |
| } |
| |
| static int stmmac_set_bfsize(int mtu, int bufsize) |
| { |
| int ret = bufsize; |
| |
| if (mtu >= BUF_SIZE_8KiB) |
| ret = BUF_SIZE_16KiB; |
| else if (mtu >= BUF_SIZE_4KiB) |
| ret = BUF_SIZE_8KiB; |
| else if (mtu >= BUF_SIZE_2KiB) |
| ret = BUF_SIZE_4KiB; |
| else if (mtu > DEFAULT_BUFSIZE) |
| ret = BUF_SIZE_2KiB; |
| else |
| ret = DEFAULT_BUFSIZE; |
| |
| return ret; |
| } |
| |
| /** |
| * stmmac_clear_rx_descriptors - clear RX descriptors |
| * @priv: driver private structure |
| * @queue: RX queue index |
| * Description: this function is called to clear the RX descriptors |
| * in case of both basic and extended descriptors are used. |
| */ |
| static void stmmac_clear_rx_descriptors(struct stmmac_priv *priv, u32 queue) |
| { |
| struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; |
| int i; |
| |
| /* Clear the RX descriptors */ |
| for (i = 0; i < DMA_RX_SIZE; i++) |
| if (priv->extend_desc) |
| stmmac_init_rx_desc(priv, &rx_q->dma_erx[i].basic, |
| priv->use_riwt, priv->mode, |
| (i == DMA_RX_SIZE - 1), |
| priv->dma_buf_sz); |
| else |
| stmmac_init_rx_desc(priv, &rx_q->dma_rx[i], |
| priv->use_riwt, priv->mode, |
| (i == DMA_RX_SIZE - 1), |
| priv->dma_buf_sz); |
| } |
| |
| /** |
| * stmmac_clear_tx_descriptors - clear tx descriptors |
| * @priv: driver private structure |
| * @queue: TX queue index. |
| * Description: this function is called to clear the TX descriptors |
| * in case of both basic and extended descriptors are used. |
| */ |
| static void stmmac_clear_tx_descriptors(struct stmmac_priv *priv, u32 queue) |
| { |
| struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; |
| int i; |
| |
| /* Clear the TX descriptors */ |
| for (i = 0; i < DMA_TX_SIZE; i++) { |
| int last = (i == (DMA_TX_SIZE - 1)); |
| struct dma_desc *p; |
| |
| if (priv->extend_desc) |
| p = &tx_q->dma_etx[i].basic; |
| else if (tx_q->tbs & STMMAC_TBS_AVAIL) |
| p = &tx_q->dma_entx[i].basic; |
| else |
| p = &tx_q->dma_tx[i]; |
| |
| stmmac_init_tx_desc(priv, p, priv->mode, last); |
| } |
| } |
| |
| /** |
| * stmmac_clear_descriptors - clear descriptors |
| * @priv: driver private structure |
| * Description: this function is called to clear the TX and RX descriptors |
| * in case of both basic and extended descriptors are used. |
| */ |
| static void stmmac_clear_descriptors(struct stmmac_priv *priv) |
| { |
| u32 rx_queue_cnt = priv->plat->rx_queues_to_use; |
| u32 tx_queue_cnt = priv->plat->tx_queues_to_use; |
| u32 queue; |
| |
| /* Clear the RX descriptors */ |
| for (queue = 0; queue < rx_queue_cnt; queue++) |
| stmmac_clear_rx_descriptors(priv, queue); |
| |
| /* Clear the TX descriptors */ |
| for (queue = 0; queue < tx_queue_cnt; queue++) |
| stmmac_clear_tx_descriptors(priv, queue); |
| } |
| |
| /** |
| * stmmac_init_rx_buffers - init the RX descriptor buffer. |
| * @priv: driver private structure |
| * @p: descriptor pointer |
| * @i: descriptor index |
| * @flags: gfp flag |
| * @queue: RX queue index |
| * Description: this function is called to allocate a receive buffer, perform |
| * the DMA mapping and init the descriptor. |
| */ |
| static int stmmac_init_rx_buffers(struct stmmac_priv *priv, struct dma_desc *p, |
| int i, gfp_t flags, u32 queue) |
| { |
| struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; |
| struct stmmac_rx_buffer *buf = &rx_q->buf_pool[i]; |
| |
| buf->page = page_pool_dev_alloc_pages(rx_q->page_pool); |
| if (!buf->page) |
| return -ENOMEM; |
| |
| if (priv->sph) { |
| buf->sec_page = page_pool_dev_alloc_pages(rx_q->page_pool); |
| if (!buf->sec_page) |
| return -ENOMEM; |
| |
| buf->sec_addr = page_pool_get_dma_addr(buf->sec_page); |
| stmmac_set_desc_sec_addr(priv, p, buf->sec_addr); |
| } else { |
| buf->sec_page = NULL; |
| } |
| |
| buf->addr = page_pool_get_dma_addr(buf->page); |
| stmmac_set_desc_addr(priv, p, buf->addr); |
| if (priv->dma_buf_sz == BUF_SIZE_16KiB) |
| stmmac_init_desc3(priv, p); |
| |
| return 0; |
| } |
| |
| /** |
| * stmmac_free_rx_buffer - free RX dma buffers |
| * @priv: private structure |
| * @queue: RX queue index |
| * @i: buffer index. |
| */ |
| static void stmmac_free_rx_buffer(struct stmmac_priv *priv, u32 queue, int i) |
| { |
| struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; |
| struct stmmac_rx_buffer *buf = &rx_q->buf_pool[i]; |
| |
| if (buf->page) |
| page_pool_put_page(rx_q->page_pool, buf->page, false); |
| buf->page = NULL; |
| |
| if (buf->sec_page) |
| page_pool_put_page(rx_q->page_pool, buf->sec_page, false); |
| buf->sec_page = NULL; |
| } |
| |
| /** |
| * stmmac_free_tx_buffer - free RX dma buffers |
| * @priv: private structure |
| * @queue: RX queue index |
| * @i: buffer index. |
| */ |
| static void stmmac_free_tx_buffer(struct stmmac_priv *priv, u32 queue, int i) |
| { |
| struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; |
| |
| if (tx_q->tx_skbuff_dma[i].buf) { |
| if (tx_q->tx_skbuff_dma[i].map_as_page) |
| dma_unmap_page(priv->device, |
| tx_q->tx_skbuff_dma[i].buf, |
| tx_q->tx_skbuff_dma[i].len, |
| DMA_TO_DEVICE); |
| else |
| dma_unmap_single(priv->device, |
| tx_q->tx_skbuff_dma[i].buf, |
| tx_q->tx_skbuff_dma[i].len, |
| DMA_TO_DEVICE); |
| } |
| |
| if (tx_q->tx_skbuff[i]) { |
| dev_kfree_skb_any(tx_q->tx_skbuff[i]); |
| tx_q->tx_skbuff[i] = NULL; |
| tx_q->tx_skbuff_dma[i].buf = 0; |
| tx_q->tx_skbuff_dma[i].map_as_page = false; |
| } |
| } |
| |
| /** |
| * init_dma_rx_desc_rings - init the RX descriptor rings |
| * @dev: net device structure |
| * @flags: gfp flag. |
| * Description: this function initializes the DMA RX descriptors |
| * and allocates the socket buffers. It supports the chained and ring |
| * modes. |
| */ |
| static int init_dma_rx_desc_rings(struct net_device *dev, gfp_t flags) |
| { |
| struct stmmac_priv *priv = netdev_priv(dev); |
| u32 rx_count = priv->plat->rx_queues_to_use; |
| int ret = -ENOMEM; |
| int queue; |
| int i; |
| |
| /* RX INITIALIZATION */ |
| netif_dbg(priv, probe, priv->dev, |
| "SKB addresses:\nskb\t\tskb data\tdma data\n"); |
| |
| for (queue = 0; queue < rx_count; queue++) { |
| struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; |
| |
| netif_dbg(priv, probe, priv->dev, |
| "(%s) dma_rx_phy=0x%08x\n", __func__, |
| (u32)rx_q->dma_rx_phy); |
| |
| stmmac_clear_rx_descriptors(priv, queue); |
| |
| for (i = 0; i < DMA_RX_SIZE; i++) { |
| struct dma_desc *p; |
| |
| if (priv->extend_desc) |
| p = &((rx_q->dma_erx + i)->basic); |
| else |
| p = rx_q->dma_rx + i; |
| |
| ret = stmmac_init_rx_buffers(priv, p, i, flags, |
| queue); |
| if (ret) |
| goto err_init_rx_buffers; |
| } |
| |
| rx_q->cur_rx = 0; |
| rx_q->dirty_rx = (unsigned int)(i - DMA_RX_SIZE); |
| |
| /* Setup the chained descriptor addresses */ |
| if (priv->mode == STMMAC_CHAIN_MODE) { |
| if (priv->extend_desc) |
| stmmac_mode_init(priv, rx_q->dma_erx, |
| rx_q->dma_rx_phy, DMA_RX_SIZE, 1); |
| else |
| stmmac_mode_init(priv, rx_q->dma_rx, |
| rx_q->dma_rx_phy, DMA_RX_SIZE, 0); |
| } |
| } |
| |
| return 0; |
| |
| err_init_rx_buffers: |
| while (queue >= 0) { |
| while (--i >= 0) |
| stmmac_free_rx_buffer(priv, queue, i); |
| |
| if (queue == 0) |
| break; |
| |
| i = DMA_RX_SIZE; |
| queue--; |
| } |
| |
| return ret; |
| } |
| |
| /** |
| * init_dma_tx_desc_rings - init the TX descriptor rings |
| * @dev: net device structure. |
| * Description: this function initializes the DMA TX descriptors |
| * and allocates the socket buffers. It supports the chained and ring |
| * modes. |
| */ |
| static int init_dma_tx_desc_rings(struct net_device *dev) |
| { |
| struct stmmac_priv *priv = netdev_priv(dev); |
| u32 tx_queue_cnt = priv->plat->tx_queues_to_use; |
| u32 queue; |
| int i; |
| |
| for (queue = 0; queue < tx_queue_cnt; queue++) { |
| struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; |
| |
| netif_dbg(priv, probe, priv->dev, |
| "(%s) dma_tx_phy=0x%08x\n", __func__, |
| (u32)tx_q->dma_tx_phy); |
| |
| /* Setup the chained descriptor addresses */ |
| if (priv->mode == STMMAC_CHAIN_MODE) { |
| if (priv->extend_desc) |
| stmmac_mode_init(priv, tx_q->dma_etx, |
| tx_q->dma_tx_phy, DMA_TX_SIZE, 1); |
| else if (!(tx_q->tbs & STMMAC_TBS_AVAIL)) |
| stmmac_mode_init(priv, tx_q->dma_tx, |
| tx_q->dma_tx_phy, DMA_TX_SIZE, 0); |
| } |
| |
| for (i = 0; i < DMA_TX_SIZE; i++) { |
| struct dma_desc *p; |
| if (priv->extend_desc) |
| p = &((tx_q->dma_etx + i)->basic); |
| else if (tx_q->tbs & STMMAC_TBS_AVAIL) |
| p = &((tx_q->dma_entx + i)->basic); |
| else |
| p = tx_q->dma_tx + i; |
| |
| stmmac_clear_desc(priv, p); |
| |
| tx_q->tx_skbuff_dma[i].buf = 0; |
| tx_q->tx_skbuff_dma[i].map_as_page = false; |
| tx_q->tx_skbuff_dma[i].len = 0; |
| tx_q->tx_skbuff_dma[i].last_segment = false; |
| tx_q->tx_skbuff[i] = NULL; |
| } |
| |
| tx_q->dirty_tx = 0; |
| tx_q->cur_tx = 0; |
| tx_q->mss = 0; |
| |
| netdev_tx_reset_queue(netdev_get_tx_queue(priv->dev, queue)); |
| } |
| |
| return 0; |
| } |
| |
| /** |
| * init_dma_desc_rings - init the RX/TX descriptor rings |
| * @dev: net device structure |
| * @flags: gfp flag. |
| * Description: this function initializes the DMA RX/TX descriptors |
| * and allocates the socket buffers. It supports the chained and ring |
| * modes. |
| */ |
| static int init_dma_desc_rings(struct net_device *dev, gfp_t flags) |
| { |
| struct stmmac_priv *priv = netdev_priv(dev); |
| int ret; |
| |
| ret = init_dma_rx_desc_rings(dev, flags); |
| if (ret) |
| return ret; |
| |
| ret = init_dma_tx_desc_rings(dev); |
| |
| stmmac_clear_descriptors(priv); |
| |
| if (netif_msg_hw(priv)) |
| stmmac_display_rings(priv); |
| |
| return ret; |
| } |
| |
| /** |
| * dma_free_rx_skbufs - free RX dma buffers |
| * @priv: private structure |
| * @queue: RX queue index |
| */ |
| static void dma_free_rx_skbufs(struct stmmac_priv *priv, u32 queue) |
| { |
| int i; |
| |
| for (i = 0; i < DMA_RX_SIZE; i++) |
| stmmac_free_rx_buffer(priv, queue, i); |
| } |
| |
| /** |
| * dma_free_tx_skbufs - free TX dma buffers |
| * @priv: private structure |
| * @queue: TX queue index |
| */ |
| static void dma_free_tx_skbufs(struct stmmac_priv *priv, u32 queue) |
| { |
| int i; |
| |
| for (i = 0; i < DMA_TX_SIZE; i++) |
| stmmac_free_tx_buffer(priv, queue, i); |
| } |
| |
| /** |
| * free_dma_rx_desc_resources - free RX dma desc resources |
| * @priv: private structure |
| */ |
| static void free_dma_rx_desc_resources(struct stmmac_priv *priv) |
| { |
| u32 rx_count = priv->plat->rx_queues_to_use; |
| u32 queue; |
| |
| /* Free RX queue resources */ |
| for (queue = 0; queue < rx_count; queue++) { |
| struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; |
| |
| /* Release the DMA RX socket buffers */ |
| dma_free_rx_skbufs(priv, queue); |
| |
| /* Free DMA regions of consistent memory previously allocated */ |
| if (!priv->extend_desc) |
| dma_free_coherent(priv->device, |
| DMA_RX_SIZE * sizeof(struct dma_desc), |
| rx_q->dma_rx, rx_q->dma_rx_phy); |
| else |
| dma_free_coherent(priv->device, DMA_RX_SIZE * |
| sizeof(struct dma_extended_desc), |
| rx_q->dma_erx, rx_q->dma_rx_phy); |
| |
| kfree(rx_q->buf_pool); |
| if (rx_q->page_pool) |
| page_pool_destroy(rx_q->page_pool); |
| } |
| } |
| |
| /** |
| * free_dma_tx_desc_resources - free TX dma desc resources |
| * @priv: private structure |
| */ |
| static void free_dma_tx_desc_resources(struct stmmac_priv *priv) |
| { |
| u32 tx_count = priv->plat->tx_queues_to_use; |
| u32 queue; |
| |
| /* Free TX queue resources */ |
| for (queue = 0; queue < tx_count; queue++) { |
| struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; |
| size_t size; |
| void *addr; |
| |
| /* Release the DMA TX socket buffers */ |
| dma_free_tx_skbufs(priv, queue); |
| |
| if (priv->extend_desc) { |
| size = sizeof(struct dma_extended_desc); |
| addr = tx_q->dma_etx; |
| } else if (tx_q->tbs & STMMAC_TBS_AVAIL) { |
| size = sizeof(struct dma_edesc); |
| addr = tx_q->dma_entx; |
| } else { |
| size = sizeof(struct dma_desc); |
| addr = tx_q->dma_tx; |
| } |
| |
| size *= DMA_TX_SIZE; |
| |
| dma_free_coherent(priv->device, size, addr, tx_q->dma_tx_phy); |
| |
| kfree(tx_q->tx_skbuff_dma); |
| kfree(tx_q->tx_skbuff); |
| } |
| } |
| |
| /** |
| * alloc_dma_rx_desc_resources - alloc RX resources. |
| * @priv: private structure |
| * Description: according to which descriptor can be used (extend or basic) |
| * this function allocates the resources for TX and RX paths. In case of |
| * reception, for example, it pre-allocated the RX socket buffer in order to |
| * allow zero-copy mechanism. |
| */ |
| static int alloc_dma_rx_desc_resources(struct stmmac_priv *priv) |
| { |
| u32 rx_count = priv->plat->rx_queues_to_use; |
| int ret = -ENOMEM; |
| u32 queue; |
| |
| /* RX queues buffers and DMA */ |
| for (queue = 0; queue < rx_count; queue++) { |
| struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; |
| struct page_pool_params pp_params = { 0 }; |
| unsigned int num_pages; |
| |
| rx_q->queue_index = queue; |
| rx_q->priv_data = priv; |
| |
| pp_params.flags = PP_FLAG_DMA_MAP; |
| pp_params.pool_size = DMA_RX_SIZE; |
| num_pages = DIV_ROUND_UP(priv->dma_buf_sz, PAGE_SIZE); |
| pp_params.order = ilog2(num_pages); |
| pp_params.nid = dev_to_node(priv->device); |
| pp_params.dev = priv->device; |
| pp_params.dma_dir = DMA_FROM_DEVICE; |
| |
| rx_q->page_pool = page_pool_create(&pp_params); |
| if (IS_ERR(rx_q->page_pool)) { |
| ret = PTR_ERR(rx_q->page_pool); |
| rx_q->page_pool = NULL; |
| goto err_dma; |
| } |
| |
| rx_q->buf_pool = kcalloc(DMA_RX_SIZE, sizeof(*rx_q->buf_pool), |
| GFP_KERNEL); |
| if (!rx_q->buf_pool) |
| goto err_dma; |
| |
| if (priv->extend_desc) { |
| rx_q->dma_erx = dma_alloc_coherent(priv->device, |
| DMA_RX_SIZE * sizeof(struct dma_extended_desc), |
| &rx_q->dma_rx_phy, |
| GFP_KERNEL); |
| if (!rx_q->dma_erx) |
| goto err_dma; |
| |
| } else { |
| rx_q->dma_rx = dma_alloc_coherent(priv->device, |
| DMA_RX_SIZE * sizeof(struct dma_desc), |
| &rx_q->dma_rx_phy, |
| GFP_KERNEL); |
| if (!rx_q->dma_rx) |
| goto err_dma; |
| } |
| } |
| |
| return 0; |
| |
| err_dma: |
| free_dma_rx_desc_resources(priv); |
| |
| return ret; |
| } |
| |
| /** |
| * alloc_dma_tx_desc_resources - alloc TX resources. |
| * @priv: private structure |
| * Description: according to which descriptor can be used (extend or basic) |
| * this function allocates the resources for TX and RX paths. In case of |
| * reception, for example, it pre-allocated the RX socket buffer in order to |
| * allow zero-copy mechanism. |
| */ |
| static int alloc_dma_tx_desc_resources(struct stmmac_priv *priv) |
| { |
| u32 tx_count = priv->plat->tx_queues_to_use; |
| int ret = -ENOMEM; |
| u32 queue; |
| |
| /* TX queues buffers and DMA */ |
| for (queue = 0; queue < tx_count; queue++) { |
| struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; |
| size_t size; |
| void *addr; |
| |
| tx_q->queue_index = queue; |
| tx_q->priv_data = priv; |
| |
| tx_q->tx_skbuff_dma = kcalloc(DMA_TX_SIZE, |
| sizeof(*tx_q->tx_skbuff_dma), |
| GFP_KERNEL); |
| if (!tx_q->tx_skbuff_dma) |
| goto err_dma; |
| |
| tx_q->tx_skbuff = kcalloc(DMA_TX_SIZE, |
| sizeof(struct sk_buff *), |
| GFP_KERNEL); |
| if (!tx_q->tx_skbuff) |
| goto err_dma; |
| |
| if (priv->extend_desc) |
| size = sizeof(struct dma_extended_desc); |
| else if (tx_q->tbs & STMMAC_TBS_AVAIL) |
| size = sizeof(struct dma_edesc); |
| else |
| size = sizeof(struct dma_desc); |
| |
| size *= DMA_TX_SIZE; |
| |
| addr = dma_alloc_coherent(priv->device, size, |
| &tx_q->dma_tx_phy, GFP_KERNEL); |
| if (!addr) |
| goto err_dma; |
| |
| if (priv->extend_desc) |
| tx_q->dma_etx = addr; |
| else if (tx_q->tbs & STMMAC_TBS_AVAIL) |
| tx_q->dma_entx = addr; |
| else |
| tx_q->dma_tx = addr; |
| } |
| |
| return 0; |
| |
| err_dma: |
| free_dma_tx_desc_resources(priv); |
| return ret; |
| } |
| |
| /** |
| * alloc_dma_desc_resources - alloc TX/RX resources. |
| * @priv: private structure |
| * Description: according to which descriptor can be used (extend or basic) |
| * this function allocates the resources for TX and RX paths. In case of |
| * reception, for example, it pre-allocated the RX socket buffer in order to |
| * allow zero-copy mechanism. |
| */ |
| static int alloc_dma_desc_resources(struct stmmac_priv *priv) |
| { |
| /* RX Allocation */ |
| int ret = alloc_dma_rx_desc_resources(priv); |
| |
| if (ret) |
| return ret; |
| |
| ret = alloc_dma_tx_desc_resources(priv); |
| |
| return ret; |
| } |
| |
| /** |
| * free_dma_desc_resources - free dma desc resources |
| * @priv: private structure |
| */ |
| static void free_dma_desc_resources(struct stmmac_priv *priv) |
| { |
| /* Release the DMA RX socket buffers */ |
| free_dma_rx_desc_resources(priv); |
| |
| /* Release the DMA TX socket buffers */ |
| free_dma_tx_desc_resources(priv); |
| } |
| |
| /** |
| * stmmac_mac_enable_rx_queues - Enable MAC rx queues |
| * @priv: driver private structure |
| * Description: It is used for enabling the rx queues in the MAC |
| */ |
| static void stmmac_mac_enable_rx_queues(struct stmmac_priv *priv) |
| { |
| u32 rx_queues_count = priv->plat->rx_queues_to_use; |
| int queue; |
| u8 mode; |
| |
| for (queue = 0; queue < rx_queues_count; queue++) { |
| mode = priv->plat->rx_queues_cfg[queue].mode_to_use; |
| stmmac_rx_queue_enable(priv, priv->hw, mode, queue); |
| } |
| } |
| |
| /** |
| * stmmac_start_rx_dma - start RX DMA channel |
| * @priv: driver private structure |
| * @chan: RX channel index |
| * Description: |
| * This starts a RX DMA channel |
| */ |
| static void stmmac_start_rx_dma(struct stmmac_priv *priv, u32 chan) |
| { |
| netdev_dbg(priv->dev, "DMA RX processes started in channel %d\n", chan); |
| stmmac_start_rx(priv, priv->ioaddr, chan); |
| } |
| |
| /** |
| * stmmac_start_tx_dma - start TX DMA channel |
| * @priv: driver private structure |
| * @chan: TX channel index |
| * Description: |
| * This starts a TX DMA channel |
| */ |
| static void stmmac_start_tx_dma(struct stmmac_priv *priv, u32 chan) |
| { |
| netdev_dbg(priv->dev, "DMA TX processes started in channel %d\n", chan); |
| stmmac_start_tx(priv, priv->ioaddr, chan); |
| } |
| |
| /** |
| * stmmac_stop_rx_dma - stop RX DMA channel |
| * @priv: driver private structure |
| * @chan: RX channel index |
| * Description: |
| * This stops a RX DMA channel |
| */ |
| static void stmmac_stop_rx_dma(struct stmmac_priv *priv, u32 chan) |
| { |
| netdev_dbg(priv->dev, "DMA RX processes stopped in channel %d\n", chan); |
| stmmac_stop_rx(priv, priv->ioaddr, chan); |
| } |
| |
| /** |
| * stmmac_stop_tx_dma - stop TX DMA channel |
| * @priv: driver private structure |
| * @chan: TX channel index |
| * Description: |
| * This stops a TX DMA channel |
| */ |
| static void stmmac_stop_tx_dma(struct stmmac_priv *priv, u32 chan) |
| { |
| netdev_dbg(priv->dev, "DMA TX processes stopped in channel %d\n", chan); |
| stmmac_stop_tx(priv, priv->ioaddr, chan); |
| } |
| |
| /** |
| * stmmac_start_all_dma - start all RX and TX DMA channels |
| * @priv: driver private structure |
| * Description: |
| * This starts all the RX and TX DMA channels |
| */ |
| static void stmmac_start_all_dma(struct stmmac_priv *priv) |
| { |
| u32 rx_channels_count = priv->plat->rx_queues_to_use; |
| u32 tx_channels_count = priv->plat->tx_queues_to_use; |
| u32 chan = 0; |
| |
| for (chan = 0; chan < rx_channels_count; chan++) |
| stmmac_start_rx_dma(priv, chan); |
| |
| for (chan = 0; chan < tx_channels_count; chan++) |
| stmmac_start_tx_dma(priv, chan); |
| } |
| |
| /** |
| * stmmac_stop_all_dma - stop all RX and TX DMA channels |
| * @priv: driver private structure |
| * Description: |
| * This stops the RX and TX DMA channels |
| */ |
| static void stmmac_stop_all_dma(struct stmmac_priv *priv) |
| { |
| u32 rx_channels_count = priv->plat->rx_queues_to_use; |
| u32 tx_channels_count = priv->plat->tx_queues_to_use; |
| u32 chan = 0; |
| |
| for (chan = 0; chan < rx_channels_count; chan++) |
| stmmac_stop_rx_dma(priv, chan); |
| |
| for (chan = 0; chan < tx_channels_count; chan++) |
| stmmac_stop_tx_dma(priv, chan); |
| } |
| |
| /** |
| * stmmac_dma_operation_mode - HW DMA operation mode |
| * @priv: driver private structure |
| * Description: it is used for configuring the DMA operation mode register in |
| * order to program the tx/rx DMA thresholds or Store-And-Forward mode. |
| */ |
| static void stmmac_dma_operation_mode(struct stmmac_priv *priv) |
| { |
| u32 rx_channels_count = priv->plat->rx_queues_to_use; |
| u32 tx_channels_count = priv->plat->tx_queues_to_use; |
| int rxfifosz = priv->plat->rx_fifo_size; |
| int txfifosz = priv->plat->tx_fifo_size; |
| u32 txmode = 0; |
| u32 rxmode = 0; |
| u32 chan = 0; |
| u8 qmode = 0; |
| |
| if (rxfifosz == 0) |
| rxfifosz = priv->dma_cap.rx_fifo_size; |
| if (txfifosz == 0) |
| txfifosz = priv->dma_cap.tx_fifo_size; |
| |
| /* Adjust for real per queue fifo size */ |
| rxfifosz /= rx_channels_count; |
| txfifosz /= tx_channels_count; |
| |
| if (priv->plat->force_thresh_dma_mode) { |
| txmode = tc; |
| rxmode = tc; |
| } else if (priv->plat->force_sf_dma_mode || priv->plat->tx_coe) { |
| /* |
| * In case of GMAC, SF mode can be enabled |
| * to perform the TX COE in HW. This depends on: |
| * 1) TX COE if actually supported |
| * 2) There is no bugged Jumbo frame support |
| * that needs to not insert csum in the TDES. |
| */ |
| txmode = SF_DMA_MODE; |
| rxmode = SF_DMA_MODE; |
| priv->xstats.threshold = SF_DMA_MODE; |
| } else { |
| txmode = tc; |
| rxmode = SF_DMA_MODE; |
| } |
| |
| /* configure all channels */ |
| for (chan = 0; chan < rx_channels_count; chan++) { |
| qmode = priv->plat->rx_queues_cfg[chan].mode_to_use; |
| |
| stmmac_dma_rx_mode(priv, priv->ioaddr, rxmode, chan, |
| rxfifosz, qmode); |
| stmmac_set_dma_bfsize(priv, priv->ioaddr, priv->dma_buf_sz, |
| chan); |
| } |
| |
| for (chan = 0; chan < tx_channels_count; chan++) { |
| qmode = priv->plat->tx_queues_cfg[chan].mode_to_use; |
| |
| stmmac_dma_tx_mode(priv, priv->ioaddr, txmode, chan, |
| txfifosz, qmode); |
| } |
| } |
| |
| /** |
| * stmmac_tx_clean - to manage the transmission completion |
| * @priv: driver private structure |
| * @queue: TX queue index |
| * Description: it reclaims the transmit resources after transmission completes. |
| */ |
| static int stmmac_tx_clean(struct stmmac_priv *priv, int budget, u32 queue) |
| { |
| struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; |
| unsigned int bytes_compl = 0, pkts_compl = 0; |
| unsigned int entry, count = 0; |
| |
| __netif_tx_lock_bh(netdev_get_tx_queue(priv->dev, queue)); |
| |
| priv->xstats.tx_clean++; |
| |
| entry = tx_q->dirty_tx; |
| while ((entry != tx_q->cur_tx) && (count < budget)) { |
| struct sk_buff *skb = tx_q->tx_skbuff[entry]; |
| struct dma_desc *p; |
| int status; |
| |
| if (priv->extend_desc) |
| p = (struct dma_desc *)(tx_q->dma_etx + entry); |
| else if (tx_q->tbs & STMMAC_TBS_AVAIL) |
| p = &tx_q->dma_entx[entry].basic; |
| else |
| p = tx_q->dma_tx + entry; |
| |
| status = stmmac_tx_status(priv, &priv->dev->stats, |
| &priv->xstats, p, priv->ioaddr); |
| /* Check if the descriptor is owned by the DMA */ |
| if (unlikely(status & tx_dma_own)) |
| break; |
| |
| count++; |
| |
| /* Make sure descriptor fields are read after reading |
| * the own bit. |
| */ |
| dma_rmb(); |
| |
| /* Just consider the last segment and ...*/ |
| if (likely(!(status & tx_not_ls))) { |
| /* ... verify the status error condition */ |
| if (unlikely(status & tx_err)) { |
| priv->dev->stats.tx_errors++; |
| } else { |
| priv->dev->stats.tx_packets++; |
| priv->xstats.tx_pkt_n++; |
| } |
| stmmac_get_tx_hwtstamp(priv, p, skb); |
| } |
| |
| if (likely(tx_q->tx_skbuff_dma[entry].buf)) { |
| if (tx_q->tx_skbuff_dma[entry].map_as_page) |
| dma_unmap_page(priv->device, |
| tx_q->tx_skbuff_dma[entry].buf, |
| tx_q->tx_skbuff_dma[entry].len, |
| DMA_TO_DEVICE); |
| else |
| dma_unmap_single(priv->device, |
| tx_q->tx_skbuff_dma[entry].buf, |
| tx_q->tx_skbuff_dma[entry].len, |
| DMA_TO_DEVICE); |
| tx_q->tx_skbuff_dma[entry].buf = 0; |
| tx_q->tx_skbuff_dma[entry].len = 0; |
| tx_q->tx_skbuff_dma[entry].map_as_page = false; |
| } |
| |
| stmmac_clean_desc3(priv, tx_q, p); |
| |
| tx_q->tx_skbuff_dma[entry].last_segment = false; |
| tx_q->tx_skbuff_dma[entry].is_jumbo = false; |
| |
| if (likely(skb != NULL)) { |
| pkts_compl++; |
| bytes_compl += skb->len; |
| dev_consume_skb_any(skb); |
| tx_q->tx_skbuff[entry] = NULL; |
| } |
| |
| stmmac_release_tx_desc(priv, p, priv->mode); |
| |
| entry = STMMAC_GET_ENTRY(entry, DMA_TX_SIZE); |
| } |
| tx_q->dirty_tx = entry; |
| |
| netdev_tx_completed_queue(netdev_get_tx_queue(priv->dev, queue), |
| pkts_compl, bytes_compl); |
| |
| if (unlikely(netif_tx_queue_stopped(netdev_get_tx_queue(priv->dev, |
| queue))) && |
| stmmac_tx_avail(priv, queue) > STMMAC_TX_THRESH) { |
| |
| netif_dbg(priv, tx_done, priv->dev, |
| "%s: restart transmit\n", __func__); |
| netif_tx_wake_queue(netdev_get_tx_queue(priv->dev, queue)); |
| } |
| |
| if ((priv->eee_enabled) && (!priv->tx_path_in_lpi_mode)) { |
| stmmac_enable_eee_mode(priv); |
| mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(eee_timer)); |
| } |
| |
| /* We still have pending packets, let's call for a new scheduling */ |
| if (tx_q->dirty_tx != tx_q->cur_tx) |
| mod_timer(&tx_q->txtimer, STMMAC_COAL_TIMER(priv->tx_coal_timer)); |
| |
| __netif_tx_unlock_bh(netdev_get_tx_queue(priv->dev, queue)); |
| |
| return count; |
| } |
| |
| /** |
| * stmmac_tx_err - to manage the tx error |
| * @priv: driver private structure |
| * @chan: channel index |
| * Description: it cleans the descriptors and restarts the transmission |
| * in case of transmission errors. |
| */ |
| static void stmmac_tx_err(struct stmmac_priv *priv, u32 chan) |
| { |
| struct stmmac_tx_queue *tx_q = &priv->tx_queue[chan]; |
| |
| netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, chan)); |
| |
| stmmac_stop_tx_dma(priv, chan); |
| dma_free_tx_skbufs(priv, chan); |
| stmmac_clear_tx_descriptors(priv, chan); |
| tx_q->dirty_tx = 0; |
| tx_q->cur_tx = 0; |
| tx_q->mss = 0; |
| netdev_tx_reset_queue(netdev_get_tx_queue(priv->dev, chan)); |
| stmmac_init_tx_chan(priv, priv->ioaddr, priv->plat->dma_cfg, |
| tx_q->dma_tx_phy, chan); |
| stmmac_start_tx_dma(priv, chan); |
| |
| priv->dev->stats.tx_errors++; |
| netif_tx_wake_queue(netdev_get_tx_queue(priv->dev, chan)); |
| } |
| |
| /** |
| * stmmac_set_dma_operation_mode - Set DMA operation mode by channel |
| * @priv: driver private structure |
| * @txmode: TX operating mode |
| * @rxmode: RX operating mode |
| * @chan: channel index |
| * Description: it is used for configuring of the DMA operation mode in |
| * runtime in order to program the tx/rx DMA thresholds or Store-And-Forward |
| * mode. |
| */ |
| static void stmmac_set_dma_operation_mode(struct stmmac_priv *priv, u32 txmode, |
| u32 rxmode, u32 chan) |
| { |
| u8 rxqmode = priv->plat->rx_queues_cfg[chan].mode_to_use; |
| u8 txqmode = priv->plat->tx_queues_cfg[chan].mode_to_use; |
| u32 rx_channels_count = priv->plat->rx_queues_to_use; |
| u32 tx_channels_count = priv->plat->tx_queues_to_use; |
| int rxfifosz = priv->plat->rx_fifo_size; |
| int txfifosz = priv->plat->tx_fifo_size; |
| |
| if (rxfifosz == 0) |
| rxfifosz = priv->dma_cap.rx_fifo_size; |
| if (txfifosz == 0) |
| txfifosz = priv->dma_cap.tx_fifo_size; |
| |
| /* Adjust for real per queue fifo size */ |
| rxfifosz /= rx_channels_count; |
| txfifosz /= tx_channels_count; |
| |
| stmmac_dma_rx_mode(priv, priv->ioaddr, rxmode, chan, rxfifosz, rxqmode); |
| stmmac_dma_tx_mode(priv, priv->ioaddr, txmode, chan, txfifosz, txqmode); |
| } |
| |
| static bool stmmac_safety_feat_interrupt(struct stmmac_priv *priv) |
| { |
| int ret; |
| |
| ret = stmmac_safety_feat_irq_status(priv, priv->dev, |
| priv->ioaddr, priv->dma_cap.asp, &priv->sstats); |
| if (ret && (ret != -EINVAL)) { |
| stmmac_global_err(priv); |
| return true; |
| } |
| |
| return false; |
| } |
| |
| static int stmmac_napi_check(struct stmmac_priv *priv, u32 chan) |
| { |
| int status = stmmac_dma_interrupt_status(priv, priv->ioaddr, |
| &priv->xstats, chan); |
| struct stmmac_channel *ch = &priv->channel[chan]; |
| unsigned long flags; |
| |
| if ((status & handle_rx) && (chan < priv->plat->rx_queues_to_use)) { |
| if (napi_schedule_prep(&ch->rx_napi)) { |
| spin_lock_irqsave(&ch->lock, flags); |
| stmmac_disable_dma_irq(priv, priv->ioaddr, chan, 1, 0); |
| spin_unlock_irqrestore(&ch->lock, flags); |
| __napi_schedule_irqoff(&ch->rx_napi); |
| } |
| } |
| |
| if ((status & handle_tx) && (chan < priv->plat->tx_queues_to_use)) { |
| if (napi_schedule_prep(&ch->tx_napi)) { |
| spin_lock_irqsave(&ch->lock, flags); |
| stmmac_disable_dma_irq(priv, priv->ioaddr, chan, 0, 1); |
| spin_unlock_irqrestore(&ch->lock, flags); |
| __napi_schedule_irqoff(&ch->tx_napi); |
| } |
| } |
| |
| return status; |
| } |
| |
| /** |
| * stmmac_dma_interrupt - DMA ISR |
| * @priv: driver private structure |
| * Description: this is the DMA ISR. It is called by the main ISR. |
| * It calls the dwmac dma routine and schedule poll method in case of some |
| * work can be done. |
| */ |
| static void stmmac_dma_interrupt(struct stmmac_priv *priv) |
| { |
| u32 tx_channel_count = priv->plat->tx_queues_to_use; |
| u32 rx_channel_count = priv->plat->rx_queues_to_use; |
| u32 channels_to_check = tx_channel_count > rx_channel_count ? |
| tx_channel_count : rx_channel_count; |
| u32 chan; |
| int status[max_t(u32, MTL_MAX_TX_QUEUES, MTL_MAX_RX_QUEUES)]; |
| |
| /* Make sure we never check beyond our status buffer. */ |
| if (WARN_ON_ONCE(channels_to_check > ARRAY_SIZE(status))) |
| channels_to_check = ARRAY_SIZE(status); |
| |
| for (chan = 0; chan < channels_to_check; chan++) |
| status[chan] = stmmac_napi_check(priv, chan); |
| |
| for (chan = 0; chan < tx_channel_count; chan++) { |
| if (unlikely(status[chan] & tx_hard_error_bump_tc)) { |
| /* Try to bump up the dma threshold on this failure */ |
| if (unlikely(priv->xstats.threshold != SF_DMA_MODE) && |
| (tc <= 256)) { |
| tc += 64; |
| if (priv->plat->force_thresh_dma_mode) |
| stmmac_set_dma_operation_mode(priv, |
| tc, |
| tc, |
| chan); |
| else |
| stmmac_set_dma_operation_mode(priv, |
| tc, |
| SF_DMA_MODE, |
| chan); |
| priv->xstats.threshold = tc; |
| } |
| } else if (unlikely(status[chan] == tx_hard_error)) { |
| stmmac_tx_err(priv, chan); |
| } |
| } |
| } |
| |
| /** |
| * stmmac_mmc_setup: setup the Mac Management Counters (MMC) |
| * @priv: driver private structure |
| * Description: this masks the MMC irq, in fact, the counters are managed in SW. |
| */ |
| static void stmmac_mmc_setup(struct stmmac_priv *priv) |
| { |
| unsigned int mode = MMC_CNTRL_RESET_ON_READ | MMC_CNTRL_COUNTER_RESET | |
| MMC_CNTRL_PRESET | MMC_CNTRL_FULL_HALF_PRESET; |
| |
| stmmac_mmc_intr_all_mask(priv, priv->mmcaddr); |
| |
| if (priv->dma_cap.rmon) { |
| stmmac_mmc_ctrl(priv, priv->mmcaddr, mode); |
| memset(&priv->mmc, 0, sizeof(struct stmmac_counters)); |
| } else |
| netdev_info(priv->dev, "No MAC Management Counters available\n"); |
| } |
| |
| /** |
| * stmmac_get_hw_features - get MAC capabilities from the HW cap. register. |
| * @priv: driver private structure |
| * Description: |
| * new GMAC chip generations have a new register to indicate the |
| * presence of the optional feature/functions. |
| * This can be also used to override the value passed through the |
| * platform and necessary for old MAC10/100 and GMAC chips. |
| */ |
| static int stmmac_get_hw_features(struct stmmac_priv *priv) |
| { |
| return stmmac_get_hw_feature(priv, priv->ioaddr, &priv->dma_cap) == 0; |
| } |
| |
| /** |
| * stmmac_check_ether_addr - check if the MAC addr is valid |
| * @priv: driver private structure |
| * Description: |
| * it is to verify if the MAC address is valid, in case of failures it |
| * generates a random MAC address |
| */ |
| static void stmmac_check_ether_addr(struct stmmac_priv *priv) |
| { |
| if (!is_valid_ether_addr(priv->dev->dev_addr)) { |
| stmmac_get_umac_addr(priv, priv->hw, priv->dev->dev_addr, 0); |
| if (!is_valid_ether_addr(priv->dev->dev_addr)) |
| eth_hw_addr_random(priv->dev); |
| dev_info(priv->device, "device MAC address %pM\n", |
| priv->dev->dev_addr); |
| } |
| } |
| |
| /** |
| * stmmac_init_dma_engine - DMA init. |
| * @priv: driver private structure |
| * Description: |
| * It inits the DMA invoking the specific MAC/GMAC callback. |
| * Some DMA parameters can be passed from the platform; |
| * in case of these are not passed a default is kept for the MAC or GMAC. |
| */ |
| static int stmmac_init_dma_engine(struct stmmac_priv *priv) |
| { |
| u32 rx_channels_count = priv->plat->rx_queues_to_use; |
| u32 tx_channels_count = priv->plat->tx_queues_to_use; |
| u32 dma_csr_ch = max(rx_channels_count, tx_channels_count); |
| struct stmmac_rx_queue *rx_q; |
| struct stmmac_tx_queue *tx_q; |
| u32 chan = 0; |
| int atds = 0; |
| int ret = 0; |
| |
| if (!priv->plat->dma_cfg || !priv->plat->dma_cfg->pbl) { |
| dev_err(priv->device, "Invalid DMA configuration\n"); |
| return -EINVAL; |
| } |
| |
| if (priv->extend_desc && (priv->mode == STMMAC_RING_MODE)) |
| atds = 1; |
| |
| ret = stmmac_reset(priv, priv->ioaddr); |
| if (ret) { |
| dev_err(priv->device, "Failed to reset the dma\n"); |
| return ret; |
| } |
| |
| /* DMA Configuration */ |
| stmmac_dma_init(priv, priv->ioaddr, priv->plat->dma_cfg, atds); |
| |
| if (priv->plat->axi) |
| stmmac_axi(priv, priv->ioaddr, priv->plat->axi); |
| |
| /* DMA CSR Channel configuration */ |
| for (chan = 0; chan < dma_csr_ch; chan++) |
| stmmac_init_chan(priv, priv->ioaddr, priv->plat->dma_cfg, chan); |
| |
| /* DMA RX Channel Configuration */ |
| for (chan = 0; chan < rx_channels_count; chan++) { |
| rx_q = &priv->rx_queue[chan]; |
| |
| stmmac_init_rx_chan(priv, priv->ioaddr, priv->plat->dma_cfg, |
| rx_q->dma_rx_phy, chan); |
| |
| rx_q->rx_tail_addr = rx_q->dma_rx_phy + |
| (DMA_RX_SIZE * sizeof(struct dma_desc)); |
| stmmac_set_rx_tail_ptr(priv, priv->ioaddr, |
| rx_q->rx_tail_addr, chan); |
| } |
| |
| /* DMA TX Channel Configuration */ |
| for (chan = 0; chan < tx_channels_count; chan++) { |
| tx_q = &priv->tx_queue[chan]; |
| |
| stmmac_init_tx_chan(priv, priv->ioaddr, priv->plat->dma_cfg, |
| tx_q->dma_tx_phy, chan); |
| |
| tx_q->tx_tail_addr = tx_q->dma_tx_phy; |
| stmmac_set_tx_tail_ptr(priv, priv->ioaddr, |
| tx_q->tx_tail_addr, chan); |
| } |
| |
| return ret; |
| } |
| |
| static void stmmac_tx_timer_arm(struct stmmac_priv *priv, u32 queue) |
| { |
| struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; |
| |
| mod_timer(&tx_q->txtimer, STMMAC_COAL_TIMER(priv->tx_coal_timer)); |
| } |
| |
| /** |
| * stmmac_tx_timer - mitigation sw timer for tx. |
| * @data: data pointer |
| * Description: |
| * This is the timer handler to directly invoke the stmmac_tx_clean. |
| */ |
| static void stmmac_tx_timer(struct timer_list *t) |
| { |
| struct stmmac_tx_queue *tx_q = from_timer(tx_q, t, txtimer); |
| struct stmmac_priv *priv = tx_q->priv_data; |
| struct stmmac_channel *ch; |
| |
| ch = &priv->channel[tx_q->queue_index]; |
| |
| if (likely(napi_schedule_prep(&ch->tx_napi))) { |
| unsigned long flags; |
| |
| spin_lock_irqsave(&ch->lock, flags); |
| stmmac_disable_dma_irq(priv, priv->ioaddr, ch->index, 0, 1); |
| spin_unlock_irqrestore(&ch->lock, flags); |
| __napi_schedule(&ch->tx_napi); |
| } |
| } |
| |
| /** |
| * stmmac_init_coalesce - init mitigation options. |
| * @priv: driver private structure |
| * Description: |
| * This inits the coalesce parameters: i.e. timer rate, |
| * timer handler and default threshold used for enabling the |
| * interrupt on completion bit. |
| */ |
| static void stmmac_init_coalesce(struct stmmac_priv *priv) |
| { |
| u32 tx_channel_count = priv->plat->tx_queues_to_use; |
| u32 chan; |
| |
| priv->tx_coal_frames = STMMAC_TX_FRAMES; |
| priv->tx_coal_timer = STMMAC_COAL_TX_TIMER; |
| priv->rx_coal_frames = STMMAC_RX_FRAMES; |
| |
| for (chan = 0; chan < tx_channel_count; chan++) { |
| struct stmmac_tx_queue *tx_q = &priv->tx_queue[chan]; |
| |
| timer_setup(&tx_q->txtimer, stmmac_tx_timer, 0); |
| } |
| } |
| |
| static void stmmac_set_rings_length(struct stmmac_priv *priv) |
| { |
| u32 rx_channels_count = priv->plat->rx_queues_to_use; |
| u32 tx_channels_count = priv->plat->tx_queues_to_use; |
| u32 chan; |
| |
| /* set TX ring length */ |
| for (chan = 0; chan < tx_channels_count; chan++) |
| stmmac_set_tx_ring_len(priv, priv->ioaddr, |
| (DMA_TX_SIZE - 1), chan); |
| |
| /* set RX ring length */ |
| for (chan = 0; chan < rx_channels_count; chan++) |
| stmmac_set_rx_ring_len(priv, priv->ioaddr, |
| (DMA_RX_SIZE - 1), chan); |
| } |
| |
| /** |
| * stmmac_set_tx_queue_weight - Set TX queue weight |
| * @priv: driver private structure |
| * Description: It is used for setting TX queues weight |
| */ |
| static void stmmac_set_tx_queue_weight(struct stmmac_priv *priv) |
| { |
| u32 tx_queues_count = priv->plat->tx_queues_to_use; |
| u32 weight; |
| u32 queue; |
| |
| for (queue = 0; queue < tx_queues_count; queue++) { |
| weight = priv->plat->tx_queues_cfg[queue].weight; |
| stmmac_set_mtl_tx_queue_weight(priv, priv->hw, weight, queue); |
| } |
| } |
| |
| /** |
| * stmmac_configure_cbs - Configure CBS in TX queue |
| * @priv: driver private structure |
| * Description: It is used for configuring CBS in AVB TX queues |
| */ |
| static void stmmac_configure_cbs(struct stmmac_priv *priv) |
| { |
| u32 tx_queues_count = priv->plat->tx_queues_to_use; |
| u32 mode_to_use; |
| u32 queue; |
| |
| /* queue 0 is reserved for legacy traffic */ |
| for (queue = 1; queue < tx_queues_count; queue++) { |
| mode_to_use = priv->plat->tx_queues_cfg[queue].mode_to_use; |
| if (mode_to_use == MTL_QUEUE_DCB) |
| continue; |
| |
| stmmac_config_cbs(priv, priv->hw, |
| priv->plat->tx_queues_cfg[queue].send_slope, |
| priv->plat->tx_queues_cfg[queue].idle_slope, |
| priv->plat->tx_queues_cfg[queue].high_credit, |
| priv->plat->tx_queues_cfg[queue].low_credit, |
| queue); |
| } |
| } |
| |
| /** |
| * stmmac_rx_queue_dma_chan_map - Map RX queue to RX dma channel |
| * @priv: driver private structure |
| * Description: It is used for mapping RX queues to RX dma channels |
| */ |
| static void stmmac_rx_queue_dma_chan_map(struct stmmac_priv *priv) |
| { |
| u32 rx_queues_count = priv->plat->rx_queues_to_use; |
| u32 queue; |
| u32 chan; |
| |
| for (queue = 0; queue < rx_queues_count; queue++) { |
| chan = priv->plat->rx_queues_cfg[queue].chan; |
| stmmac_map_mtl_to_dma(priv, priv->hw, queue, chan); |
| } |
| } |
| |
| /** |
| * stmmac_mac_config_rx_queues_prio - Configure RX Queue priority |
| * @priv: driver private structure |
| * Description: It is used for configuring the RX Queue Priority |
| */ |
| static void stmmac_mac_config_rx_queues_prio(struct stmmac_priv *priv) |
| { |
| u32 rx_queues_count = priv->plat->rx_queues_to_use; |
| u32 queue; |
| u32 prio; |
| |
| for (queue = 0; queue < rx_queues_count; queue++) { |
| if (!priv->plat->rx_queues_cfg[queue].use_prio) |
| continue; |
| |
| prio = priv->plat->rx_queues_cfg[queue].prio; |
| stmmac_rx_queue_prio(priv, priv->hw, prio, queue); |
| } |
| } |
| |
| /** |
| * stmmac_mac_config_tx_queues_prio - Configure TX Queue priority |
| * @priv: driver private structure |
| * Description: It is used for configuring the TX Queue Priority |
| */ |
| static void stmmac_mac_config_tx_queues_prio(struct stmmac_priv *priv) |
| { |
| u32 tx_queues_count = priv->plat->tx_queues_to_use; |
| u32 queue; |
| u32 prio; |
| |
| for (queue = 0; queue < tx_queues_count; queue++) { |
| if (!priv->plat->tx_queues_cfg[queue].use_prio) |
| continue; |
| |
| prio = priv->plat->tx_queues_cfg[queue].prio; |
| stmmac_tx_queue_prio(priv, priv->hw, prio, queue); |
| } |
| } |
| |
| /** |
| * stmmac_mac_config_rx_queues_routing - Configure RX Queue Routing |
| * @priv: driver private structure |
| * Description: It is used for configuring the RX queue routing |
| */ |
| static void stmmac_mac_config_rx_queues_routing(struct stmmac_priv *priv) |
| { |
| u32 rx_queues_count = priv->plat->rx_queues_to_use; |
| u32 queue; |
| u8 packet; |
| |
| for (queue = 0; queue < rx_queues_count; queue++) { |
| /* no specific packet type routing specified for the queue */ |
| if (priv->plat->rx_queues_cfg[queue].pkt_route == 0x0) |
| continue; |
| |
| packet = priv->plat->rx_queues_cfg[queue].pkt_route; |
| stmmac_rx_queue_routing(priv, priv->hw, packet, queue); |
| } |
| } |
| |
| static void stmmac_mac_config_rss(struct stmmac_priv *priv) |
| { |
| if (!priv->dma_cap.rssen || !priv->plat->rss_en) { |
| priv->rss.enable = false; |
| return; |
| } |
| |
| if (priv->dev->features & NETIF_F_RXHASH) |
| priv->rss.enable = true; |
| else |
| priv->rss.enable = false; |
| |
| stmmac_rss_configure(priv, priv->hw, &priv->rss, |
| priv->plat->rx_queues_to_use); |
| } |
| |
| /** |
| * stmmac_mtl_configuration - Configure MTL |
| * @priv: driver private structure |
| * Description: It is used for configurring MTL |
| */ |
| static void stmmac_mtl_configuration(struct stmmac_priv *priv) |
| { |
| u32 rx_queues_count = priv->plat->rx_queues_to_use; |
| u32 tx_queues_count = priv->plat->tx_queues_to_use; |
| |
| if (tx_queues_count > 1) |
| stmmac_set_tx_queue_weight(priv); |
| |
| /* Configure MTL RX algorithms */ |
| if (rx_queues_count > 1) |
| stmmac_prog_mtl_rx_algorithms(priv, priv->hw, |
| priv->plat->rx_sched_algorithm); |
| |
| /* Configure MTL TX algorithms */ |
| if (tx_queues_count > 1) |
| stmmac_prog_mtl_tx_algorithms(priv, priv->hw, |
| priv->plat->tx_sched_algorithm); |
| |
| /* Configure CBS in AVB TX queues */ |
| if (tx_queues_count > 1) |
| stmmac_configure_cbs(priv); |
| |
| /* Map RX MTL to DMA channels */ |
| stmmac_rx_queue_dma_chan_map(priv); |
| |
| /* Enable MAC RX Queues */ |
| stmmac_mac_enable_rx_queues(priv); |
| |
| /* Set RX priorities */ |
| if (rx_queues_count > 1) |
| stmmac_mac_config_rx_queues_prio(priv); |
| |
| /* Set TX priorities */ |
| if (tx_queues_count > 1) |
| stmmac_mac_config_tx_queues_prio(priv); |
| |
| /* Set RX routing */ |
| if (rx_queues_count > 1) |
| stmmac_mac_config_rx_queues_routing(priv); |
| |
| /* Receive Side Scaling */ |
| if (rx_queues_count > 1) |
| stmmac_mac_config_rss(priv); |
| } |
| |
| static void stmmac_safety_feat_configuration(struct stmmac_priv *priv) |
| { |
| if (priv->dma_cap.asp) { |
| netdev_info(priv->dev, "Enabling Safety Features\n"); |
| stmmac_safety_feat_config(priv, priv->ioaddr, priv->dma_cap.asp); |
| } else { |
| netdev_info(priv->dev, "No Safety Features support found\n"); |
| } |
| } |
| |
| /** |
| * stmmac_hw_setup - setup mac in a usable state. |
| * @dev : pointer to the device structure. |
| * Description: |
| * this is the main function to setup the HW in a usable state because the |
| * dma engine is reset, the core registers are configured (e.g. AXI, |
| * Checksum features, timers). The DMA is ready to start receiving and |
| * transmitting. |
| * Return value: |
| * 0 on success and an appropriate (-)ve integer as defined in errno.h |
| * file on failure. |
| */ |
| static int stmmac_hw_setup(struct net_device *dev, bool init_ptp) |
| { |
| struct stmmac_priv *priv = netdev_priv(dev); |
| u32 rx_cnt = priv->plat->rx_queues_to_use; |
| u32 tx_cnt = priv->plat->tx_queues_to_use; |
| u32 chan; |
| int ret; |
| |
| /* DMA initialization and SW reset */ |
| ret = stmmac_init_dma_engine(priv); |
| if (ret < 0) { |
| netdev_err(priv->dev, "%s: DMA engine initialization failed\n", |
| __func__); |
| return ret; |
| } |
| |
| /* Copy the MAC addr into the HW */ |
| stmmac_set_umac_addr(priv, priv->hw, dev->dev_addr, 0); |
| |
| /* PS and related bits will be programmed according to the speed */ |
| if (priv->hw->pcs) { |
| int speed = priv->plat->mac_port_sel_speed; |
| |
| if ((speed == SPEED_10) || (speed == SPEED_100) || |
| (speed == SPEED_1000)) { |
| priv->hw->ps = speed; |
| } else { |
| dev_warn(priv->device, "invalid port speed\n"); |
| priv->hw->ps = 0; |
| } |
| } |
| |
| /* Initialize the MAC Core */ |
| stmmac_core_init(priv, priv->hw, dev); |
| |
| /* Initialize MTL*/ |
| stmmac_mtl_configuration(priv); |
| |
| /* Initialize Safety Features */ |
| stmmac_safety_feat_configuration(priv); |
| |
| ret = stmmac_rx_ipc(priv, priv->hw); |
| if (!ret) { |
| netdev_warn(priv->dev, "RX IPC Checksum Offload disabled\n"); |
| priv->plat->rx_coe = STMMAC_RX_COE_NONE; |
| priv->hw->rx_csum = 0; |
| } |
| |
| /* Enable the MAC Rx/Tx */ |
| stmmac_mac_set(priv, priv->ioaddr, true); |
| |
| /* Set the HW DMA mode and the COE */ |
| stmmac_dma_operation_mode(priv); |
| |
| stmmac_mmc_setup(priv); |
| |
| if (init_ptp) { |
| ret = clk_prepare_enable(priv->plat->clk_ptp_ref); |
| if (ret < 0) |
| netdev_warn(priv->dev, "failed to enable PTP reference clock: %d\n", ret); |
| |
| ret = stmmac_init_ptp(priv); |
| if (ret == -EOPNOTSUPP) |
| netdev_warn(priv->dev, "PTP not supported by HW\n"); |
| else if (ret) |
| netdev_warn(priv->dev, "PTP init failed\n"); |
| } |
| |
| priv->tx_lpi_timer = STMMAC_DEFAULT_TWT_LS; |
| |
| if (priv->use_riwt) { |
| if (!priv->rx_riwt) |
| priv->rx_riwt = DEF_DMA_RIWT; |
| |
| ret = stmmac_rx_watchdog(priv, priv->ioaddr, priv->rx_riwt, rx_cnt); |
| } |
| |
| if (priv->hw->pcs) |
| stmmac_pcs_ctrl_ane(priv, priv->ioaddr, 1, priv->hw->ps, 0); |
| |
| /* set TX and RX rings length */ |
| stmmac_set_rings_length(priv); |
| |
| /* Enable TSO */ |
| if (priv->tso) { |
| for (chan = 0; chan < tx_cnt; chan++) |
| stmmac_enable_tso(priv, priv->ioaddr, 1, chan); |
| } |
| |
| /* Enable Split Header */ |
| if (priv->sph && priv->hw->rx_csum) { |
| for (chan = 0; chan < rx_cnt; chan++) |
| stmmac_enable_sph(priv, priv->ioaddr, 1, chan); |
| } |
| |
| /* VLAN Tag Insertion */ |
| if (priv->dma_cap.vlins) |
| stmmac_enable_vlan(priv, priv->hw, STMMAC_VLAN_INSERT); |
| |
| /* TBS */ |
| for (chan = 0; chan < tx_cnt; chan++) { |
| struct stmmac_tx_queue *tx_q = &priv->tx_queue[chan]; |
| int enable = tx_q->tbs & STMMAC_TBS_AVAIL; |
| |
| stmmac_enable_tbs(priv, priv->ioaddr, enable, chan); |
| } |
| |
| /* Start the ball rolling... */ |
| stmmac_start_all_dma(priv); |
| |
| return 0; |
| } |
| |
| static void stmmac_hw_teardown(struct net_device *dev) |
| { |
| struct stmmac_priv *priv = netdev_priv(dev); |
| |
| clk_disable_unprepare(priv->plat->clk_ptp_ref); |
| } |
| |
| /** |
| * stmmac_open - open entry point of the driver |
| * @dev : pointer to the device structure. |
| * Description: |
| * This function is the open entry point of the driver. |
| * Return value: |
| * 0 on success and an appropriate (-)ve integer as defined in errno.h |
| * file on failure. |
| */ |
| static int stmmac_open(struct net_device *dev) |
| { |
| struct stmmac_priv *priv = netdev_priv(dev); |
| int bfsize = 0; |
| u32 chan; |
| int ret; |
| |
| if (priv->hw->pcs != STMMAC_PCS_TBI && |
| priv->hw->pcs != STMMAC_PCS_RTBI) { |
| ret = stmmac_init_phy(dev); |
| if (ret) { |
| netdev_err(priv->dev, |
| "%s: Cannot attach to PHY (error: %d)\n", |
| __func__, ret); |
| return ret; |
| } |
| } |
| |
| /* Extra statistics */ |
| memset(&priv->xstats, 0, sizeof(struct stmmac_extra_stats)); |
| priv->xstats.threshold = tc; |
| |
| bfsize = stmmac_set_16kib_bfsize(priv, dev->mtu); |
| if (bfsize < 0) |
| bfsize = 0; |
| |
| if (bfsize < BUF_SIZE_16KiB) |
| bfsize = stmmac_set_bfsize(dev->mtu, priv->dma_buf_sz); |
| |
| priv->dma_buf_sz = bfsize; |
| buf_sz = bfsize; |
| |
| priv->rx_copybreak = STMMAC_RX_COPYBREAK; |
| |
| /* Earlier check for TBS */ |
| for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++) { |
| struct stmmac_tx_queue *tx_q = &priv->tx_queue[chan]; |
| int tbs_en = priv->plat->tx_queues_cfg[chan].tbs_en; |
| |
| tx_q->tbs |= tbs_en ? STMMAC_TBS_AVAIL : 0; |
| if (stmmac_enable_tbs(priv, priv->ioaddr, tbs_en, chan)) |
| tx_q->tbs &= ~STMMAC_TBS_AVAIL; |
| } |
| |
| ret = alloc_dma_desc_resources(priv); |
| if (ret < 0) { |
| netdev_err(priv->dev, "%s: DMA descriptors allocation failed\n", |
| __func__); |
| goto dma_desc_error; |
| } |
| |
| ret = init_dma_desc_rings(dev, GFP_KERNEL); |
| if (ret < 0) { |
| netdev_err(priv->dev, "%s: DMA descriptors initialization failed\n", |
| __func__); |
| goto init_error; |
| } |
| |
| ret = stmmac_hw_setup(dev, true); |
| if (ret < 0) { |
| netdev_err(priv->dev, "%s: Hw setup failed\n", __func__); |
| goto init_error; |
| } |
| |
| stmmac_init_coalesce(priv); |
| |
| phylink_start(priv->phylink); |
| |
| /* Request the IRQ lines */ |
| ret = request_irq(dev->irq, stmmac_interrupt, |
| IRQF_SHARED, dev->name, dev); |
| if (unlikely(ret < 0)) { |
| netdev_err(priv->dev, |
| "%s: ERROR: allocating the IRQ %d (error: %d)\n", |
| __func__, dev->irq, ret); |
| goto irq_error; |
| } |
| |
| /* Request the Wake IRQ in case of another line is used for WoL */ |
| if (priv->wol_irq != dev->irq) { |
| ret = request_irq(priv->wol_irq, stmmac_interrupt, |
| IRQF_SHARED, dev->name, dev); |
| if (unlikely(ret < 0)) { |
| netdev_err(priv->dev, |
| "%s: ERROR: allocating the WoL IRQ %d (%d)\n", |
| __func__, priv->wol_irq, ret); |
| goto wolirq_error; |
| } |
| } |
| |
| /* Request the IRQ lines */ |
| if (priv-><
|