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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
$id: ",rzg2l-cpg.yaml#"
$schema: ""
title: Renesas RZ/G2L Clock Pulse Generator / Module Standby Mode
- Geert Uytterhoeven <>
description: |
On Renesas RZ/G2L SoC, the CPG (Clock Pulse Generator) and Module
Standby Mode share the same register block.
They provide the following functionalities:
- The CPG block generates various core clocks,
- The Module Standby Mode block provides two functions:
1. Module Standby, providing a Clock Domain to control the clock supply
to individual SoC devices,
2. Reset Control, to perform a software reset of individual SoC devices.
const: renesas,r9a07g044-cpg # RZ/G2{L,LC}
maxItems: 1
maxItems: 1
Clock source to CPG can be either from external clock input (EXCLK) or
crystal oscillator (XIN/XOUT).
const: extal
description: |
- For CPG core clocks, the two clock specifier cells must be "CPG_CORE"
and a core clock reference, as defined in
- For module clocks, the two clock specifier cells must be "CPG_MOD" and
a module number, as defined in the <dt-bindings/clock/r9a07g044-cpg.h>.
const: 2
SoC devices that are part of the CPG/Module Standby Mode Clock Domain and
can be power-managed through Module Standby should refer to the CPG device
node in their "power-domains" property, as documented by the generic PM
Domain bindings in Documentation/devicetree/bindings/power/power-domain.yaml.
const: 0
The single reset specifier cell must be the module number, as defined in
the <dt-bindings/clock/r9a07g044-cpg.h>.
const: 1
- compatible
- reg
- clocks
- clock-names
- '#clock-cells'
- '#power-domain-cells'
- '#reset-cells'
additionalProperties: false
- |
cpg: clock-controller@11010000 {
compatible = "renesas,r9a07g044-cpg";
reg = <0x11010000 0x10000>;
clocks = <&extal_clk>;
clock-names = "extal";
#clock-cells = <2>;
#power-domain-cells = <0>;
#reset-cells = <1>;