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# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
title: ARM architected timer
- Marc Zyngier <>
- Mark Rutland <>
description: |+
ARM cores may have a per-core architected timer, which provides per-cpu timers,
or a memory mapped architected timer, which provides up to 8 frames with a
physical and optional virtual timer per frame.
The per-core architected timer is attached to a GIC to deliver its
per-processor interrupts via PPIs. The memory mapped timer is attached to a GIC
to deliver its interrupts via SPIs.
- items:
- enum:
- arm,cortex-a15-timer
- enum:
- arm,armv7-timer
- items:
- enum:
- arm,armv7-timer
- items:
- enum:
- arm,armv8-timer
- description: secure timer irq
- description: non-secure timer irq
- description: virtual timer irq
- description: hypervisor timer irq
description: The frequency of the main counter, in Hz. Should be present
only where necessary to work around broken firmware which does not configure
CNTFRQ on all CPUs to a uniform correct value. Use of this property is
strongly discouraged; fix your firmware unless absolutely impossible.
type: boolean
description: If present, the timer is powered through an always-on power
domain, therefore it never loses context.
type: boolean
description: Indicates the presence of QorIQ erratum A-008585, which says
that reading the counter is unreliable unless the same value is returned
by back-to-back reads. This also affects writes to the tval register, due
to the implicit counter read.
type: boolean
description: Indicates the presence of Hisilicon erratum 161010101, which
says that reading the counters is unreliable in some cases, and reads may
return a value 32 beyond the correct value. This also affects writes to
the tval registers, due to the implicit counter read.
type: boolean
description: Firmware does not initialize any of the generic timer CPU
registers, which contain their architecturally-defined reset values. Only
supported for 32-bit systems which follow the ARMv7 architected reset
type: boolean
description: The main counter does not tick when the system is in
low-power system suspend on some SoCs. This behavior does not match the
Architecture Reference Manual's specification that the system counter "must
be implemented in an always-on power domain."
- compatible
- required:
- interrupts
- required:
- interrupts-extended
- |
timer {
compatible = "arm,cortex-a15-timer",
interrupts = <1 13 0xf08>,
<1 14 0xf08>,
<1 11 0xf08>,
<1 10 0xf08>;
clock-frequency = <100000000>;