blob: beacfffbdc3eba36468ca5164540e419473fbd48 [file] [log] [blame]
/*
* Copyright 2016 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
*/
#include <linux/delay.h>
#include <linux/fb.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/slab.h>
#include "hwmgr.h"
#include "amd_powerplay.h"
#include "hardwaremanager.h"
#include "ppatomfwctrl.h"
#include "atomfirmware.h"
#include "cgs_common.h"
#include "vega10_powertune.h"
#include "smu9.h"
#include "smu9_driver_if.h"
#include "vega10_inc.h"
#include "soc15_common.h"
#include "pppcielanes.h"
#include "vega10_hwmgr.h"
#include "vega10_smumgr.h"
#include "vega10_processpptables.h"
#include "vega10_pptable.h"
#include "vega10_thermal.h"
#include "pp_debug.h"
#include "amd_pcie_helpers.h"
#include "ppinterrupt.h"
#include "pp_overdriver.h"
#include "pp_thermal.h"
#include "vega10_baco.h"
#include "smuio/smuio_9_0_offset.h"
#include "smuio/smuio_9_0_sh_mask.h"
#define HBM_MEMORY_CHANNEL_WIDTH 128
static const uint32_t channel_number[] = {1, 2, 0, 4, 0, 8, 0, 16, 2};
#define mmDF_CS_AON0_DramBaseAddress0 0x0044
#define mmDF_CS_AON0_DramBaseAddress0_BASE_IDX 0
//DF_CS_AON0_DramBaseAddress0
#define DF_CS_AON0_DramBaseAddress0__AddrRngVal__SHIFT 0x0
#define DF_CS_AON0_DramBaseAddress0__LgcyMmioHoleEn__SHIFT 0x1
#define DF_CS_AON0_DramBaseAddress0__IntLvNumChan__SHIFT 0x4
#define DF_CS_AON0_DramBaseAddress0__IntLvAddrSel__SHIFT 0x8
#define DF_CS_AON0_DramBaseAddress0__DramBaseAddr__SHIFT 0xc
#define DF_CS_AON0_DramBaseAddress0__AddrRngVal_MASK 0x00000001L
#define DF_CS_AON0_DramBaseAddress0__LgcyMmioHoleEn_MASK 0x00000002L
#define DF_CS_AON0_DramBaseAddress0__IntLvNumChan_MASK 0x000000F0L
#define DF_CS_AON0_DramBaseAddress0__IntLvAddrSel_MASK 0x00000700L
#define DF_CS_AON0_DramBaseAddress0__DramBaseAddr_MASK 0xFFFFF000L
typedef enum {
CLK_SMNCLK = 0,
CLK_SOCCLK,
CLK_MP0CLK,
CLK_MP1CLK,
CLK_LCLK,
CLK_DCEFCLK,
CLK_VCLK,
CLK_DCLK,
CLK_ECLK,
CLK_UCLK,
CLK_GFXCLK,
CLK_COUNT,
} CLOCK_ID_e;
static const ULONG PhwVega10_Magic = (ULONG)(PHM_VIslands_Magic);
struct vega10_power_state *cast_phw_vega10_power_state(
struct pp_hw_power_state *hw_ps)
{
PP_ASSERT_WITH_CODE((PhwVega10_Magic == hw_ps->magic),
"Invalid Powerstate Type!",
return NULL;);
return (struct vega10_power_state *)hw_ps;
}
const struct vega10_power_state *cast_const_phw_vega10_power_state(
const struct pp_hw_power_state *hw_ps)
{
PP_ASSERT_WITH_CODE((PhwVega10_Magic == hw_ps->magic),
"Invalid Powerstate Type!",
return NULL;);
return (const struct vega10_power_state *)hw_ps;
}
static void vega10_set_default_registry_data(struct pp_hwmgr *hwmgr)
{
struct vega10_hwmgr *data = hwmgr->backend;
data->registry_data.sclk_dpm_key_disabled =
hwmgr->feature_mask & PP_SCLK_DPM_MASK ? false : true;
data->registry_data.socclk_dpm_key_disabled =
hwmgr->feature_mask & PP_SOCCLK_DPM_MASK ? false : true;
data->registry_data.mclk_dpm_key_disabled =
hwmgr->feature_mask & PP_MCLK_DPM_MASK ? false : true;
data->registry_data.pcie_dpm_key_disabled =
hwmgr->feature_mask & PP_PCIE_DPM_MASK ? false : true;
data->registry_data.dcefclk_dpm_key_disabled =
hwmgr->feature_mask & PP_DCEFCLK_DPM_MASK ? false : true;
if (hwmgr->feature_mask & PP_POWER_CONTAINMENT_MASK) {
data->registry_data.power_containment_support = 1;
data->registry_data.enable_pkg_pwr_tracking_feature = 1;
data->registry_data.enable_tdc_limit_feature = 1;
}
data->registry_data.clock_stretcher_support =
hwmgr->feature_mask & PP_CLOCK_STRETCH_MASK ? true : false;
data->registry_data.ulv_support =
hwmgr->feature_mask & PP_ULV_MASK ? true : false;
data->registry_data.sclk_deep_sleep_support =
hwmgr->feature_mask & PP_SCLK_DEEP_SLEEP_MASK ? true : false;
data->registry_data.disable_water_mark = 0;
data->registry_data.fan_control_support = 1;
data->registry_data.thermal_support = 1;
data->registry_data.fw_ctf_enabled = 1;
data->registry_data.avfs_support =
hwmgr->feature_mask & PP_AVFS_MASK ? true : false;
data->registry_data.led_dpm_enabled = 1;
data->registry_data.vr0hot_enabled = 1;
data->registry_data.vr1hot_enabled = 1;
data->registry_data.regulator_hot_gpio_support = 1;
data->registry_data.didt_support = 1;
if (data->registry_data.didt_support) {
data->registry_data.didt_mode = 6;
data->registry_data.sq_ramping_support = 1;
data->registry_data.db_ramping_support = 0;
data->registry_data.td_ramping_support = 0;
data->registry_data.tcp_ramping_support = 0;
data->registry_data.dbr_ramping_support = 0;
data->registry_data.edc_didt_support = 1;
data->registry_data.gc_didt_support = 0;
data->registry_data.psm_didt_support = 0;
}
data->display_voltage_mode = PPVEGA10_VEGA10DISPLAYVOLTAGEMODE_DFLT;
data->dcef_clk_quad_eqn_a = PPREGKEY_VEGA10QUADRATICEQUATION_DFLT;
data->dcef_clk_quad_eqn_b = PPREGKEY_VEGA10QUADRATICEQUATION_DFLT;
data->dcef_clk_quad_eqn_c = PPREGKEY_VEGA10QUADRATICEQUATION_DFLT;
data->disp_clk_quad_eqn_a = PPREGKEY_VEGA10QUADRATICEQUATION_DFLT;
data->disp_clk_quad_eqn_b = PPREGKEY_VEGA10QUADRATICEQUATION_DFLT;
data->disp_clk_quad_eqn_c = PPREGKEY_VEGA10QUADRATICEQUATION_DFLT;
data->pixel_clk_quad_eqn_a = PPREGKEY_VEGA10QUADRATICEQUATION_DFLT;
data->pixel_clk_quad_eqn_b = PPREGKEY_VEGA10QUADRATICEQUATION_DFLT;
data->pixel_clk_quad_eqn_c = PPREGKEY_VEGA10QUADRATICEQUATION_DFLT;
data->phy_clk_quad_eqn_a = PPREGKEY_VEGA10QUADRATICEQUATION_DFLT;
data->phy_clk_quad_eqn_b = PPREGKEY_VEGA10QUADRATICEQUATION_DFLT;
data->phy_clk_quad_eqn_c = PPREGKEY_VEGA10QUADRATICEQUATION_DFLT;
data->gfxclk_average_alpha = PPVEGA10_VEGA10GFXCLKAVERAGEALPHA_DFLT;
data->socclk_average_alpha = PPVEGA10_VEGA10SOCCLKAVERAGEALPHA_DFLT;
data->uclk_average_alpha = PPVEGA10_VEGA10UCLKCLKAVERAGEALPHA_DFLT;
data->gfx_activity_average_alpha = PPVEGA10_VEGA10GFXACTIVITYAVERAGEALPHA_DFLT;
}
static int vega10_set_features_platform_caps(struct pp_hwmgr *hwmgr)
{
struct vega10_hwmgr *data = hwmgr->backend;
struct phm_ppt_v2_information *table_info =
(struct phm_ppt_v2_information *)hwmgr->pptable;
struct amdgpu_device *adev = hwmgr->adev;
phm_cap_set(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_SclkDeepSleep);
phm_cap_set(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_DynamicPatchPowerState);
if (data->vddci_control == VEGA10_VOLTAGE_CONTROL_NONE)
phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_ControlVDDCI);
phm_cap_set(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_EnableSMU7ThermalManagement);
if (adev->pg_flags & AMD_PG_SUPPORT_UVD)
phm_cap_set(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_UVDPowerGating);
if (adev->pg_flags & AMD_PG_SUPPORT_VCE)
phm_cap_set(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_VCEPowerGating);
phm_cap_set(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_UnTabledHardwareInterface);
phm_cap_set(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_FanSpeedInTableIsRPM);
phm_cap_set(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_ODFuzzyFanControlSupport);
phm_cap_set(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_DynamicPowerManagement);
phm_cap_set(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_SMC);
/* power tune caps */
/* assume disabled */
phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_PowerContainment);
phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_DiDtSupport);
phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_SQRamping);
phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_DBRamping);
phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_TDRamping);
phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_TCPRamping);
phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_DBRRamping);
phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_DiDtEDCEnable);
phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_GCEDC);
phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_PSM);
if (data->registry_data.didt_support) {
phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DiDtSupport);
if (data->registry_data.sq_ramping_support)
phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SQRamping);
if (data->registry_data.db_ramping_support)
phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DBRamping);
if (data->registry_data.td_ramping_support)
phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_TDRamping);
if (data->registry_data.tcp_ramping_support)
phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_TCPRamping);
if (data->registry_data.dbr_ramping_support)
phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DBRRamping);
if (data->registry_data.edc_didt_support)
phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DiDtEDCEnable);
if (data->registry_data.gc_didt_support)
phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_GCEDC);
if (data->registry_data.psm_didt_support)
phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_PSM);
}
if (data->registry_data.power_containment_support)
phm_cap_set(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_PowerContainment);
phm_cap_set(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_CAC);
if (table_info->tdp_table->usClockStretchAmount &&
data->registry_data.clock_stretcher_support)
phm_cap_set(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_ClockStretcher);
phm_cap_set(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_RegulatorHot);
phm_cap_set(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_AutomaticDCTransition);
phm_cap_set(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_UVDDPM);
phm_cap_set(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_VCEDPM);
return 0;
}
static int vega10_odn_initial_default_setting(struct pp_hwmgr *hwmgr)
{
struct vega10_hwmgr *data = hwmgr->backend;
struct phm_ppt_v2_information *table_info =
(struct phm_ppt_v2_information *)(hwmgr->pptable);
struct vega10_odn_dpm_table *odn_table = &(data->odn_dpm_table);
struct vega10_odn_vddc_lookup_table *od_lookup_table;
struct phm_ppt_v1_voltage_lookup_table *vddc_lookup_table;
struct phm_ppt_v1_clock_voltage_dependency_table *dep_table[3];
struct phm_ppt_v1_clock_voltage_dependency_table *od_table[3];
struct pp_atomfwctrl_avfs_parameters avfs_params = {0};
uint32_t i;
int result;
result = pp_atomfwctrl_get_avfs_information(hwmgr, &avfs_params);
if (!result) {
data->odn_dpm_table.max_vddc = avfs_params.ulMaxVddc;
data->odn_dpm_table.min_vddc = avfs_params.ulMinVddc;
}
od_lookup_table = &odn_table->vddc_lookup_table;
vddc_lookup_table = table_info->vddc_lookup_table;
for (i = 0; i < vddc_lookup_table->count; i++)
od_lookup_table->entries[i].us_vdd = vddc_lookup_table->entries[i].us_vdd;
od_lookup_table->count = vddc_lookup_table->count;
dep_table[0] = table_info->vdd_dep_on_sclk;
dep_table[1] = table_info->vdd_dep_on_mclk;
dep_table[2] = table_info->vdd_dep_on_socclk;
od_table[0] = (struct phm_ppt_v1_clock_voltage_dependency_table *)&odn_table->vdd_dep_on_sclk;
od_table[1] = (struct phm_ppt_v1_clock_voltage_dependency_table *)&odn_table->vdd_dep_on_mclk;
od_table[2] = (struct phm_ppt_v1_clock_voltage_dependency_table *)&odn_table->vdd_dep_on_socclk;
for (i = 0; i < 3; i++)
smu_get_voltage_dependency_table_ppt_v1(dep_table[i], od_table[i]);
if (odn_table->max_vddc == 0 || odn_table->max_vddc > 2000)
odn_table->max_vddc = dep_table[0]->entries[dep_table[0]->count - 1].vddc;
if (odn_table->min_vddc == 0 || odn_table->min_vddc > 2000)
odn_table->min_vddc = dep_table[0]->entries[0].vddc;
i = od_table[2]->count - 1;
od_table[2]->entries[i].clk = hwmgr->platform_descriptor.overdriveLimit.memoryClock > od_table[2]->entries[i].clk ?
hwmgr->platform_descriptor.overdriveLimit.memoryClock :
od_table[2]->entries[i].clk;
od_table[2]->entries[i].vddc = odn_table->max_vddc > od_table[2]->entries[i].vddc ?
odn_table->max_vddc :
od_table[2]->entries[i].vddc;
return 0;
}
static void vega10_init_dpm_defaults(struct pp_hwmgr *hwmgr)
{
struct vega10_hwmgr *data = hwmgr->backend;
int i;
uint32_t sub_vendor_id, hw_revision;
uint32_t top32, bottom32;
struct amdgpu_device *adev = hwmgr->adev;
vega10_initialize_power_tune_defaults(hwmgr);
for (i = 0; i < GNLD_FEATURES_MAX; i++) {
data->smu_features[i].smu_feature_id = 0xffff;
data->smu_features[i].smu_feature_bitmap = 1 << i;
data->smu_features[i].enabled = false;
data->smu_features[i].supported = false;
}
data->smu_features[GNLD_DPM_PREFETCHER].smu_feature_id =
FEATURE_DPM_PREFETCHER_BIT;
data->smu_features[GNLD_DPM_GFXCLK].smu_feature_id =
FEATURE_DPM_GFXCLK_BIT;
data->smu_features[GNLD_DPM_UCLK].smu_feature_id =
FEATURE_DPM_UCLK_BIT;
data->smu_features[GNLD_DPM_SOCCLK].smu_feature_id =
FEATURE_DPM_SOCCLK_BIT;
data->smu_features[GNLD_DPM_UVD].smu_feature_id =
FEATURE_DPM_UVD_BIT;
data->smu_features[GNLD_DPM_VCE].smu_feature_id =
FEATURE_DPM_VCE_BIT;
data->smu_features[GNLD_DPM_MP0CLK].smu_feature_id =
FEATURE_DPM_MP0CLK_BIT;
data->smu_features[GNLD_DPM_LINK].smu_feature_id =
FEATURE_DPM_LINK_BIT;
data->smu_features[GNLD_DPM_DCEFCLK].smu_feature_id =
FEATURE_DPM_DCEFCLK_BIT;
data->smu_features[GNLD_ULV].smu_feature_id =
FEATURE_ULV_BIT;
data->smu_features[GNLD_AVFS].smu_feature_id =
FEATURE_AVFS_BIT;
data->smu_features[GNLD_DS_GFXCLK].smu_feature_id =
FEATURE_DS_GFXCLK_BIT;
data->smu_features[GNLD_DS_SOCCLK].smu_feature_id =
FEATURE_DS_SOCCLK_BIT;
data->smu_features[GNLD_DS_LCLK].smu_feature_id =
FEATURE_DS_LCLK_BIT;
data->smu_features[GNLD_PPT].smu_feature_id =
FEATURE_PPT_BIT;
data->smu_features[GNLD_TDC].smu_feature_id =
FEATURE_TDC_BIT;
data->smu_features[GNLD_THERMAL].smu_feature_id =
FEATURE_THERMAL_BIT;
data->smu_features[GNLD_GFX_PER_CU_CG].smu_feature_id =
FEATURE_GFX_PER_CU_CG_BIT;
data->smu_features[GNLD_RM].smu_feature_id =
FEATURE_RM_BIT;
data->smu_features[GNLD_DS_DCEFCLK].smu_feature_id =
FEATURE_DS_DCEFCLK_BIT;
data->smu_features[GNLD_ACDC].smu_feature_id =
FEATURE_ACDC_BIT;
data->smu_features[GNLD_VR0HOT].smu_feature_id =
FEATURE_VR0HOT_BIT;
data->smu_features[GNLD_VR1HOT].smu_feature_id =
FEATURE_VR1HOT_BIT;
data->smu_features[GNLD_FW_CTF].smu_feature_id =
FEATURE_FW_CTF_BIT;
data->smu_features[GNLD_LED_DISPLAY].smu_feature_id =
FEATURE_LED_DISPLAY_BIT;
data->smu_features[GNLD_FAN_CONTROL].smu_feature_id =
FEATURE_FAN_CONTROL_BIT;
data->smu_features[GNLD_ACG].smu_feature_id = FEATURE_ACG_BIT;
data->smu_features[GNLD_DIDT].smu_feature_id = FEATURE_GFX_EDC_BIT;
data->smu_features[GNLD_PCC_LIMIT].smu_feature_id = FEATURE_PCC_LIMIT_CONTROL_BIT;
if (!data->registry_data.prefetcher_dpm_key_disabled)
data->smu_features[GNLD_DPM_PREFETCHER].supported = true;
if (!data->registry_data.sclk_dpm_key_disabled)
data->smu_features[GNLD_DPM_GFXCLK].supported = true;
if (!data->registry_data.mclk_dpm_key_disabled)
data->smu_features[GNLD_DPM_UCLK].supported = true;
if (!data->registry_data.socclk_dpm_key_disabled)
data->smu_features[GNLD_DPM_SOCCLK].supported = true;
if (PP_CAP(PHM_PlatformCaps_UVDDPM))
data->smu_features[GNLD_DPM_UVD].supported = true;
if (PP_CAP(PHM_PlatformCaps_VCEDPM))
data->smu_features[GNLD_DPM_VCE].supported = true;
if (!data->registry_data.pcie_dpm_key_disabled)
data->smu_features[GNLD_DPM_LINK].supported = true;
if (!data->registry_data.dcefclk_dpm_key_disabled)
data->smu_features[GNLD_DPM_DCEFCLK].supported = true;
if (PP_CAP(PHM_PlatformCaps_SclkDeepSleep) &&
data->registry_data.sclk_deep_sleep_support) {
data->smu_features[GNLD_DS_GFXCLK].supported = true;
data->smu_features[GNLD_DS_SOCCLK].supported = true;
data->smu_features[GNLD_DS_LCLK].supported = true;
data->smu_features[GNLD_DS_DCEFCLK].supported = true;
}
if (data->registry_data.enable_pkg_pwr_tracking_feature)
data->smu_features[GNLD_PPT].supported = true;
if (data->registry_data.enable_tdc_limit_feature)
data->smu_features[GNLD_TDC].supported = true;
if (data->registry_data.thermal_support)
data->smu_features[GNLD_THERMAL].supported = true;
if (data->registry_data.fan_control_support)
data->smu_features[GNLD_FAN_CONTROL].supported = true;
if (data->registry_data.fw_ctf_enabled)
data->smu_features[GNLD_FW_CTF].supported = true;
if (data->registry_data.avfs_support)
data->smu_features[GNLD_AVFS].supported = true;
if (data->registry_data.led_dpm_enabled)
data->smu_features[GNLD_LED_DISPLAY].supported = true;
if (data->registry_data.vr1hot_enabled)
data->smu_features[GNLD_VR1HOT].supported = true;
if (data->registry_data.vr0hot_enabled)
data->smu_features[GNLD_VR0HOT].supported = true;
smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetSmuVersion);
hwmgr->smu_version = smum_get_argument(hwmgr);
/* ACG firmware has major version 5 */
if ((hwmgr->smu_version & 0xff000000) == 0x5000000)
data->smu_features[GNLD_ACG].supported = true;
if (data->registry_data.didt_support)
data->smu_features[GNLD_DIDT].supported = true;
hw_revision = adev->pdev->revision;
sub_vendor_id = adev->pdev->subsystem_vendor;
if ((hwmgr->chip_id == 0x6862 ||
hwmgr->chip_id == 0x6861 ||
hwmgr->chip_id == 0x6868) &&
(hw_revision == 0) &&
(sub_vendor_id != 0x1002))
data->smu_features[GNLD_PCC_LIMIT].supported = true;
/* Get the SN to turn into a Unique ID */
smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ReadSerialNumTop32);
top32 = smum_get_argument(hwmgr);
smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ReadSerialNumBottom32);
bottom32 = smum_get_argument(hwmgr);
adev->unique_id = ((uint64_t)bottom32 << 32) | top32;
}
#ifdef PPLIB_VEGA10_EVV_SUPPORT
static int vega10_get_socclk_for_voltage_evv(struct pp_hwmgr *hwmgr,
phm_ppt_v1_voltage_lookup_table *lookup_table,
uint16_t virtual_voltage_id, int32_t *socclk)
{
uint8_t entry_id;
uint8_t voltage_id;
struct phm_ppt_v2_information *table_info =
(struct phm_ppt_v2_information *)(hwmgr->pptable);
PP_ASSERT_WITH_CODE(lookup_table->count != 0,
"Lookup table is empty",
return -EINVAL);
/* search for leakage voltage ID 0xff01 ~ 0xff08 and sclk */
for (entry_id = 0; entry_id < table_info->vdd_dep_on_sclk->count; entry_id++) {
voltage_id = table_info->vdd_dep_on_socclk->entries[entry_id].vddInd;
if (lookup_table->entries[voltage_id].us_vdd == virtual_voltage_id)
break;
}
PP_ASSERT_WITH_CODE(entry_id < table_info->vdd_dep_on_socclk->count,
"Can't find requested voltage id in vdd_dep_on_socclk table!",
return -EINVAL);
*socclk = table_info->vdd_dep_on_socclk->entries[entry_id].clk;
return 0;
}
#define ATOM_VIRTUAL_VOLTAGE_ID0 0xff01
/**
* Get Leakage VDDC based on leakage ID.
*
* @param hwmgr the address of the powerplay hardware manager.
* @return always 0.
*/
static int vega10_get_evv_voltages(struct pp_hwmgr *hwmgr)
{
struct vega10_hwmgr *data = hwmgr->backend;
uint16_t vv_id;
uint32_t vddc = 0;
uint16_t i, j;
uint32_t sclk = 0;
struct phm_ppt_v2_information *table_info =
(struct phm_ppt_v2_information *)hwmgr->pptable;
struct phm_ppt_v1_clock_voltage_dependency_table *socclk_table =
table_info->vdd_dep_on_socclk;
int result;
for (i = 0; i < VEGA10_MAX_LEAKAGE_COUNT; i++) {
vv_id = ATOM_VIRTUAL_VOLTAGE_ID0 + i;
if (!vega10_get_socclk_for_voltage_evv(hwmgr,
table_info->vddc_lookup_table, vv_id, &sclk)) {
if (PP_CAP(PHM_PlatformCaps_ClockStretcher)) {
for (j = 1; j < socclk_table->count; j++) {
if (socclk_table->entries[j].clk == sclk &&
socclk_table->entries[j].cks_enable == 0) {
sclk += 5000;
break;
}
}
}
PP_ASSERT_WITH_CODE(!atomctrl_get_voltage_evv_on_sclk_ai(hwmgr,
VOLTAGE_TYPE_VDDC, sclk, vv_id, &vddc),
"Error retrieving EVV voltage value!",
continue);
/* need to make sure vddc is less than 2v or else, it could burn the ASIC. */
PP_ASSERT_WITH_CODE((vddc < 2000 && vddc != 0),
"Invalid VDDC value", result = -EINVAL;);
/* the voltage should not be zero nor equal to leakage ID */
if (vddc != 0 && vddc != vv_id) {
data->vddc_leakage.actual_voltage[data->vddc_leakage.count] = (uint16_t)(vddc/100);
data->vddc_leakage.leakage_id[data->vddc_leakage.count] = vv_id;
data->vddc_leakage.count++;
}
}
}
return 0;
}
/**
* Change virtual leakage voltage to actual value.
*
* @param hwmgr the address of the powerplay hardware manager.
* @param pointer to changing voltage
* @param pointer to leakage table
*/
static void vega10_patch_with_vdd_leakage(struct pp_hwmgr *hwmgr,
uint16_t *voltage, struct vega10_leakage_voltage *leakage_table)
{
uint32_t index;
/* search for leakage voltage ID 0xff01 ~ 0xff08 */
for (index = 0; index < leakage_table->count; index++) {
/* if this voltage matches a leakage voltage ID */
/* patch with actual leakage voltage */
if (leakage_table->leakage_id[index] == *voltage) {
*voltage = leakage_table->actual_voltage[index];
break;
}
}
if (*voltage > ATOM_VIRTUAL_VOLTAGE_ID0)
pr_info("Voltage value looks like a Leakage ID but it's not patched\n");
}
/**
* Patch voltage lookup table by EVV leakages.
*
* @param hwmgr the address of the powerplay hardware manager.
* @param pointer to voltage lookup table
* @param pointer to leakage table
* @return always 0
*/
static int vega10_patch_lookup_table_with_leakage(struct pp_hwmgr *hwmgr,
phm_ppt_v1_voltage_lookup_table *lookup_table,
struct vega10_leakage_voltage *leakage_table)
{
uint32_t i;
for (i = 0; i < lookup_table->count; i++)
vega10_patch_with_vdd_leakage(hwmgr,
&lookup_table->entries[i].us_vdd, leakage_table);
return 0;
}
static int vega10_patch_clock_voltage_limits_with_vddc_leakage(
struct pp_hwmgr *hwmgr, struct vega10_leakage_voltage *leakage_table,
uint16_t *vddc)
{
vega10_patch_with_vdd_leakage(hwmgr, (uint16_t *)vddc, leakage_table);
return 0;
}
#endif
static int vega10_patch_voltage_dependency_tables_with_lookup_table(
struct pp_hwmgr *hwmgr)
{
uint8_t entry_id, voltage_id;
unsigned i;
struct phm_ppt_v2_information *table_info =
(struct phm_ppt_v2_information *)(hwmgr->pptable);
struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
table_info->mm_dep_table;
struct phm_ppt_v1_clock_voltage_dependency_table *mclk_table =
table_info->vdd_dep_on_mclk;
for (i = 0; i < 6; i++) {
struct phm_ppt_v1_clock_voltage_dependency_table *vdt;
switch (i) {
case 0: vdt = table_info->vdd_dep_on_socclk; break;
case 1: vdt = table_info->vdd_dep_on_sclk; break;
case 2: vdt = table_info->vdd_dep_on_dcefclk; break;
case 3: vdt = table_info->vdd_dep_on_pixclk; break;
case 4: vdt = table_info->vdd_dep_on_dispclk; break;
case 5: vdt = table_info->vdd_dep_on_phyclk; break;
}
for (entry_id = 0; entry_id < vdt->count; entry_id++) {
voltage_id = vdt->entries[entry_id].vddInd;
vdt->entries[entry_id].vddc =
table_info->vddc_lookup_table->entries[voltage_id].us_vdd;
}
}
for (entry_id = 0; entry_id < mm_table->count; ++entry_id) {
voltage_id = mm_table->entries[entry_id].vddcInd;
mm_table->entries[entry_id].vddc =
table_info->vddc_lookup_table->entries[voltage_id].us_vdd;
}
for (entry_id = 0; entry_id < mclk_table->count; ++entry_id) {
voltage_id = mclk_table->entries[entry_id].vddInd;
mclk_table->entries[entry_id].vddc =
table_info->vddc_lookup_table->entries[voltage_id].us_vdd;
voltage_id = mclk_table->entries[entry_id].vddciInd;
mclk_table->entries[entry_id].vddci =
table_info->vddci_lookup_table->entries[voltage_id].us_vdd;
voltage_id = mclk_table->entries[entry_id].mvddInd;
mclk_table->entries[entry_id].mvdd =
table_info->vddmem_lookup_table->entries[voltage_id].us_vdd;
}
return 0;
}
static int vega10_sort_lookup_table(struct pp_hwmgr *hwmgr,
struct phm_ppt_v1_voltage_lookup_table *lookup_table)
{
uint32_t table_size, i, j;
struct phm_ppt_v1_voltage_lookup_record tmp_voltage_lookup_record;
PP_ASSERT_WITH_CODE(lookup_table && lookup_table->count,
"Lookup table is empty", return -EINVAL);
table_size = lookup_table->count;
/* Sorting voltages */
for (i = 0; i < table_size - 1; i++) {
for (j = i + 1; j > 0; j--) {
if (lookup_table->entries[j].us_vdd <
lookup_table->entries[j - 1].us_vdd) {
tmp_voltage_lookup_record = lookup_table->entries[j - 1];
lookup_table->entries[j - 1] = lookup_table->entries[j];
lookup_table->entries[j] = tmp_voltage_lookup_record;
}
}
}
return 0;
}
static int vega10_complete_dependency_tables(struct pp_hwmgr *hwmgr)
{
int result = 0;
int tmp_result;
struct phm_ppt_v2_information *table_info =
(struct phm_ppt_v2_information *)(hwmgr->pptable);
#ifdef PPLIB_VEGA10_EVV_SUPPORT
struct vega10_hwmgr *data = hwmgr->backend;
tmp_result = vega10_patch_lookup_table_with_leakage(hwmgr,
table_info->vddc_lookup_table, &(data->vddc_leakage));
if (tmp_result)
result = tmp_result;
tmp_result = vega10_patch_clock_voltage_limits_with_vddc_leakage(hwmgr,
&(data->vddc_leakage), &table_info->max_clock_voltage_on_dc.vddc);
if (tmp_result)
result = tmp_result;
#endif
tmp_result = vega10_patch_voltage_dependency_tables_with_lookup_table(hwmgr);
if (tmp_result)
result = tmp_result;
tmp_result = vega10_sort_lookup_table(hwmgr, table_info->vddc_lookup_table);
if (tmp_result)
result = tmp_result;
return result;
}
static int vega10_set_private_data_based_on_pptable(struct pp_hwmgr *hwmgr)
{
struct phm_ppt_v2_information *table_info =
(struct phm_ppt_v2_information *)(hwmgr->pptable);
struct phm_ppt_v1_clock_voltage_dependency_table *allowed_sclk_vdd_table =
table_info->vdd_dep_on_socclk;
struct phm_ppt_v1_clock_voltage_dependency_table *allowed_mclk_vdd_table =
table_info->vdd_dep_on_mclk;
PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table,
"VDD dependency on SCLK table is missing. This table is mandatory", return -EINVAL);
PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table->count >= 1,
"VDD dependency on SCLK table is empty. This table is mandatory", return -EINVAL);
PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table,
"VDD dependency on MCLK table is missing. This table is mandatory", return -EINVAL);
PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table->count >= 1,
"VDD dependency on MCLK table is empty. This table is mandatory", return -EINVAL);
table_info->max_clock_voltage_on_ac.sclk =
allowed_sclk_vdd_table->entries[allowed_sclk_vdd_table->count - 1].clk;
table_info->max_clock_voltage_on_ac.mclk =
allowed_mclk_vdd_table->entries[allowed_mclk_vdd_table->count - 1].clk;
table_info->max_clock_voltage_on_ac.vddc =
allowed_sclk_vdd_table->entries[allowed_sclk_vdd_table->count - 1].vddc;
table_info->max_clock_voltage_on_ac.vddci =
allowed_mclk_vdd_table->entries[allowed_mclk_vdd_table->count - 1].vddci;
hwmgr->dyn_state.max_clock_voltage_on_ac.sclk =
table_info->max_clock_voltage_on_ac.sclk;
hwmgr->dyn_state.max_clock_voltage_on_ac.mclk =
table_info->max_clock_voltage_on_ac.mclk;
hwmgr->dyn_state.max_clock_voltage_on_ac.vddc =
table_info->max_clock_voltage_on_ac.vddc;
hwmgr->dyn_state.max_clock_voltage_on_ac.vddci =
table_info->max_clock_voltage_on_ac.vddci;
return 0;
}
static int vega10_hwmgr_backend_fini(struct pp_hwmgr *hwmgr)
{
kfree(hwmgr->dyn_state.vddc_dep_on_dal_pwrl);
hwmgr->dyn_state.vddc_dep_on_dal_pwrl = NULL;
kfree(hwmgr->backend);
hwmgr->backend = NULL;
return 0;
}
static int vega10_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
{
int result = 0;
struct vega10_hwmgr *data;
uint32_t config_telemetry = 0;
struct pp_atomfwctrl_voltage_table vol_table;
struct amdgpu_device *adev = hwmgr->adev;
data = kzalloc(sizeof(struct vega10_hwmgr), GFP_KERNEL);
if (data == NULL)
return -ENOMEM;
hwmgr->backend = data;
hwmgr->workload_mask = 1 << hwmgr->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT];
hwmgr->power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
hwmgr->default_power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
vega10_set_default_registry_data(hwmgr);
data->disable_dpm_mask = 0xff;
/* need to set voltage control types before EVV patching */
data->vddc_control = VEGA10_VOLTAGE_CONTROL_NONE;
data->mvdd_control = VEGA10_VOLTAGE_CONTROL_NONE;
data->vddci_control = VEGA10_VOLTAGE_CONTROL_NONE;
/* VDDCR_SOC */
if (pp_atomfwctrl_is_voltage_controlled_by_gpio_v4(hwmgr,
VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_SVID2)) {
if (!pp_atomfwctrl_get_voltage_table_v4(hwmgr,
VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_SVID2,
&vol_table)) {
config_telemetry = ((vol_table.telemetry_slope << 8) & 0xff00) |
(vol_table.telemetry_offset & 0xff);
data->vddc_control = VEGA10_VOLTAGE_CONTROL_BY_SVID2;
}
} else {
kfree(hwmgr->backend);
hwmgr->backend = NULL;
PP_ASSERT_WITH_CODE(false,
"VDDCR_SOC is not SVID2!",
return -1);
}
/* MVDDC */
if (pp_atomfwctrl_is_voltage_controlled_by_gpio_v4(hwmgr,
VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_SVID2)) {
if (!pp_atomfwctrl_get_voltage_table_v4(hwmgr,
VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_SVID2,
&vol_table)) {
config_telemetry |=
((vol_table.telemetry_slope << 24) & 0xff000000) |
((vol_table.telemetry_offset << 16) & 0xff0000);
data->mvdd_control = VEGA10_VOLTAGE_CONTROL_BY_SVID2;
}
}
/* VDDCI_MEM */
if (PP_CAP(PHM_PlatformCaps_ControlVDDCI)) {
if (pp_atomfwctrl_is_voltage_controlled_by_gpio_v4(hwmgr,
VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_GPIO_LUT))
data->vddci_control = VEGA10_VOLTAGE_CONTROL_BY_GPIO;
}
data->config_telemetry = config_telemetry;
vega10_set_features_platform_caps(hwmgr);
vega10_init_dpm_defaults(hwmgr);
#ifdef PPLIB_VEGA10_EVV_SUPPORT
/* Get leakage voltage based on leakage ID. */
PP_ASSERT_WITH_CODE(!vega10_get_evv_voltages(hwmgr),
"Get EVV Voltage Failed. Abort Driver loading!",
return -1);
#endif
/* Patch our voltage dependency table with actual leakage voltage
* We need to perform leakage translation before it's used by other functions
*/
vega10_complete_dependency_tables(hwmgr);
/* Parse pptable data read from VBIOS */
vega10_set_private_data_based_on_pptable(hwmgr);
data->is_tlu_enabled = false;
hwmgr->platform_descriptor.hardwareActivityPerformanceLevels =
VEGA10_MAX_HARDWARE_POWERLEVELS;
hwmgr->platform_descriptor.hardwarePerformanceLevels = 2;
hwmgr->platform_descriptor.minimumClocksReductionPercentage = 50;
hwmgr->platform_descriptor.vbiosInterruptId = 0x20000400; /* IRQ_SOURCE1_SW_INT */
/* The true clock step depends on the frequency, typically 4.5 or 9 MHz. Here we use 5. */
hwmgr->platform_descriptor.clockStep.engineClock = 500;
hwmgr->platform_descriptor.clockStep.memoryClock = 500;
data->total_active_cus = adev->gfx.cu_info.number;
/* Setup default Overdrive Fan control settings */
data->odn_fan_table.target_fan_speed =
hwmgr->thermal_controller.advanceFanControlParameters.usMaxFanRPM;
data->odn_fan_table.target_temperature =
hwmgr->thermal_controller.
advanceFanControlParameters.ucTargetTemperature;
data->odn_fan_table.min_performance_clock =
hwmgr->thermal_controller.advanceFanControlParameters.
ulMinFanSCLKAcousticLimit;
data->odn_fan_table.min_fan_limit =
hwmgr->thermal_controller.
advanceFanControlParameters.usFanPWMMinLimit *
hwmgr->thermal_controller.fanInfo.ulMaxRPM / 100;
data->mem_channels = (RREG32_SOC15(DF, 0, mmDF_CS_AON0_DramBaseAddress0) &
DF_CS_AON0_DramBaseAddress0__IntLvNumChan_MASK) >>
DF_CS_AON0_DramBaseAddress0__IntLvNumChan__SHIFT;
PP_ASSERT_WITH_CODE(data->mem_channels < ARRAY_SIZE(channel_number),
"Mem Channel Index Exceeded maximum!",
return -EINVAL);
return result;
}
static int vega10_init_sclk_threshold(struct pp_hwmgr *hwmgr)
{
struct vega10_hwmgr *data = hwmgr->backend;
data->low_sclk_interrupt_threshold = 0;
return 0;
}
static int vega10_setup_dpm_led_config(struct pp_hwmgr *hwmgr)
{
struct vega10_hwmgr *data = hwmgr->backend;
PPTable_t *pp_table = &(data->smc_state_table.pp_table);
struct pp_atomfwctrl_voltage_table table;
uint8_t i, j;
uint32_t mask = 0;
uint32_t tmp;
int32_t ret = 0;
ret = pp_atomfwctrl_get_voltage_table_v4(hwmgr, VOLTAGE_TYPE_LEDDPM,
VOLTAGE_OBJ_GPIO_LUT, &table);
if (!ret) {
tmp = table.mask_low;
for (i = 0, j = 0; i < 32; i++) {
if (tmp & 1) {
mask |= (uint32_t)(i << (8 * j));
if (++j >= 3)
break;
}
tmp >>= 1;
}
}
pp_table->LedPin0 = (uint8_t)(mask & 0xff);
pp_table->LedPin1 = (uint8_t)((mask >> 8) & 0xff);
pp_table->LedPin2 = (uint8_t)((mask >> 16) & 0xff);
return 0;
}
static int vega10_setup_asic_task(struct pp_hwmgr *hwmgr)
{
PP_ASSERT_WITH_CODE(!vega10_init_sclk_threshold(hwmgr),
"Failed to init sclk threshold!",
return -EINVAL);
PP_ASSERT_WITH_CODE(!vega10_setup_dpm_led_config(hwmgr),
"Failed to set up led dpm config!",
return -EINVAL);
smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_NumOfDisplays, 0);
return 0;
}
/**
* Remove repeated voltage values and create table with unique values.
*
* @param hwmgr the address of the powerplay hardware manager.
* @param vol_table the pointer to changing voltage table
* @return 0 in success
*/
static int vega10_trim_voltage_table(struct pp_hwmgr *hwmgr,
struct pp_atomfwctrl_voltage_table *vol_table)
{
uint32_t i, j;
uint16_t vvalue;
bool found = false;
struct pp_atomfwctrl_voltage_table *table;
PP_ASSERT_WITH_CODE(vol_table,
"Voltage Table empty.", return -EINVAL);
table = kzalloc(sizeof(struct pp_atomfwctrl_voltage_table),
GFP_KERNEL);
if (!table)
return -ENOMEM;
table->mask_low = vol_table->mask_low;
table->phase_delay = vol_table->phase_delay;
for (i = 0; i < vol_table->count; i++) {
vvalue = vol_table->entries[i].value;
found = false;
for (j = 0; j < table->count; j++) {
if (vvalue == table->entries[j].value) {
found = true;
break;
}
}
if (!found) {
table->entries[table->count].value = vvalue;
table->entries[table->count].smio_low =
vol_table->entries[i].smio_low;
table->count++;
}
}
memcpy(vol_table, table, sizeof(struct pp_atomfwctrl_voltage_table));
kfree(table);
return 0;
}
static int vega10_get_mvdd_voltage_table(struct pp_hwmgr *hwmgr,
phm_ppt_v1_clock_voltage_dependency_table *dep_table,
struct pp_atomfwctrl_voltage_table *vol_table)
{
int i;
PP_ASSERT_WITH_CODE(dep_table->count,
"Voltage Dependency Table empty.",
return -EINVAL);
vol_table->mask_low = 0;
vol_table->phase_delay = 0;
vol_table->count = dep_table->count;
for (i = 0; i < vol_table->count; i++) {
vol_table->entries[i].value = dep_table->entries[i].mvdd;
vol_table->entries[i].smio_low = 0;
}
PP_ASSERT_WITH_CODE(!vega10_trim_voltage_table(hwmgr,
vol_table),
"Failed to trim MVDD Table!",
return -1);
return 0;
}
static int vega10_get_vddci_voltage_table(struct pp_hwmgr *hwmgr,
phm_ppt_v1_clock_voltage_dependency_table *dep_table,
struct pp_atomfwctrl_voltage_table *vol_table)
{
uint32_t i;
PP_ASSERT_WITH_CODE(dep_table->count,
"Voltage Dependency Table empty.",
return -EINVAL);
vol_table->mask_low = 0;
vol_table->phase_delay = 0;
vol_table->count = dep_table->count;
for (i = 0; i < dep_table->count; i++) {
vol_table->entries[i].value = dep_table->entries[i].vddci;
vol_table->entries[i].smio_low = 0;
}
PP_ASSERT_WITH_CODE(!vega10_trim_voltage_table(hwmgr, vol_table),
"Failed to trim VDDCI table.",
return -1);
return 0;
}
static int vega10_get_vdd_voltage_table(struct pp_hwmgr *hwmgr,
phm_ppt_v1_clock_voltage_dependency_table *dep_table,
struct pp_atomfwctrl_voltage_table *vol_table)
{
int i;
PP_ASSERT_WITH_CODE(dep_table->count,
"Voltage Dependency Table empty.",
return -EINVAL);
vol_table->mask_low = 0;
vol_table->phase_delay = 0;
vol_table->count = dep_table->count;
for (i = 0; i < vol_table->count; i++) {
vol_table->entries[i].value = dep_table->entries[i].vddc;
vol_table->entries[i].smio_low = 0;
}
return 0;
}
/* ---- Voltage Tables ----
* If the voltage table would be bigger than
* what will fit into the state table on
* the SMC keep only the higher entries.
*/
static void vega10_trim_voltage_table_to_fit_state_table(
struct pp_hwmgr *hwmgr,
uint32_t max_vol_steps,
struct pp_atomfwctrl_voltage_table *vol_table)
{
unsigned int i, diff;
if (vol_table->count <= max_vol_steps)
return;
diff = vol_table->count - max_vol_steps;
for (i = 0; i < max_vol_steps; i++)
vol_table->entries[i] = vol_table->entries[i + diff];
vol_table->count = max_vol_steps;
}
/**
* Create Voltage Tables.
*
* @param hwmgr the address of the powerplay hardware manager.
* @return always 0
*/
static int vega10_construct_voltage_tables(struct pp_hwmgr *hwmgr)
{
struct vega10_hwmgr *data = hwmgr->backend;
struct phm_ppt_v2_information *table_info =
(struct phm_ppt_v2_information *)hwmgr->pptable;
int result;
if (data->mvdd_control == VEGA10_VOLTAGE_CONTROL_BY_SVID2 ||
data->mvdd_control == VEGA10_VOLTAGE_CONTROL_NONE) {
result = vega10_get_mvdd_voltage_table(hwmgr,
table_info->vdd_dep_on_mclk,
&(data->mvdd_voltage_table));
PP_ASSERT_WITH_CODE(!result,
"Failed to retrieve MVDDC table!",
return result);
}
if (data->vddci_control == VEGA10_VOLTAGE_CONTROL_NONE) {
result = vega10_get_vddci_voltage_table(hwmgr,
table_info->vdd_dep_on_mclk,
&(data->vddci_voltage_table));
PP_ASSERT_WITH_CODE(!result,
"Failed to retrieve VDDCI_MEM table!",
return result);
}
if (data->vddc_control == VEGA10_VOLTAGE_CONTROL_BY_SVID2 ||
data->vddc_control == VEGA10_VOLTAGE_CONTROL_NONE) {
result = vega10_get_vdd_voltage_table(hwmgr,
table_info->vdd_dep_on_sclk,
&(data->vddc_voltage_table));
PP_ASSERT_WITH_CODE(!result,
"Failed to retrieve VDDCR_SOC table!",
return result);
}
PP_ASSERT_WITH_CODE(data->vddc_voltage_table.count <= 16,
"Too many voltage values for VDDC. Trimming to fit state table.",
vega10_trim_voltage_table_to_fit_state_table(hwmgr,
16, &(data->vddc_voltage_table)));
PP_ASSERT_WITH_CODE(data->vddci_voltage_table.count <= 16,
"Too many voltage values for VDDCI. Trimming to fit state table.",
vega10_trim_voltage_table_to_fit_state_table(hwmgr,
16, &(data->vddci_voltage_table)));
PP_ASSERT_WITH_CODE(data->mvdd_voltage_table.count <= 16,
"Too many voltage values for MVDD. Trimming to fit state table.",
vega10_trim_voltage_table_to_fit_state_table(hwmgr,
16, &(data->mvdd_voltage_table)));
return 0;
}
/*
* @fn vega10_init_dpm_state
* @brief Function to initialize all Soft Min/Max and Hard Min/Max to 0xff.
*
* @param dpm_state - the address of the DPM Table to initiailize.
* @return None.
*/
static void vega10_init_dpm_state(struct vega10_dpm_state *dpm_state)
{
dpm_state->soft_min_level = 0xff;
dpm_state->soft_max_level = 0xff;
dpm_state->hard_min_level = 0xff;
dpm_state->hard_max_level = 0xff;
}
static void vega10_setup_default_single_dpm_table(struct pp_hwmgr *hwmgr,
struct vega10_single_dpm_table *dpm_table,
struct phm_ppt_v1_clock_voltage_dependency_table *dep_table)
{
int i;
dpm_table->count = 0;
for (i = 0; i < dep_table->count; i++) {
if (i == 0 || dpm_table->dpm_levels[dpm_table->count - 1].value <=
dep_table->entries[i].clk) {
dpm_table->dpm_levels[dpm_table->count].value =
dep_table->entries[i].clk;
dpm_table->dpm_levels[dpm_table->count].enabled = true;
dpm_table->count++;
}
}
}
static int vega10_setup_default_pcie_table(struct pp_hwmgr *hwmgr)
{
struct vega10_hwmgr *data = hwmgr->backend;
struct vega10_pcie_table *pcie_table = &(data->dpm_table.pcie_table);
struct phm_ppt_v2_information *table_info =
(struct phm_ppt_v2_information *)(hwmgr->pptable);
struct phm_ppt_v1_pcie_table *bios_pcie_table =
table_info->pcie_table;
uint32_t i;
PP_ASSERT_WITH_CODE(bios_pcie_table->count,
"Incorrect number of PCIE States from VBIOS!",
return -1);
for (i = 0; i < NUM_LINK_LEVELS; i++) {
if (data->registry_data.pcieSpeedOverride)
pcie_table->pcie_gen[i] =
data->registry_data.pcieSpeedOverride;
else
pcie_table->pcie_gen[i] =
bios_pcie_table->entries[i].gen_speed;
if (data->registry_data.pcieLaneOverride)
pcie_table->pcie_lane[i] = (uint8_t)encode_pcie_lane_width(
data->registry_data.pcieLaneOverride);
else
pcie_table->pcie_lane[i] = (uint8_t)encode_pcie_lane_width(
bios_pcie_table->entries[i].lane_width);
if (data->registry_data.pcieClockOverride)
pcie_table->lclk[i] =
data->registry_data.pcieClockOverride;
else
pcie_table->lclk[i] =
bios_pcie_table->entries[i].pcie_sclk;
}
pcie_table->count = NUM_LINK_LEVELS;
return 0;
}
/*
* This function is to initialize all DPM state tables
* for SMU based on the dependency table.
* Dynamic state patching function will then trim these
* state tables to the allowed range based
* on the power policy or external client requests,
* such as UVD request, etc.
*/
static int vega10_setup_default_dpm_tables(struct pp_hwmgr *hwmgr)
{
struct vega10_hwmgr *data = hwmgr->backend;
struct phm_ppt_v2_information *table_info =
(struct phm_ppt_v2_information *)(hwmgr->pptable);
struct vega10_single_dpm_table *dpm_table;
uint32_t i;
struct phm_ppt_v1_clock_voltage_dependency_table *dep_soc_table =
table_info->vdd_dep_on_socclk;
struct phm_ppt_v1_clock_voltage_dependency_table *dep_gfx_table =
table_info->vdd_dep_on_sclk;
struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table =
table_info->vdd_dep_on_mclk;
struct phm_ppt_v1_mm_clock_voltage_dependency_table *dep_mm_table =
table_info->mm_dep_table;
struct phm_ppt_v1_clock_voltage_dependency_table *dep_dcef_table =
table_info->vdd_dep_on_dcefclk;
struct phm_ppt_v1_clock_voltage_dependency_table *dep_pix_table =
table_info->vdd_dep_on_pixclk;
struct phm_ppt_v1_clock_voltage_dependency_table *dep_disp_table =
table_info->vdd_dep_on_dispclk;
struct phm_ppt_v1_clock_voltage_dependency_table *dep_phy_table =
table_info->vdd_dep_on_phyclk;
PP_ASSERT_WITH_CODE(dep_soc_table,
"SOCCLK dependency table is missing. This table is mandatory",
return -EINVAL);
PP_ASSERT_WITH_CODE(dep_soc_table->count >= 1,
"SOCCLK dependency table is empty. This table is mandatory",
return -EINVAL);
PP_ASSERT_WITH_CODE(dep_gfx_table,
"GFXCLK dependency table is missing. This table is mandatory",
return -EINVAL);
PP_ASSERT_WITH_CODE(dep_gfx_table->count >= 1,
"GFXCLK dependency table is empty. This table is mandatory",
return -EINVAL);
PP_ASSERT_WITH_CODE(dep_mclk_table,
"MCLK dependency table is missing. This table is mandatory",
return -EINVAL);
PP_ASSERT_WITH_CODE(dep_mclk_table->count >= 1,
"MCLK dependency table has to have is missing. This table is mandatory",
return -EINVAL);
/* Initialize Sclk DPM table based on allow Sclk values */
dpm_table = &(data->dpm_table.soc_table);
vega10_setup_default_single_dpm_table(hwmgr,
dpm_table,
dep_soc_table);
vega10_init_dpm_state(&(dpm_table->dpm_state));
dpm_table = &(data->dpm_table.gfx_table);
vega10_setup_default_single_dpm_table(hwmgr,
dpm_table,
dep_gfx_table);
if (hwmgr->platform_descriptor.overdriveLimit.engineClock == 0)
hwmgr->platform_descriptor.overdriveLimit.engineClock =
dpm_table->dpm_levels[dpm_table->count-1].value;
vega10_init_dpm_state(&(dpm_table->dpm_state));
/* Initialize Mclk DPM table based on allow Mclk values */
data->dpm_table.mem_table.count = 0;
dpm_table = &(data->dpm_table.mem_table);
vega10_setup_default_single_dpm_table(hwmgr,
dpm_table,
dep_mclk_table);
if (hwmgr->platform_descriptor.overdriveLimit.memoryClock == 0)
hwmgr->platform_descriptor.overdriveLimit.memoryClock =
dpm_table->dpm_levels[dpm_table->count-1].value;
vega10_init_dpm_state(&(dpm_table->dpm_state));
data->dpm_table.eclk_table.count = 0;
dpm_table = &(data->dpm_table.eclk_table);
for (i = 0; i < dep_mm_table->count; i++) {
if (i == 0 || dpm_table->dpm_levels
[dpm_table->count - 1].value <=
dep_mm_table->entries[i].eclk) {
dpm_table->dpm_levels[dpm_table->count].value =
dep_mm_table->entries[i].eclk;
dpm_table->dpm_levels[dpm_table->count].enabled =
(i == 0) ? true : false;
dpm_table->count++;
}
}
vega10_init_dpm_state(&(dpm_table->dpm_state));
data->dpm_table.vclk_table.count = 0;
data->dpm_table.dclk_table.count = 0;
dpm_table = &(data->dpm_table.vclk_table);
for (i = 0; i < dep_mm_table->count; i++) {
if (i == 0 || dpm_table->dpm_levels
[dpm_table->count - 1].value <=
dep_mm_table->entries[i].vclk) {
dpm_table->dpm_levels[dpm_table->count].value =
dep_mm_table->entries[i].vclk;
dpm_table->dpm_levels[dpm_table->count].enabled =
(i == 0) ? true : false;
dpm_table->count++;
}
}
vega10_init_dpm_state(&(dpm_table->dpm_state));
dpm_table = &(data->dpm_table.dclk_table);
for (i = 0; i < dep_mm_table->count; i++) {
if (i == 0 || dpm_table->dpm_levels
[dpm_table->count - 1].value <=
dep_mm_table->entries[i].dclk) {
dpm_table->dpm_levels[dpm_table->count].value =
dep_mm_table->entries[i].dclk;
dpm_table->dpm_levels[dpm_table->count].enabled =
(i == 0) ? true : false;
dpm_table->count++;
}
}
vega10_init_dpm_state(&(dpm_table->dpm_state));
/* Assume there is no headless Vega10 for now */
dpm_table = &(data->dpm_table.dcef_table);
vega10_setup_default_single_dpm_table(hwmgr,
dpm_table,
dep_dcef_table);
vega10_init_dpm_state(&(dpm_table->dpm_state));
dpm_table = &(data->dpm_table.pixel_table);
vega10_setup_default_single_dpm_table(hwmgr,
dpm_table,
dep_pix_table);
vega10_init_dpm_state(&(dpm_table->dpm_state));
dpm_table = &(data->dpm_table.display_table);
vega10_setup_default_single_dpm_table(hwmgr,
dpm_table,
dep_disp_table);
vega10_init_dpm_state(&(dpm_table->dpm_state));
dpm_table = &(data->dpm_table.phy_table);
vega10_setup_default_single_dpm_table(hwmgr,
dpm_table,
dep_phy_table);
vega10_init_dpm_state(&(dpm_table->dpm_state));
vega10_setup_default_pcie_table(hwmgr);
/* Zero out the saved copy of the CUSTOM profile
* This will be checked when trying to set the profile
* and will require that new values be passed in
*/
data->custom_profile_mode[0] = 0;
data->custom_profile_mode[1] = 0;
data->custom_profile_mode[2] = 0;
data->custom_profile_mode[3] = 0;
/* save a copy of the default DPM table */
memcpy(&(data->golden_dpm_table), &(data->dpm_table),
sizeof(struct vega10_dpm_table));
return 0;
}
/*
* @fn vega10_populate_ulv_state
* @brief Function to provide parameters for Utral Low Voltage state to SMC.
*
* @param hwmgr - the address of the hardware manager.
* @return Always 0.
*/
static int vega10_populate_ulv_state(struct pp_hwmgr *hwmgr)
{
struct vega10_hwmgr *data = hwmgr->backend;
struct phm_ppt_v2_information *table_info =
(struct phm_ppt_v2_information *)(hwmgr->pptable);
data->smc_state_table.pp_table.UlvOffsetVid =
(uint8_t)table_info->us_ulv_voltage_offset;
data->smc_state_table.pp_table.UlvSmnclkDid =
(uint8_t)(table_info->us_ulv_smnclk_did);
data->smc_state_table.pp_table.UlvMp1clkDid =
(uint8_t)(table_info->us_ulv_mp1clk_did);
data->smc_state_table.pp_table.UlvGfxclkBypass =
(uint8_t)(table_info->us_ulv_gfxclk_bypass);
data->smc_state_table.pp_table.UlvPhaseSheddingPsi0 =
(uint8_t)(data->vddc_voltage_table.psi0_enable);
data->smc_state_table.pp_table.UlvPhaseSheddingPsi1 =
(uint8_t)(data->vddc_voltage_table.psi1_enable);
return 0;
}
static int vega10_populate_single_lclk_level(struct pp_hwmgr *hwmgr,
uint32_t lclock, uint8_t *curr_lclk_did)
{
struct pp_atomfwctrl_clock_dividers_soc15 dividers;
PP_ASSERT_WITH_CODE(!pp_atomfwctrl_get_gpu_pll_dividers_vega10(
hwmgr,
COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
lclock, &dividers),
"Failed to get LCLK clock settings from VBIOS!",
return -1);
*curr_lclk_did = dividers.ulDid;
return 0;
}
static int vega10_populate_smc_link_levels(struct pp_hwmgr *hwmgr)
{
int result = -1;
struct vega10_hwmgr *data = hwmgr->backend;
PPTable_t *pp_table = &(data->smc_state_table.pp_table);
struct vega10_pcie_table *pcie_table =
&(data->dpm_table.pcie_table);
uint32_t i, j;
for (i = 0; i < pcie_table->count; i++) {
pp_table->PcieGenSpeed[i] = pcie_table->pcie_gen[i];
pp_table->PcieLaneCount[i] = pcie_table->pcie_lane[i];
result = vega10_populate_single_lclk_level(hwmgr,
pcie_table->lclk[i], &(pp_table->LclkDid[i]));
if (result) {
pr_info("Populate LClock Level %d Failed!\n", i);
return result;
}
}
j = i - 1;
while (i < NUM_LINK_LEVELS) {
pp_table->PcieGenSpeed[i] = pcie_table->pcie_gen[j];
pp_table->PcieLaneCount[i] = pcie_table->pcie_lane[j];
result = vega10_populate_single_lclk_level(hwmgr,
pcie_table->lclk[j], &(pp_table->LclkDid[i]));
if (result) {
pr_info("Populate LClock Level %d Failed!\n", i);
return result;
}
i++;
}
return result;
}
/**
* Populates single SMC GFXSCLK structure using the provided engine clock
*
* @param hwmgr the address of the hardware manager
* @param gfx_clock the GFX clock to use to populate the structure.
* @param current_gfxclk_level location in PPTable for the SMC GFXCLK structure.
*/
static int vega10_populate_single_gfx_level(struct pp_hwmgr *hwmgr,
uint32_t gfx_clock, PllSetting_t *current_gfxclk_level,
uint32_t *acg_freq)
{
struct phm_ppt_v2_information *table_info =
(struct phm_ppt_v2_information *)(hwmgr->pptable);
struct phm_ppt_v1_clock_voltage_dependency_table *dep_on_sclk;
struct vega10_hwmgr *data = hwmgr->backend;
struct pp_atomfwctrl_clock_dividers_soc15 dividers;
uint32_t gfx_max_clock =
hwmgr->platform_descriptor.overdriveLimit.engineClock;
uint32_t i = 0;
if (hwmgr->od_enabled)
dep_on_sclk = (struct phm_ppt_v1_clock_voltage_dependency_table *)
&(data->odn_dpm_table.vdd_dep_on_sclk);
else
dep_on_sclk = table_info->vdd_dep_on_sclk;
PP_ASSERT_WITH_CODE(dep_on_sclk,
"Invalid SOC_VDD-GFX_CLK Dependency Table!",
return -EINVAL);
if (data->need_update_dpm_table & DPMTABLE_OD_UPDATE_SCLK)
gfx_clock = gfx_clock > gfx_max_clock ? gfx_max_clock : gfx_clock;
else {
for (i = 0; i < dep_on_sclk->count; i++) {
if (dep_on_sclk->entries[i].clk == gfx_clock)
break;
}
PP_ASSERT_WITH_CODE(dep_on_sclk->count > i,
"Cannot find gfx_clk in SOC_VDD-GFX_CLK!",
return -EINVAL);
}
PP_ASSERT_WITH_CODE(!pp_atomfwctrl_get_gpu_pll_dividers_vega10(hwmgr,
COMPUTE_GPUCLK_INPUT_FLAG_GFXCLK,
gfx_clock, &dividers),
"Failed to get GFX Clock settings from VBIOS!",
return -EINVAL);
/* Feedback Multiplier: bit 0:8 int, bit 15:12 post_div, bit 31:16 frac */
current_gfxclk_level->FbMult =
cpu_to_le32(dividers.ulPll_fb_mult);
/* Spread FB Multiplier bit: bit 0:8 int, bit 31:16 frac */
current_gfxclk_level->SsOn = dividers.ucPll_ss_enable;
current_gfxclk_level->SsFbMult =
cpu_to_le32(dividers.ulPll_ss_fbsmult);
current_gfxclk_level->SsSlewFrac =
cpu_to_le16(dividers.usPll_ss_slew_frac);
current_gfxclk_level->Did = (uint8_t)(dividers.ulDid);
*acg_freq = gfx_clock / 100; /* 100 Khz to Mhz conversion */
return 0;
}
/**
* @brief Populates single SMC SOCCLK structure using the provided clock.
*
* @param hwmgr - the address of the hardware manager.
* @param soc_clock - the SOC clock to use to populate the structure.
* @param current_socclk_level - location in PPTable for the SMC SOCCLK structure.
* @return 0 on success..
*/
static int vega10_populate_single_soc_level(struct pp_hwmgr *hwmgr,
uint32_t soc_clock, uint8_t *current_soc_did,
uint8_t *current_vol_index)
{
struct vega10_hwmgr *data = hwmgr->backend;
struct phm_ppt_v2_information *table_info =
(struct phm_ppt_v2_information *)(hwmgr->pptable);
struct phm_ppt_v1_clock_voltage_dependency_table *dep_on_soc;
struct pp_atomfwctrl_clock_dividers_soc15 dividers;
uint32_t i;
if (hwmgr->od_enabled) {
dep_on_soc = (struct phm_ppt_v1_clock_voltage_dependency_table *)
&data->odn_dpm_table.vdd_dep_on_socclk;
for (i = 0; i < dep_on_soc->count; i++) {
if (dep_on_soc->entries[i].clk >= soc_clock)
break;
}
} else {
dep_on_soc = table_info->vdd_dep_on_socclk;
for (i = 0; i < dep_on_soc->count; i++) {
if (dep_on_soc->entries[i].clk == soc_clock)
break;
}
}
PP_ASSERT_WITH_CODE(dep_on_soc->count > i,
"Cannot find SOC_CLK in SOC_VDD-SOC_CLK Dependency Table",
return -EINVAL);
PP_ASSERT_WITH_CODE(!pp_atomfwctrl_get_gpu_pll_dividers_vega10(hwmgr,
COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
soc_clock, &dividers),
"Failed to get SOC Clock settings from VBIOS!",
return -EINVAL);
*current_soc_did = (uint8_t)dividers.ulDid;
*current_vol_index = (uint8_t)(dep_on_soc->entries[i].vddInd);
return 0;
}
/**
* Populates all SMC SCLK levels' structure based on the trimmed allowed dpm engine clock states
*
* @param hwmgr the address of the hardware manager
*/
static int vega10_populate_all_graphic_levels(struct pp_hwmgr *hwmgr)
{
struct vega10_hwmgr *data = hwmgr->backend;
struct phm_ppt_v2_information *table_info =
(struct phm_ppt_v2_information *)(hwmgr->pptable);
PPTable_t *pp_table = &(data->smc_state_table.pp_table);
struct vega10_single_dpm_table *dpm_table = &(data->dpm_table.gfx_table);
int result = 0;
uint32_t i, j;
for (i = 0; i < dpm_table->count; i++) {
result = vega10_populate_single_gfx_level(hwmgr,
dpm_table->dpm_levels[i].value,
&(pp_table->GfxclkLevel[i]),
&(pp_table->AcgFreqTable[i]));
if (result)
return result;
}
j = i - 1;
while (i < NUM_GFXCLK_DPM_LEVELS) {
result = vega10_populate_single_gfx_level(hwmgr,
dpm_table->dpm_levels[j].value,
&(pp_table->GfxclkLevel[i]),
&(pp_table->AcgFreqTable[i]));
if (result)
return result;
i++;
}
pp_table->GfxclkSlewRate =
cpu_to_le16(table_info->us_gfxclk_slew_rate);
dpm_table = &(data->dpm_table.soc_table);
for (i = 0; i < dpm_table->count; i++) {
result = vega10_populate_single_soc_level(hwmgr,
dpm_table->dpm_levels[i].value,
&(pp_table->SocclkDid[i]),
&(pp_table->SocDpmVoltageIndex[i]));
if (result)
return result;
}
j = i - 1;
while (i < NUM_SOCCLK_DPM_LEVELS) {
result = vega10_populate_single_soc_level(hwmgr,
dpm_table->dpm_levels[j].value,
&(pp_table->SocclkDid[i]),
&(pp_table->SocDpmVoltageIndex[i]));
if (result)
return result;
i++;
}
return result;
}
static void vega10_populate_vddc_soc_levels(struct pp_hwmgr *hwmgr)
{
struct vega10_hwmgr *data = hwmgr->backend;
PPTable_t *pp_table = &(data->smc_state_table.pp_table);
struct phm_ppt_v2_information *table_info = hwmgr->pptable;
struct phm_ppt_v1_voltage_lookup_table *vddc_lookup_table;
uint8_t soc_vid = 0;
uint32_t i, max_vddc_level;
if (hwmgr->od_enabled)
vddc_lookup_table = (struct phm_ppt_v1_voltage_lookup_table *)&data->odn_dpm_table.vddc_lookup_table;
else
vddc_lookup_table = table_info->vddc_lookup_table;
max_vddc_level = vddc_lookup_table->count;
for (i = 0; i < max_vddc_level; i++) {
soc_vid = (uint8_t)convert_to_vid(vddc_lookup_table->entries[i].us_vdd);
pp_table->SocVid[i] = soc_vid;
}
while (i < MAX_REGULAR_DPM_NUMBER) {
pp_table->SocVid[i] = soc_vid;
i++;
}
}
/**
* @brief Populates single SMC GFXCLK structure using the provided clock.
*
* @param hwmgr - the address of the hardware manager.
* @param mem_clock - the memory clock to use to populate the structure.
* @return 0 on success..
*/
static int vega10_populate_single_memory_level(struct pp_hwmgr *hwmgr,
uint32_t mem_clock, uint8_t *current_mem_vid,
PllSetting_t *current_memclk_level, uint8_t *current_mem_soc_vind)
{
struct vega10_hwmgr *data = hwmgr->backend;
struct phm_ppt_v2_information *table_info =
(struct phm_ppt_v2_information *)(hwmgr->pptable);
struct phm_ppt_v1_clock_voltage_dependency_table *dep_on_mclk;
struct pp_atomfwctrl_clock_dividers_soc15 dividers;
uint32_t mem_max_clock =
hwmgr->platform_descriptor.overdriveLimit.memoryClock;
uint32_t i = 0;
if (hwmgr->od_enabled)
dep_on_mclk = (struct phm_ppt_v1_clock_voltage_dependency_table *)
&data->odn_dpm_table.vdd_dep_on_mclk;
else
dep_on_mclk = table_info->vdd_dep_on_mclk;
PP_ASSERT_WITH_CODE(dep_on_mclk,
"Invalid SOC_VDD-UCLK Dependency Table!",
return -EINVAL);
if (data->need_update_dpm_table & DPMTABLE_OD_UPDATE_MCLK) {
mem_clock = mem_clock > mem_max_clock ? mem_max_clock : mem_clock;
} else {
for (i = 0; i < dep_on_mclk->count; i++) {
if (dep_on_mclk->entries[i].clk == mem_clock)
break;
}
PP_ASSERT_WITH_CODE(dep_on_mclk->count > i,
"Cannot find UCLK in SOC_VDD-UCLK Dependency Table!",
return -EINVAL);
}
PP_ASSERT_WITH_CODE(!pp_atomfwctrl_get_gpu_pll_dividers_vega10(
hwmgr, COMPUTE_GPUCLK_INPUT_FLAG_UCLK, mem_clock, &dividers),
"Failed to get UCLK settings from VBIOS!",
return -1);
*current_mem_vid =
(uint8_t)(convert_to_vid(dep_on_mclk->entries[i].mvdd));
*current_mem_soc_vind =
(uint8_t)(dep_on_mclk->entries[i].vddInd);
current_memclk_level->FbMult = cpu_to_le32(dividers.ulPll_fb_mult);
current_memclk_level->Did = (uint8_t)(dividers.ulDid);
PP_ASSERT_WITH_CODE(current_memclk_level->Did >= 1,
"Invalid Divider ID!",
return -EINVAL);
return 0;
}
/**
* @brief Populates all SMC MCLK levels' structure based on the trimmed allowed dpm memory clock states.
*
* @param pHwMgr - the address of the hardware manager.
* @return PP_Result_OK on success.
*/
static int vega10_populate_all_memory_levels(struct pp_hwmgr *hwmgr)
{
struct vega10_hwmgr *data = hwmgr->backend;
PPTable_t *pp_table = &(data->smc_state_table.pp_table);
struct vega10_single_dpm_table *dpm_table =
&(data->dpm_table.mem_table);
int result = 0;
uint32_t i, j;
for (i = 0; i < dpm_table->count; i++) {
result = vega10_populate_single_memory_level(hwmgr,
dpm_table->dpm_levels[i].value,
&(pp_table->MemVid[i]),
&(pp_table->UclkLevel[i]),
&(pp_table->MemSocVoltageIndex[i]));
if (result)
return result;
}
j = i - 1;
while (i < NUM_UCLK_DPM_LEVELS) {
result = vega10_populate_single_memory_level(hwmgr,
dpm_table->dpm_levels[j].value,
&(pp_table->MemVid[i]),
&(pp_table->UclkLevel[i]),
&(pp_table->MemSocVoltageIndex[i]));
if (result)
return result;
i++;
}
pp_table->NumMemoryChannels = (uint16_t)(data->mem_channels);
pp_table->MemoryChannelWidth =
(uint16_t)(HBM_MEMORY_CHANNEL_WIDTH *
channel_number[data->mem_channels]);
pp_table->LowestUclkReservedForUlv =
(uint8_t)(data->lowest_uclk_reserved_for_ulv);
return result;
}
static int vega10_populate_single_display_type(struct pp_hwmgr *hwmgr,
DSPCLK_e disp_clock)
{
struct vega10_hwmgr *data = hwmgr->backend;
PPTable_t *pp_table = &(data->smc_state_table.pp_table);
struct phm_ppt_v2_information *table_info =
(struct phm_ppt_v2_information *)
(hwmgr->pptable);
struct phm_ppt_v1_clock_voltage_dependency_table *dep_table;
uint32_t i;
uint16_t clk = 0, vddc = 0;
uint8_t vid = 0;
switch (disp_clock) {
case DSPCLK_DCEFCLK:
dep_table = table_info->vdd_dep_on_dcefclk;
break;
case DSPCLK_DISPCLK:
dep_table = table_info->vdd_dep_on_dispclk;
break;
case DSPCLK_PIXCLK:
dep_table = table_info->vdd_dep_on_pixclk;
break;
case DSPCLK_PHYCLK:
dep_table = table_info->vdd_dep_on_phyclk;
break;
default:
return -1;
}
PP_ASSERT_WITH_CODE(dep_table->count <= NUM_DSPCLK_LEVELS,
"Number Of Entries Exceeded maximum!",
return -1);
for (i = 0; i < dep_table->count; i++) {
clk = (uint16_t)(dep_table->entries[i].clk / 100);
vddc = table_info->vddc_lookup_table->
entries[dep_table->entries[i].vddInd].us_vdd;
vid = (uint8_t)convert_to_vid(vddc);
pp_table->DisplayClockTable[disp_clock][i].Freq =
cpu_to_le16(clk);
pp_table->DisplayClockTable[disp_clock][i].Vid =
cpu_to_le16(vid);
}
while (i < NUM_DSPCLK_LEVELS) {
pp_table->DisplayClockTable[disp_clock][i].Freq =
cpu_to_le16(clk);
pp_table->DisplayClockTable[disp_clock][i].Vid =
cpu_to_le16(vid);
i++;
}
return 0;
}
static int vega10_populate_all_display_clock_levels(struct pp_hwmgr *hwmgr)
{
uint32_t i;
for (i = 0; i < DSPCLK_COUNT; i++) {
PP_ASSERT_WITH_CODE(!vega10_populate_single_display_type(hwmgr, i),
"Failed to populate Clock in DisplayClockTable!",
return -1);
}
return 0;
}
static int vega10_populate_single_eclock_level(struct pp_hwmgr *hwmgr,
uint32_t eclock, uint8_t *current_eclk_did,
uint8_t *current_soc_vol)
{
struct phm_ppt_v2_information *table_info =
(struct phm_ppt_v2_information *)(hwmgr->pptable);
struct phm_ppt_v1_mm_clock_voltage_dependency_table *dep_table =
table_info->mm_dep_table;
struct pp_atomfwctrl_clock_dividers_soc15 dividers;
uint32_t i;
PP_ASSERT_WITH_CODE(!pp_atomfwctrl_get_gpu_pll_dividers_vega10(hwmgr,
COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
eclock, &dividers),
"Failed to get ECLK clock settings from VBIOS!",
return -1);
*current_eclk_did = (uint8_t)dividers.ulDid;
for (i = 0; i < dep_table->count; i++) {
if (dep_table->entries[i].eclk == eclock)
*current_soc_vol = dep_table->entries[i].vddcInd;
}
return 0;
}
static int vega10_populate_smc_vce_levels(struct pp_hwmgr *hwmgr)
{
struct vega10_hwmgr *data = hwmgr->backend;
PPTable_t *pp_table = &(data->smc_state_table.pp_table);
struct vega10_single_dpm_table *dpm_table = &(data->dpm_table.eclk_table);
int result = -EINVAL;
uint32_t i, j;
for (i = 0; i < dpm_table->count; i++) {
result = vega10_populate_single_eclock_level(hwmgr,
dpm_table->dpm_levels[i].value,
&(pp_table->EclkDid[i]),
&(pp_table->VceDpmVoltageIndex[i]));
if (result)
return result;
}
j = i - 1;
while (i < NUM_VCE_DPM_LEVELS) {
result = vega10_populate_single_eclock_level(hwmgr,
dpm_table->dpm_levels[j].value,
&(pp_table->EclkDid[i]),
&(pp_table->VceDpmVoltageIndex[i]));
if (result)
return result;
i++;
}
return result;
}
static int vega10_populate_single_vclock_level(struct pp_hwmgr *hwmgr,
uint32_t vclock, uint8_t *current_vclk_did)
{
struct pp_atomfwctrl_clock_dividers_soc15 dividers;
PP_ASSERT_WITH_CODE(!pp_atomfwctrl_get_gpu_pll_dividers_vega10(hwmgr,
COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
vclock, &dividers),
"Failed to get VCLK clock settings from VBIOS!",
return -EINVAL);
*current_vclk_did = (uint8_t)dividers.ulDid;
return 0;
}
static int vega10_populate_single_dclock_level(struct pp_hwmgr *hwmgr,
uint32_t dclock, uint8_t *current_dclk_did)
{
struct pp_atomfwctrl_clock_dividers_soc15 dividers;
PP_ASSERT_WITH_CODE(!pp_atomfwctrl_get_gpu_pll_dividers_vega10(hwmgr,
COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
dclock, &dividers),
"Failed to get DCLK clock settings from VBIOS!",
return -EINVAL);
*current_dclk_did = (uint8_t)dividers.ulDid;
return 0;
}
static int vega10_populate_smc_uvd_levels(struct pp_hwmgr *hwmgr)
{
struct vega10_hwmgr *data = hwmgr->backend;
PPTable_t *pp_table = &(data->smc_state_table.pp_table);
struct vega10_single_dpm_table *vclk_dpm_table =
&(data->dpm_table.vclk_table);
struct vega10_single_dpm_table *dclk_dpm_table =
&(data->dpm_table.dclk_table);
struct phm_ppt_v2_information *table_info =
(struct phm_ppt_v2_information *)(hwmgr->pptable);
struct phm_ppt_v1_mm_clock_voltage_dependency_table *dep_table =
table_info->mm_dep_table;
int result = -EINVAL;
uint32_t i, j;
for (i = 0; i < vclk_dpm_table->count; i++) {
result = vega10_populate_single_vclock_level(hwmgr,
vclk_dpm_table->dpm_levels[i].value,
&(pp_table->VclkDid[i]));
if (result)
return result;
}
j = i - 1;
while (i < NUM_UVD_DPM_LEVELS) {
result = vega10_populate_single_vclock_level(hwmgr,
vclk_dpm_table->dpm_levels[j].value,
&(pp_table->VclkDid[i]));
if (result)
return result;
i++;
}
for (i = 0; i < dclk_dpm_table->count; i++) {
result = vega10_populate_single_dclock_level(hwmgr,
dclk_dpm_table->dpm_levels[i].value,
&(pp_table->DclkDid[i]));
if (result)
return result;
}
j = i - 1;
while (i < NUM_UVD_DPM_LEVELS) {
result = vega10_populate_single_dclock_level(hwmgr,
dclk_dpm_table->dpm_levels[j].value,
&(pp_table->DclkDid[i]));
if (result)
return result;
i++;
}
for (i = 0; i < dep_table->count; i++) {
if (dep_table->entries[i].vclk ==
vclk_dpm_table->dpm_levels[i].value &&
dep_table->entries[i].dclk ==
dclk_dpm_table->dpm_levels[i].value)
pp_table->UvdDpmVoltageIndex[i] =
dep_table->entries[i].vddcInd;
else
return -1;
}
j = i - 1;
while (i < NUM_UVD_DPM_LEVELS) {
pp_table->UvdDpmVoltageIndex[i] = dep_table->entries[j].vddcInd;
i++;
}
return 0;
}
static int vega10_populate_clock_stretcher_table(struct pp_hwmgr *hwmgr)
{
struct vega10_hwmgr *data = hwmgr->backend;
PPTable_t *pp_table = &(data->smc_state_table.pp_table);
struct phm_ppt_v2_information *table_info =
(struct phm_ppt_v2_information *)(hwmgr->pptable);
struct phm_ppt_v1_clock_voltage_dependency_table *dep_table =
table_info->vdd_dep_on_sclk;
uint32_t i;
for (i = 0; i < dep_table->count; i++) {
pp_table->CksEnable[i] = dep_table->entries[i].cks_enable;
pp_table->CksVidOffset[i] = (uint8_t)(dep_table->entries[i].cks_voffset
* VOLTAGE_VID_OFFSET_SCALE2 / VOLTAGE_VID_OFFSET_SCALE1);
}
return 0;
}
static int vega10_populate_avfs_parameters(struct pp_hwmgr *hwmgr)
{
struct vega10_hwmgr *data = hwmgr->backend;
PPTable_t *pp_table = &(data->smc_state_table.pp_table);
struct phm_ppt_v2_information *table_info =
(struct phm_ppt_v2_information *)(hwmgr->pptable);
struct phm_ppt_v1_clock_voltage_dependency_table *dep_table =
table_info->vdd_dep_on_sclk;
struct pp_atomfwctrl_avfs_parameters avfs_params = {0};
int result = 0;
uint32_t i;
pp_table->MinVoltageVid = (uint8_t)0xff;
pp_table->MaxVoltageVid = (uint8_t)0;
if (data->smu_features[GNLD_AVFS].supported) {
result = pp_atomfwctrl_get_avfs_information(hwmgr, &avfs_params);
if (!result) {
pp_table->MinVoltageVid = (uint8_t)
convert_to_vid((uint16_t)(avfs_params.ulMinVddc));
pp_table->MaxVoltageVid = (uint8_t)
convert_to_vid((uint16_t)(avfs_params.ulMaxVddc));
pp_table->AConstant[0] = cpu_to_le32(avfs_params.ulMeanNsigmaAcontant0);
pp_table->AConstant[1] = cpu_to_le32(avfs_params.ulMeanNsigmaAcontant1);
pp_table->AConstant[2] = cpu_to_le32(avfs_params.ulMeanNsigmaAcontant2);
pp_table->DC_tol_sigma = cpu_to_le16(avfs_params.usMeanNsigmaDcTolSigma);
pp_table->Platform_mean = cpu_to_le16(avfs_params.usMeanNsigmaPlatformMean);
pp_table->Platform_sigma = cpu_to_le16(avfs_params.usMeanNsigmaDcTolSigma);
pp_table->PSM_Age_CompFactor = cpu_to_le16(avfs_params.usPsmAgeComfactor);
pp_table->BtcGbVdroopTableCksOff.a0 =
cpu_to_le32(avfs_params.ulGbVdroopTableCksoffA0);
pp_table->BtcGbVdroopTableCksOff.a0_shift = 20;
pp_table->BtcGbVdroopTableCksOff.a1 =
cpu_to_le32(avfs_params.ulGbVdroopTableCksoffA1);
pp_table->BtcGbVdroopTableCksOff.a1_shift = 20;
pp_table->BtcGbVdroopTableCksOff.a2 =
cpu_to_le32(avfs_params.ulGbVdroopTableCksoffA2);
pp_table->BtcGbVdroopTableCksOff.a2_shift = 20;
pp_table->OverrideBtcGbCksOn = avfs_params.ucEnableGbVdroopTableCkson;
pp_table->BtcGbVdroopTableCksOn.a0 =
cpu_to_le32(avfs_params.ulGbVdroopTableCksonA0);
pp_table->BtcGbVdroopTableCksOn.a0_shift = 20;
pp_table->BtcGbVdroopTableCksOn.a1 =
cpu_to_le32(avfs_params.ulGbVdroopTableCksonA1);
pp_table->BtcGbVdroopTableCksOn.a1_shift = 20;
pp_table->BtcGbVdroopTableCksOn.a2 =
cpu_to_le32(avfs_params.ulGbVdroopTableCksonA2);
pp_table->BtcGbVdroopTableCksOn.a2_shift = 20;
pp_table->AvfsGbCksOn.m1 =
cpu_to_le32(avfs_params.ulGbFuseTableCksonM1);
pp_table->AvfsGbCksOn.m2 =
cpu_to_le32(avfs_params.ulGbFuseTableCksonM2);
pp_table->AvfsGbCksOn.b =
cpu_to_le32(avfs_params.ulGbFuseTableCksonB);
pp_table->AvfsGbCksOn.m1_shift = 24;
pp_table->AvfsGbCksOn.m2_shift = 12;
pp_table->AvfsGbCksOn.b_shift = 0;
pp_table->OverrideAvfsGbCksOn =
avfs_params.ucEnableGbFuseTableCkson;
pp_table->AvfsGbCksOff.m1 =
cpu_to_le32(avfs_params.ulGbFuseTableCksoffM1);
pp_table->AvfsGbCksOff.m2 =
cpu_to_le32(avfs_params.ulGbFuseTableCksoffM2);
pp_table->AvfsGbCksOff.b =
cpu_to_le32(avfs_params.ulGbFuseTableCksoffB);
pp_table->AvfsGbCksOff.m1_shift = 24;
pp_table->AvfsGbCksOff.m2_shift = 12;
pp_table->AvfsGbCksOff.b_shift = 0;
for (i = 0; i < dep_table->count; i++)
pp_table->StaticVoltageOffsetVid[i] =
convert_to_vid((uint8_t)(dep_table->entries[i].sclk_offset));
if ((PPREGKEY_VEGA10QUADRATICEQUATION_DFLT !=
data->disp_clk_quad_eqn_a) &&
(PPREGKEY_VEGA10QUADRATICEQUATION_DFLT !=
data->disp_clk_quad_eqn_b)) {
pp_table->DisplayClock2Gfxclk[DSPCLK_DISPCLK].m1 =
(int32_t)data->disp_clk_quad_eqn_a;
pp_table->DisplayClock2Gfxclk[DSPCLK_DISPCLK].m2 =
(int32_t)data->disp_clk_quad_eqn_b;
pp_table->DisplayClock2Gfxclk[DSPCLK_DISPCLK].b =
(int32_t)data->disp_clk_quad_eqn_c;
} else {
pp_table->DisplayClock2Gfxclk[DSPCLK_DISPCLK].m1 =
(int32_t)avfs_params.ulDispclk2GfxclkM1;
pp_table->DisplayClock2Gfxclk[DSPCLK_DISPCLK].m2 =
(int32_t)avfs_params.ulDispclk2GfxclkM2;
pp_table->DisplayClock2Gfxclk[DSPCLK_DISPCLK].b =
(int32_t)avfs_params.ulDispclk2GfxclkB;
}
pp_table->DisplayClock2Gfxclk[DSPCLK_DISPCLK].m1_shift = 24;
pp_table->DisplayClock2Gfxclk[DSPCLK_DISPCLK].m2_shift = 12;
pp_table->DisplayClock2Gfxclk[DSPCLK_DISPCLK].b_shift = 12;
if ((PPREGKEY_VEGA10QUADRATICEQUATION_DFLT !=
data->dcef_clk_quad_eqn_a) &&
(PPREGKEY_VEGA10QUADRATICEQUATION_DFLT !=
data->dcef_clk_quad_eqn_b)) {
pp_table->DisplayClock2Gfxclk[DSPCLK_DCEFCLK].m1 =
(int32_t)data->dcef_clk_quad_eqn_a;
pp_table->DisplayClock2Gfxclk[DSPCLK_DCEFCLK].m2 =
(int32_t)data->dcef_clk_quad_eqn_b;
pp_table->DisplayClock2Gfxclk[DSPCLK_DCEFCLK].b =
(int32_t)data->dcef_clk_quad_eqn_c;
} else {
pp_table->DisplayClock2Gfxclk[DSPCLK_DCEFCLK].m1 =
(int32_t)avfs_params.ulDcefclk2GfxclkM1;
pp_table->DisplayClock2Gfxclk[DSPCLK_DCEFCLK].m2 =
(int32_t)avfs_params.ulDcefclk2GfxclkM2;
pp_table->DisplayClock2Gfxclk[DSPCLK_DCEFCLK].b =
(int32_t)avfs_params.ulDcefclk2GfxclkB;
}
pp_table->DisplayClock2Gfxclk[DSPCLK_DCEFCLK].m1_shift = 24;
pp_table->DisplayClock2Gfxclk[DSPCLK_DCEFCLK].m2_shift = 12;
pp_table->DisplayClock2Gfxclk[DSPCLK_DCEFCLK].b_shift = 12;
if ((PPREGKEY_VEGA10QUADRATICEQUATION_DFLT !=
data->pixel_clk_quad_eqn_a) &&
(PPREGKEY_VEGA10QUADRATICEQUATION_DFLT !=
data->pixel_clk_quad_eqn_b)) {
pp_table->DisplayClock2Gfxclk[DSPCLK_PIXCLK].m1 =
(int32_t)data->pixel_clk_quad_eqn_a;
pp_table->DisplayClock2Gfxclk[DSPCLK_PIXCLK].m2 =
(int32_t)data->pixel_clk_quad_eqn_b;
pp_table->DisplayClock2Gfxclk[DSPCLK_PIXCLK].b =
(int32_t)data->pixel_clk_quad_eqn_c;
} else {
pp_table->DisplayClock2Gfxclk[DSPCLK_PIXCLK].m1 =
(int32_t)avfs_params.ulPixelclk2GfxclkM1;
pp_table->DisplayClock2Gfxclk[DSPCLK_PIXCLK].m2 =
(int32_t)avfs_params.ulPixelclk2GfxclkM2;
pp_table->DisplayClock2Gfxclk[DSPCLK_PIXCLK].b =
(int32_t)avfs_params.ulPixelclk2GfxclkB;
}
pp_table->DisplayClock2Gfxclk[DSPCLK_PIXCLK].m1_shift = 24;
pp_table->DisplayClock2Gfxclk[DSPCLK_PIXCLK].m2_shift = 12;
pp_table->DisplayClock2Gfxclk[DSPCLK_PIXCLK].b_shift = 12;
if ((PPREGKEY_VEGA10QUADRATICEQUATION_DFLT !=
data->phy_clk_quad_eqn_a) &&
(PPREGKEY_VEGA10QUADRATICEQUATION_DFLT !=
data->phy_clk_quad_eqn_b)) {
pp_table->DisplayClock2Gfxclk[DSPCLK_PHYCLK].m1 =
(int32_t)data->phy_clk_quad_eqn_a;
pp_table->DisplayClock2Gfxclk[DSPCLK_PHYCLK].m2 =
(int32_t)data->phy_clk_quad_eqn_b;
pp_table->DisplayClock2Gfxclk[DSPCLK_PHYCLK].b =
(int32_t)data->phy_clk_quad_eqn_c;
} else {
pp_table->DisplayClock2Gfxclk[DSPCLK_PHYCLK].m1 =
(int32_t)avfs_params.ulPhyclk2GfxclkM1;
pp_table->DisplayClock2Gfxclk[DSPCLK_PHYCLK].m2 =
(int32_t)avfs_params.ulPhyclk2GfxclkM2;
pp_table->DisplayClock2Gfxclk[DSPCLK_PHYCLK].b =
(int32_t)avfs_params.ulPhyclk2GfxclkB;
}
pp_table->DisplayClock2Gfxclk[DSPCLK_PHYCLK].m1_shift = 24;
pp_table->DisplayClock2Gfxclk[DSPCLK_PHYCLK].m2_shift = 12;
pp_table->DisplayClock2Gfxclk[DSPCLK_PHYCLK].b_shift = 12;
pp_table->AcgBtcGbVdroopTable.a0 = avfs_params.ulAcgGbVdroopTableA0;
pp_table->AcgBtcGbVdroopTable.a0_shift = 20;
pp_table->AcgBtcGbVdroopTable.a1 = avfs_params.ulAcgGbVdroopTableA1;
pp_table->AcgBtcGbVdroopTable.a1_shift = 20;
pp_table->AcgBtcGbVdroopTable.a2 = avfs_params.ulAcgGbVdroopTableA2;
pp_table->AcgBtcGbVdroopTable.a2_shift = 20;
pp_table->AcgAvfsGb.m1 = avfs_params.ulAcgGbFuseTableM1;
pp_table->AcgAvfsGb.m2 = avfs_params.ulAcgGbFuseTableM2;
pp_table->AcgAvfsGb.b = avfs_params.ulAcgGbFuseTableB;
pp_table->AcgAvfsGb.m1_shift = 24;
pp_table->AcgAvfsGb.m2_shift = 12;
pp_table->AcgAvfsGb.b_shift = 0;
} else {
data->smu_features[GNLD_AVFS].supported = false;
}
}
return 0;
}
static int vega10_acg_enable(struct pp_hwmgr *hwmgr)
{
struct vega10_hwmgr *data = hwmgr->backend;
uint32_t agc_btc_response;
if (data->smu_features[GNLD_ACG].supported) {
if (0 == vega10_enable_smc_features(hwmgr, true,
data->smu_features[GNLD_DPM_PREFETCHER].smu_feature_bitmap))
data->smu_features[GNLD_DPM_PREFETCHER].enabled = true;
smum_send_msg_to_smc(hwmgr, PPSMC_MSG_InitializeAcg);
smum_send_msg_to_smc(hwmgr, PPSMC_MSG_RunAcgBtc);
agc_btc_response = smum_get_argument(hwmgr);
if (1 == agc_btc_response) {
if (1 == data->acg_loop_state)
smum_send_msg_to_smc(hwmgr, PPSMC_MSG_RunAcgInClosedLoop);
else if (2 == data->acg_loop_state)
smum_send_msg_to_smc(hwmgr, PPSMC_MSG_RunAcgInOpenLoop);
if (0 == vega10_enable_smc_features(hwmgr, true,
data->smu_features[GNLD_ACG].smu_feature_bitmap))
data->smu_features[GNLD_ACG].enabled = true;
} else {
pr_info("[ACG_Enable] ACG BTC Returned Failed Status!\n");
data->smu_features[GNLD_ACG].enabled = false;
}
}
return 0;
}
static int vega10_acg_disable(struct pp_hwmgr *hwmgr)
{
struct vega10_hwmgr *data = hwmgr->backend;
if (data->smu_features[GNLD_ACG].supported &&
data->smu_features[GNLD_ACG].enabled)
if (!vega10_enable_smc_features(hwmgr, false,
data->smu_features[GNLD_ACG].smu_feature_bitmap))
data->smu_features[GNLD_ACG].enabled = false;
return 0;
}
static int vega10_populate_gpio_parameters(struct pp_hwmgr *hwmgr)
{
struct vega10_hwmgr *data = hwmgr->backend;
PPTable_t *pp_table = &(data->smc_state_table.pp_table);
struct pp_atomfwctrl_gpio_parameters gpio_params = {0};
int result;
result = pp_atomfwctrl_get_gpio_information(hwmgr, &gpio_params);
if (!result) {
if (PP_CAP(PHM_PlatformCaps_RegulatorHot) &&
data->registry_data.regulator_hot_gpio_support) {
pp_table->VR0HotGpio = gpio_params.ucVR0HotGpio;
pp_table->VR0HotPolarity = gpio_params.ucVR0HotPolarity;
pp_table->VR1HotGpio = gpio_params.ucVR1HotGpio;
pp_table->VR1HotPolarity = gpio_params.ucVR1HotPolarity;
} else {
pp_table->VR0HotGpio = 0;
pp_table->VR0HotPolarity = 0;
pp_table->VR1HotGpio = 0;
pp_table->VR1HotPolarity = 0;
}
if (PP_CAP(PHM_PlatformCaps_AutomaticDCTransition) &&
data->registry_data.ac_dc_switch_gpio_support) {
pp_table->AcDcGpio = gpio_params.ucAcDcGpio;
pp_table->AcDcPolarity = gpio_params.ucAcDcPolarity;
} else {
pp_table->AcDcGpio = 0;
pp_table->AcDcPolarity = 0;
}
}
return result;
}
static int vega10_avfs_enable(struct pp_hwmgr *hwmgr, bool enable)
{
struct vega10_hwmgr *data = hwmgr->backend;
if (data->smu_features[GNLD_AVFS].supported) {
/* Already enabled or disabled */
if (!(enable ^ data->smu_features[GNLD_AVFS].enabled))
return 0;
if (enable) {
PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
true,
data->smu_features[GNLD_AVFS].smu_feature_bitmap),
"[avfs_control] Attempt to Enable AVFS feature Failed!",
return -1);
data->smu_features[GNLD_AVFS].enabled = true;
} else {
PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
false,
data->smu_features[GNLD_AVFS].smu_feature_bitmap),
"[avfs_control] Attempt to Disable AVFS feature Failed!",
return -1);
data->smu_features[GNLD_AVFS].enabled = false;
}
}
return 0;
}
static int vega10_update_avfs(struct pp_hwmgr *hwmgr)
{
struct vega10_hwmgr *data = hwmgr->backend;
if (data->need_update_dpm_table & DPMTABLE_OD_UPDATE_VDDC) {
vega10_avfs_enable(hwmgr, false);
} else if (data->need_update_dpm_table) {
vega10_avfs_enable(hwmgr, false);
vega10_avfs_enable(hwmgr, true);
} else {
vega10_avfs_enable(hwmgr, true);
}
return 0;
}
static int vega10_populate_and_upload_avfs_fuse_override(struct pp_hwmgr *hwmgr)
{
int result = 0;
uint64_t serial_number = 0;
uint32_t top32, bottom32;
struct phm_fuses_default fuse;
struct vega10_hwmgr *data = hwmgr->backend;
AvfsFuseOverride_t *avfs_fuse_table = &(data->smc_state_table.avfs_fuse_override_table);
smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ReadSerialNumTop32);
top32 = smum_get_argument(hwmgr);
smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ReadSerialNumBottom32);
bottom32 = smum_get_argument(hwmgr);
serial_number = ((uint64_t)bottom32 << 32) | top32;
if (pp_override_get_default_fuse_value(serial_number, &fuse) == 0) {
avfs_fuse_table->VFT0_b = fuse.VFT0_b;
avfs_fuse_table->VFT0_m1 = fuse.VFT0_m1;
avfs_fuse_table->VFT0_m2 = fuse.VFT0_m2;
avfs_fuse_table->VFT1_b = fuse.VFT1_b;
avfs_fuse_table->VFT1_m1 = fuse.VFT1_m1;
avfs_fuse_table->VFT1_m2 = fuse.VFT1_m2;
avfs_fuse_table->VFT2_b = fuse.VFT2_b;
avfs_fuse_table->VFT2_m1 = fuse.VFT2_m1;
avfs_fuse_table->VFT2_m2 = fuse.VFT2_m2;
result = smum_smc_table_manager(hwmgr, (uint8_t *)avfs_fuse_table,
AVFSFUSETABLE, false);
PP_ASSERT_WITH_CODE(!result,
"Failed to upload FuseOVerride!",
);
}
return result;
}
static void vega10_check_dpm_table_updated(struct pp_hwmgr *hwmgr)
{
struct vega10_hwmgr *data = hwmgr->backend;
struct vega10_odn_dpm_table *odn_table = &(data->odn_dpm_table);
struct phm_ppt_v2_information *table_info = hwmgr->pptable;
struct phm_ppt_v1_clock_voltage_dependency_table *dep_table;
struct phm_ppt_v1_clock_voltage_dependency_table *odn_dep_table;
uint32_t i;
dep_table = table_info->vdd_dep_on_mclk;
odn_dep_table = (struct phm_ppt_v1_clock_voltage_dependency_table *)&(odn_table->vdd_dep_on_mclk);
for (i = 0; i < dep_table->count; i++) {
if (dep_table->entries[i].vddc != odn_dep_table->entries[i].vddc) {
data->need_update_dpm_table |= DPMTABLE_OD_UPDATE_VDDC | DPMTABLE_OD_UPDATE_MCLK;
return;
}
}
dep_table = table_info->vdd_dep_on_sclk;
odn_dep_table = (struct phm_ppt_v1_clock_voltage_dependency_table *)&(odn_table->vdd_dep_on_sclk);
for (i = 0; i < dep_table->count; i++) {
if (dep_table->entries[i].vddc != odn_dep_table->entries[i].vddc) {
data->need_update_dpm_table |= DPMTABLE_OD_UPDATE_VDDC | DPMTABLE_OD_UPDATE_SCLK;
return;
}
}
}
/**
* Initializes the SMC table and uploads it
*
* @param hwmgr the address of the powerplay hardware manager.
* @param pInput the pointer to input data (PowerState)
* @return always 0
*/
static int vega10_init_smc_table(struct pp_hwmgr *hwmgr)
{
int result;
struct vega10_hwmgr *data = hwmgr->backend;
struct phm_ppt_v2_information *table_info =
(struct phm_ppt_v2_information *)(hwmgr->pptable);
PPTable_t *pp_table = &(data->smc_state_table.pp_table);
struct pp_atomfwctrl_voltage_table voltage_table;
struct pp_atomfwctrl_bios_boot_up_values boot_up_values;
struct vega10_odn_dpm_table *odn_table = &(data->odn_dpm_table);
result = vega10_setup_default_dpm_tables(hwmgr);
PP_ASSERT_WITH_CODE(!result,
"Failed to setup default DPM tables!",
return result);
/* initialize ODN table */
if (hwmgr->od_enabled) {
if (odn_table->max_vddc) {
data->need_update_dpm_table |= DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_OD_UPDATE_MCLK;
vega10_check_dpm_table_updated(hwmgr);
} else {
vega10_odn_initial_default_setting(hwmgr);
}
}
pp_atomfwctrl_get_voltage_table_v4(hwmgr, VOLTAGE_TYPE_VDDC,
VOLTAGE_OBJ_SVID2, &voltage_table);
pp_table->MaxVidStep = voltage_table.max_vid_step;
pp_table->GfxDpmVoltageMode =
(uint8_t)(table_info->uc_gfx_dpm_voltage_mode);
pp_table->SocDpmVoltageMode =
(uint8_t)(table_info->uc_soc_dpm_voltage_mode);
pp_table->UclkDpmVoltageMode =
(uint8_t)(table_info->uc_uclk_dpm_voltage_mode);
pp_table->UvdDpmVoltageMode =
(uint8_t)(table_info->uc_uvd_dpm_voltage_mode);
pp_table->VceDpmVoltageMode =
(uint8_t)(table_info->uc_vce_dpm_voltage_mode);
pp_table->Mp0DpmVoltageMode =
(uint8_t)(table_info->uc_mp0_dpm_voltage_mode);
pp_table->DisplayDpmVoltageMode =
(uint8_t)(table_info->uc_dcef_dpm_voltage_mode);
data->vddc_voltage_table.psi0_enable = voltage_table.psi0_enable;
data->vddc_voltage_table.psi1_enable = voltage_table.psi1_enable;
if (data->registry_data.ulv_support &&
table_info->us_ulv_voltage_offset) {
result = vega10_populate_ulv_state(hwmgr);
PP_ASSERT_WITH_CODE(!result,
"Failed to initialize ULV state!",
return result);
}
result = vega10_populate_smc_link_levels(hwmgr);
PP_ASSERT_WITH_CODE(!result,
"Failed to initialize Link Level!",
return result);
result = vega10_populate_all_graphic_levels(hwmgr);
PP_ASSERT_WITH_CODE(!result,
"Failed to initialize Graphics Level!",
return result);
result = vega10_populate_all_memory_levels(hwmgr);
PP_ASSERT_WITH_CODE(!result,
"Failed to initialize Memory Level!",
return result);
vega10_populate_vddc_soc_levels(hwmgr);
result = vega10_populate_all_display_clock_levels(hwmgr);
PP_ASSERT_WITH_CODE(!result,
"Failed to initialize Display Level!",
return result);
result = vega10_populate_smc_vce_levels(hwmgr);
PP_ASSERT_WITH_CODE(!result,
"Failed to initialize VCE Level!",
return result);
result = vega10_populate_smc_uvd_levels(hwmgr);
PP_ASSERT_WITH_CODE(!result,
"Failed to initialize UVD Level!",
return result);
if (data->registry_data.clock_stretcher_support) {
result = vega10_populate_clock_stretcher_table(hwmgr);
PP_ASSERT_WITH_CODE(!result,
"Failed to populate Clock Stretcher Table!",
return result);
}
result = pp_atomfwctrl_get_vbios_bootup_values(hwmgr, &boot_up_values);
if (!result) {
data->vbios_boot_state.vddc = boot_up_values.usVddc;
data->vbios_boot_state.vddci = boot_up_values.usVddci;
data->vbios_boot_state.mvddc = boot_up_values.usMvddc;
data->vbios_boot_state.gfx_clock = boot_up_values.ulGfxClk;
data->vbios_boot_state.mem_clock = boot_up_values.ulUClk;
pp_atomfwctrl_get_clk_information_by_clkid(hwmgr,
SMU9_SYSPLL0_SOCCLK_ID, 0, &boot_up_values.ulSocClk);
pp_atomfwctrl_get_clk_information_by_clkid(hwmgr,
SMU9_SYSPLL0_DCEFCLK_ID, 0, &boot_up_values.ulDCEFClk);
data->vbios_boot_state.soc_clock = boot_up_values.ulSocClk;
data->vbios_boot_state.dcef_clock = boot_up_values.ulDCEFClk;
if (0 != boot_up_values.usVddc) {
smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetFloorSocVoltage,
(boot_up_values.usVddc * 4));
data->vbios_boot_state.bsoc_vddc_lock = true;
} else {
data->vbios_boot_state.bsoc_vddc_lock = false;
}
smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetMinDeepSleepDcefclk,
(uint32_t)(data->vbios_boot_state.dcef_clock / 100));
}
result = vega10_populate_avfs_parameters(hwmgr);