| /* |
| * Copyright © 2008 Intel Corporation |
| * |
| * Permission is hereby granted, free of charge, to any person obtaining a |
| * copy of this software and associated documentation files (the "Software"), |
| * to deal in the Software without restriction, including without limitation |
| * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| * and/or sell copies of the Software, and to permit persons to whom the |
| * Software is furnished to do so, subject to the following conditions: |
| * |
| * The above copyright notice and this permission notice (including the next |
| * paragraph) shall be included in all copies or substantial portions of the |
| * Software. |
| * |
| * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
| * IN THE SOFTWARE. |
| * |
| * Authors: |
| * Keith Packard <keithp@keithp.com> |
| * |
| */ |
| |
| #include <linux/export.h> |
| #include <linux/i2c.h> |
| #include <linux/notifier.h> |
| #include <linux/reboot.h> |
| #include <linux/slab.h> |
| #include <linux/types.h> |
| |
| #include <asm/byteorder.h> |
| |
| #include <drm/drm_atomic_helper.h> |
| #include <drm/drm_crtc.h> |
| #include <drm/drm_dp_helper.h> |
| #include <drm/drm_edid.h> |
| #include <drm/drm_hdcp.h> |
| #include <drm/drm_probe_helper.h> |
| #include <drm/i915_drm.h> |
| |
| #include "i915_debugfs.h" |
| #include "i915_drv.h" |
| #include "i915_trace.h" |
| #include "intel_atomic.h" |
| #include "intel_audio.h" |
| #include "intel_connector.h" |
| #include "intel_ddi.h" |
| #include "intel_display_types.h" |
| #include "intel_dp.h" |
| #include "intel_dp_link_training.h" |
| #include "intel_dp_mst.h" |
| #include "intel_dpio_phy.h" |
| #include "intel_fifo_underrun.h" |
| #include "intel_hdcp.h" |
| #include "intel_hdmi.h" |
| #include "intel_hotplug.h" |
| #include "intel_lspcon.h" |
| #include "intel_lvds.h" |
| #include "intel_panel.h" |
| #include "intel_psr.h" |
| #include "intel_sideband.h" |
| #include "intel_tc.h" |
| #include "intel_vdsc.h" |
| |
| #define DP_DPRX_ESI_LEN 14 |
| |
| /* DP DSC small joiner has 2 FIFOs each of 640 x 6 bytes */ |
| #define DP_DSC_MAX_SMALL_JOINER_RAM_BUFFER 61440 |
| #define DP_DSC_MIN_SUPPORTED_BPC 8 |
| #define DP_DSC_MAX_SUPPORTED_BPC 10 |
| |
| /* DP DSC throughput values used for slice count calculations KPixels/s */ |
| #define DP_DSC_PEAK_PIXEL_RATE 2720000 |
| #define DP_DSC_MAX_ENC_THROUGHPUT_0 340000 |
| #define DP_DSC_MAX_ENC_THROUGHPUT_1 400000 |
| |
| /* DP DSC FEC Overhead factor = 1/(0.972261) */ |
| #define DP_DSC_FEC_OVERHEAD_FACTOR 972261 |
| |
| /* Compliance test status bits */ |
| #define INTEL_DP_RESOLUTION_SHIFT_MASK 0 |
| #define INTEL_DP_RESOLUTION_PREFERRED (1 << INTEL_DP_RESOLUTION_SHIFT_MASK) |
| #define INTEL_DP_RESOLUTION_STANDARD (2 << INTEL_DP_RESOLUTION_SHIFT_MASK) |
| #define INTEL_DP_RESOLUTION_FAILSAFE (3 << INTEL_DP_RESOLUTION_SHIFT_MASK) |
| |
| struct dp_link_dpll { |
| int clock; |
| struct dpll dpll; |
| }; |
| |
| static const struct dp_link_dpll g4x_dpll[] = { |
| { 162000, |
| { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } }, |
| { 270000, |
| { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } } |
| }; |
| |
| static const struct dp_link_dpll pch_dpll[] = { |
| { 162000, |
| { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } }, |
| { 270000, |
| { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } } |
| }; |
| |
| static const struct dp_link_dpll vlv_dpll[] = { |
| { 162000, |
| { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } }, |
| { 270000, |
| { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } } |
| }; |
| |
| /* |
| * CHV supports eDP 1.4 that have more link rates. |
| * Below only provides the fixed rate but exclude variable rate. |
| */ |
| static const struct dp_link_dpll chv_dpll[] = { |
| /* |
| * CHV requires to program fractional division for m2. |
| * m2 is stored in fixed point format using formula below |
| * (m2_int << 22) | m2_fraction |
| */ |
| { 162000, /* m2_int = 32, m2_fraction = 1677722 */ |
| { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } }, |
| { 270000, /* m2_int = 27, m2_fraction = 0 */ |
| { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }, |
| }; |
| |
| /* Constants for DP DSC configurations */ |
| static const u8 valid_dsc_bpp[] = {6, 8, 10, 12, 15}; |
| |
| /* With Single pipe configuration, HW is capable of supporting maximum |
| * of 4 slices per line. |
| */ |
| static const u8 valid_dsc_slicecount[] = {1, 2, 4}; |
| |
| /** |
| * intel_dp_is_edp - is the given port attached to an eDP panel (either CPU or PCH) |
| * @intel_dp: DP struct |
| * |
| * If a CPU or PCH DP output is attached to an eDP panel, this function |
| * will return true, and false otherwise. |
| */ |
| bool intel_dp_is_edp(struct intel_dp *intel_dp) |
| { |
| struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| |
| return intel_dig_port->base.type == INTEL_OUTPUT_EDP; |
| } |
| |
| static struct intel_dp *intel_attached_dp(struct drm_connector *connector) |
| { |
| return enc_to_intel_dp(&intel_attached_encoder(connector)->base); |
| } |
| |
| static void intel_dp_link_down(struct intel_encoder *encoder, |
| const struct intel_crtc_state *old_crtc_state); |
| static bool edp_panel_vdd_on(struct intel_dp *intel_dp); |
| static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync); |
| static void vlv_init_panel_power_sequencer(struct intel_encoder *encoder, |
| const struct intel_crtc_state *crtc_state); |
| static void vlv_steal_power_sequencer(struct drm_i915_private *dev_priv, |
| enum pipe pipe); |
| static void intel_dp_unset_edid(struct intel_dp *intel_dp); |
| |
| /* update sink rates from dpcd */ |
| static void intel_dp_set_sink_rates(struct intel_dp *intel_dp) |
| { |
| static const int dp_rates[] = { |
| 162000, 270000, 540000, 810000 |
| }; |
| int i, max_rate; |
| |
| max_rate = drm_dp_bw_code_to_link_rate(intel_dp->dpcd[DP_MAX_LINK_RATE]); |
| |
| for (i = 0; i < ARRAY_SIZE(dp_rates); i++) { |
| if (dp_rates[i] > max_rate) |
| break; |
| intel_dp->sink_rates[i] = dp_rates[i]; |
| } |
| |
| intel_dp->num_sink_rates = i; |
| } |
| |
| /* Get length of rates array potentially limited by max_rate. */ |
| static int intel_dp_rate_limit_len(const int *rates, int len, int max_rate) |
| { |
| int i; |
| |
| /* Limit results by potentially reduced max rate */ |
| for (i = 0; i < len; i++) { |
| if (rates[len - i - 1] <= max_rate) |
| return len - i; |
| } |
| |
| return 0; |
| } |
| |
| /* Get length of common rates array potentially limited by max_rate. */ |
| static int intel_dp_common_len_rate_limit(const struct intel_dp *intel_dp, |
| int max_rate) |
| { |
| return intel_dp_rate_limit_len(intel_dp->common_rates, |
| intel_dp->num_common_rates, max_rate); |
| } |
| |
| /* Theoretical max between source and sink */ |
| static int intel_dp_max_common_rate(struct intel_dp *intel_dp) |
| { |
| return intel_dp->common_rates[intel_dp->num_common_rates - 1]; |
| } |
| |
| /* Theoretical max between source and sink */ |
| static int intel_dp_max_common_lane_count(struct intel_dp *intel_dp) |
| { |
| struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| int source_max = intel_dig_port->max_lanes; |
| int sink_max = drm_dp_max_lane_count(intel_dp->dpcd); |
| int fia_max = intel_tc_port_fia_max_lane_count(intel_dig_port); |
| |
| return min3(source_max, sink_max, fia_max); |
| } |
| |
| int intel_dp_max_lane_count(struct intel_dp *intel_dp) |
| { |
| return intel_dp->max_link_lane_count; |
| } |
| |
| int |
| intel_dp_link_required(int pixel_clock, int bpp) |
| { |
| /* pixel_clock is in kHz, divide bpp by 8 for bit to Byte conversion */ |
| return DIV_ROUND_UP(pixel_clock * bpp, 8); |
| } |
| |
| int |
| intel_dp_max_data_rate(int max_link_clock, int max_lanes) |
| { |
| /* max_link_clock is the link symbol clock (LS_Clk) in kHz and not the |
| * link rate that is generally expressed in Gbps. Since, 8 bits of data |
| * is transmitted every LS_Clk per lane, there is no need to account for |
| * the channel encoding that is done in the PHY layer here. |
| */ |
| |
| return max_link_clock * max_lanes; |
| } |
| |
| static int |
| intel_dp_downstream_max_dotclock(struct intel_dp *intel_dp) |
| { |
| struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| struct intel_encoder *encoder = &intel_dig_port->base; |
| struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
| int max_dotclk = dev_priv->max_dotclk_freq; |
| int ds_max_dotclk; |
| |
| int type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK; |
| |
| if (type != DP_DS_PORT_TYPE_VGA) |
| return max_dotclk; |
| |
| ds_max_dotclk = drm_dp_downstream_max_clock(intel_dp->dpcd, |
| intel_dp->downstream_ports); |
| |
| if (ds_max_dotclk != 0) |
| max_dotclk = min(max_dotclk, ds_max_dotclk); |
| |
| return max_dotclk; |
| } |
| |
| static int cnl_max_source_rate(struct intel_dp *intel_dp) |
| { |
| struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
| struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); |
| enum port port = dig_port->base.port; |
| |
| u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK; |
| |
| /* Low voltage SKUs are limited to max of 5.4G */ |
| if (voltage == VOLTAGE_INFO_0_85V) |
| return 540000; |
| |
| /* For this SKU 8.1G is supported in all ports */ |
| if (IS_CNL_WITH_PORT_F(dev_priv)) |
| return 810000; |
| |
| /* For other SKUs, max rate on ports A and D is 5.4G */ |
| if (port == PORT_A || port == PORT_D) |
| return 540000; |
| |
| return 810000; |
| } |
| |
| static int icl_max_source_rate(struct intel_dp *intel_dp) |
| { |
| struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
| struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); |
| enum phy phy = intel_port_to_phy(dev_priv, dig_port->base.port); |
| |
| if (intel_phy_is_combo(dev_priv, phy) && |
| !IS_ELKHARTLAKE(dev_priv) && |
| !intel_dp_is_edp(intel_dp)) |
| return 540000; |
| |
| return 810000; |
| } |
| |
| static void |
| intel_dp_set_source_rates(struct intel_dp *intel_dp) |
| { |
| /* The values must be in increasing order */ |
| static const int cnl_rates[] = { |
| 162000, 216000, 270000, 324000, 432000, 540000, 648000, 810000 |
| }; |
| static const int bxt_rates[] = { |
| 162000, 216000, 243000, 270000, 324000, 432000, 540000 |
| }; |
| static const int skl_rates[] = { |
| 162000, 216000, 270000, 324000, 432000, 540000 |
| }; |
| static const int hsw_rates[] = { |
| 162000, 270000, 540000 |
| }; |
| static const int g4x_rates[] = { |
| 162000, 270000 |
| }; |
| struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
| struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); |
| const struct ddi_vbt_port_info *info = |
| &dev_priv->vbt.ddi_port_info[dig_port->base.port]; |
| const int *source_rates; |
| int size, max_rate = 0, vbt_max_rate = info->dp_max_link_rate; |
| |
| /* This should only be done once */ |
| WARN_ON(intel_dp->source_rates || intel_dp->num_source_rates); |
| |
| if (INTEL_GEN(dev_priv) >= 10) { |
| source_rates = cnl_rates; |
| size = ARRAY_SIZE(cnl_rates); |
| if (IS_GEN(dev_priv, 10)) |
| max_rate = cnl_max_source_rate(intel_dp); |
| else |
| max_rate = icl_max_source_rate(intel_dp); |
| } else if (IS_GEN9_LP(dev_priv)) { |
| source_rates = bxt_rates; |
| size = ARRAY_SIZE(bxt_rates); |
| } else if (IS_GEN9_BC(dev_priv)) { |
| source_rates = skl_rates; |
| size = ARRAY_SIZE(skl_rates); |
| } else if ((IS_HASWELL(dev_priv) && !IS_HSW_ULX(dev_priv)) || |
| IS_BROADWELL(dev_priv)) { |
| source_rates = hsw_rates; |
| size = ARRAY_SIZE(hsw_rates); |
| } else { |
| source_rates = g4x_rates; |
| size = ARRAY_SIZE(g4x_rates); |
| } |
| |
| if (max_rate && vbt_max_rate) |
| max_rate = min(max_rate, vbt_max_rate); |
| else if (vbt_max_rate) |
| max_rate = vbt_max_rate; |
| |
| if (max_rate) |
| size = intel_dp_rate_limit_len(source_rates, size, max_rate); |
| |
| intel_dp->source_rates = source_rates; |
| intel_dp->num_source_rates = size; |
| } |
| |
| static int intersect_rates(const int *source_rates, int source_len, |
| const int *sink_rates, int sink_len, |
| int *common_rates) |
| { |
| int i = 0, j = 0, k = 0; |
| |
| while (i < source_len && j < sink_len) { |
| if (source_rates[i] == sink_rates[j]) { |
| if (WARN_ON(k >= DP_MAX_SUPPORTED_RATES)) |
| return k; |
| common_rates[k] = source_rates[i]; |
| ++k; |
| ++i; |
| ++j; |
| } else if (source_rates[i] < sink_rates[j]) { |
| ++i; |
| } else { |
| ++j; |
| } |
| } |
| return k; |
| } |
| |
| /* return index of rate in rates array, or -1 if not found */ |
| static int intel_dp_rate_index(const int *rates, int len, int rate) |
| { |
| int i; |
| |
| for (i = 0; i < len; i++) |
| if (rate == rates[i]) |
| return i; |
| |
| return -1; |
| } |
| |
| static void intel_dp_set_common_rates(struct intel_dp *intel_dp) |
| { |
| WARN_ON(!intel_dp->num_source_rates || !intel_dp->num_sink_rates); |
| |
| intel_dp->num_common_rates = intersect_rates(intel_dp->source_rates, |
| intel_dp->num_source_rates, |
| intel_dp->sink_rates, |
| intel_dp->num_sink_rates, |
| intel_dp->common_rates); |
| |
| /* Paranoia, there should always be something in common. */ |
| if (WARN_ON(intel_dp->num_common_rates == 0)) { |
| intel_dp->common_rates[0] = 162000; |
| intel_dp->num_common_rates = 1; |
| } |
| } |
| |
| static bool intel_dp_link_params_valid(struct intel_dp *intel_dp, int link_rate, |
| u8 lane_count) |
| { |
| /* |
| * FIXME: we need to synchronize the current link parameters with |
| * hardware readout. Currently fast link training doesn't work on |
| * boot-up. |
| */ |
| if (link_rate == 0 || |
| link_rate > intel_dp->max_link_rate) |
| return false; |
| |
| if (lane_count == 0 || |
| lane_count > intel_dp_max_lane_count(intel_dp)) |
| return false; |
| |
| return true; |
| } |
| |
| static bool intel_dp_can_link_train_fallback_for_edp(struct intel_dp *intel_dp, |
| int link_rate, |
| u8 lane_count) |
| { |
| const struct drm_display_mode *fixed_mode = |
| intel_dp->attached_connector->panel.fixed_mode; |
| int mode_rate, max_rate; |
| |
| mode_rate = intel_dp_link_required(fixed_mode->clock, 18); |
| max_rate = intel_dp_max_data_rate(link_rate, lane_count); |
| if (mode_rate > max_rate) |
| return false; |
| |
| return true; |
| } |
| |
| int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp, |
| int link_rate, u8 lane_count) |
| { |
| int index; |
| |
| index = intel_dp_rate_index(intel_dp->common_rates, |
| intel_dp->num_common_rates, |
| link_rate); |
| if (index > 0) { |
| if (intel_dp_is_edp(intel_dp) && |
| !intel_dp_can_link_train_fallback_for_edp(intel_dp, |
| intel_dp->common_rates[index - 1], |
| lane_count)) { |
| DRM_DEBUG_KMS("Retrying Link training for eDP with same parameters\n"); |
| return 0; |
| } |
| intel_dp->max_link_rate = intel_dp->common_rates[index - 1]; |
| intel_dp->max_link_lane_count = lane_count; |
| } else if (lane_count > 1) { |
| if (intel_dp_is_edp(intel_dp) && |
| !intel_dp_can_link_train_fallback_for_edp(intel_dp, |
| intel_dp_max_common_rate(intel_dp), |
| lane_count >> 1)) { |
| DRM_DEBUG_KMS("Retrying Link training for eDP with same parameters\n"); |
| return 0; |
| } |
| intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp); |
| intel_dp->max_link_lane_count = lane_count >> 1; |
| } else { |
| DRM_ERROR("Link Training Unsuccessful\n"); |
| return -1; |
| } |
| |
| return 0; |
| } |
| |
| u32 intel_dp_mode_to_fec_clock(u32 mode_clock) |
| { |
| return div_u64(mul_u32_u32(mode_clock, 1000000U), |
| DP_DSC_FEC_OVERHEAD_FACTOR); |
| } |
| |
| static u16 intel_dp_dsc_get_output_bpp(u32 link_clock, u32 lane_count, |
| u32 mode_clock, u32 mode_hdisplay) |
| { |
| u32 bits_per_pixel, max_bpp_small_joiner_ram; |
| int i; |
| |
| /* |
| * Available Link Bandwidth(Kbits/sec) = (NumberOfLanes)* |
| * (LinkSymbolClock)* 8 * (TimeSlotsPerMTP) |
| * for SST -> TimeSlotsPerMTP is 1, |
| * for MST -> TimeSlotsPerMTP has to be calculated |
| */ |
| bits_per_pixel = (link_clock * lane_count * 8) / |
| intel_dp_mode_to_fec_clock(mode_clock); |
| DRM_DEBUG_KMS("Max link bpp: %u\n", bits_per_pixel); |
| |
| /* Small Joiner Check: output bpp <= joiner RAM (bits) / Horiz. width */ |
| max_bpp_small_joiner_ram = DP_DSC_MAX_SMALL_JOINER_RAM_BUFFER / mode_hdisplay; |
| DRM_DEBUG_KMS("Max small joiner bpp: %u\n", max_bpp_small_joiner_ram); |
| |
| /* |
| * Greatest allowed DSC BPP = MIN (output BPP from available Link BW |
| * check, output bpp from small joiner RAM check) |
| */ |
| bits_per_pixel = min(bits_per_pixel, max_bpp_small_joiner_ram); |
| |
| /* Error out if the max bpp is less than smallest allowed valid bpp */ |
| if (bits_per_pixel < valid_dsc_bpp[0]) { |
| DRM_DEBUG_KMS("Unsupported BPP %u, min %u\n", |
| bits_per_pixel, valid_dsc_bpp[0]); |
| return 0; |
| } |
| |
| /* Find the nearest match in the array of known BPPs from VESA */ |
| for (i = 0; i < ARRAY_SIZE(valid_dsc_bpp) - 1; i++) { |
| if (bits_per_pixel < valid_dsc_bpp[i + 1]) |
| break; |
| } |
| bits_per_pixel = valid_dsc_bpp[i]; |
| |
| /* |
| * Compressed BPP in U6.4 format so multiply by 16, for Gen 11, |
| * fractional part is 0 |
| */ |
| return bits_per_pixel << 4; |
| } |
| |
| static u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp, |
| int mode_clock, int mode_hdisplay) |
| { |
| u8 min_slice_count, i; |
| int max_slice_width; |
| |
| if (mode_clock <= DP_DSC_PEAK_PIXEL_RATE) |
| min_slice_count = DIV_ROUND_UP(mode_clock, |
| DP_DSC_MAX_ENC_THROUGHPUT_0); |
| else |
| min_slice_count = DIV_ROUND_UP(mode_clock, |
| DP_DSC_MAX_ENC_THROUGHPUT_1); |
| |
| max_slice_width = drm_dp_dsc_sink_max_slice_width(intel_dp->dsc_dpcd); |
| if (max_slice_width < DP_DSC_MIN_SLICE_WIDTH_VALUE) { |
| DRM_DEBUG_KMS("Unsupported slice width %d by DP DSC Sink device\n", |
| max_slice_width); |
| return 0; |
| } |
| /* Also take into account max slice width */ |
| min_slice_count = min_t(u8, min_slice_count, |
| DIV_ROUND_UP(mode_hdisplay, |
| max_slice_width)); |
| |
| /* Find the closest match to the valid slice count values */ |
| for (i = 0; i < ARRAY_SIZE(valid_dsc_slicecount); i++) { |
| if (valid_dsc_slicecount[i] > |
| drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd, |
| false)) |
| break; |
| if (min_slice_count <= valid_dsc_slicecount[i]) |
| return valid_dsc_slicecount[i]; |
| } |
| |
| DRM_DEBUG_KMS("Unsupported Slice Count %d\n", min_slice_count); |
| return 0; |
| } |
| |
| static enum drm_mode_status |
| intel_dp_mode_valid(struct drm_connector *connector, |
| struct drm_display_mode *mode) |
| { |
| struct intel_dp *intel_dp = intel_attached_dp(connector); |
| struct intel_connector *intel_connector = to_intel_connector(connector); |
| struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode; |
| struct drm_i915_private *dev_priv = to_i915(connector->dev); |
| int target_clock = mode->clock; |
| int max_rate, mode_rate, max_lanes, max_link_clock; |
| int max_dotclk; |
| u16 dsc_max_output_bpp = 0; |
| u8 dsc_slice_count = 0; |
| |
| if (mode->flags & DRM_MODE_FLAG_DBLSCAN) |
| return MODE_NO_DBLESCAN; |
| |
| max_dotclk = intel_dp_downstream_max_dotclock(intel_dp); |
| |
| if (intel_dp_is_edp(intel_dp) && fixed_mode) { |
| if (mode->hdisplay > fixed_mode->hdisplay) |
| return MODE_PANEL; |
| |
| if (mode->vdisplay > fixed_mode->vdisplay) |
| return MODE_PANEL; |
| |
| target_clock = fixed_mode->clock; |
| } |
| |
| max_link_clock = intel_dp_max_link_rate(intel_dp); |
| max_lanes = intel_dp_max_lane_count(intel_dp); |
| |
| max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes); |
| mode_rate = intel_dp_link_required(target_clock, 18); |
| |
| /* |
| * Output bpp is stored in 6.4 format so right shift by 4 to get the |
| * integer value since we support only integer values of bpp. |
| */ |
| if ((INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) && |
| drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd)) { |
| if (intel_dp_is_edp(intel_dp)) { |
| dsc_max_output_bpp = |
| drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd) >> 4; |
| dsc_slice_count = |
| drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd, |
| true); |
| } else if (drm_dp_sink_supports_fec(intel_dp->fec_capable)) { |
| dsc_max_output_bpp = |
| intel_dp_dsc_get_output_bpp(max_link_clock, |
| max_lanes, |
| target_clock, |
| mode->hdisplay) >> 4; |
| dsc_slice_count = |
| intel_dp_dsc_get_slice_count(intel_dp, |
| target_clock, |
| mode->hdisplay); |
| } |
| } |
| |
| if ((mode_rate > max_rate && !(dsc_max_output_bpp && dsc_slice_count)) || |
| target_clock > max_dotclk) |
| return MODE_CLOCK_HIGH; |
| |
| if (mode->clock < 10000) |
| return MODE_CLOCK_LOW; |
| |
| if (mode->flags & DRM_MODE_FLAG_DBLCLK) |
| return MODE_H_ILLEGAL; |
| |
| return MODE_OK; |
| } |
| |
| u32 intel_dp_pack_aux(const u8 *src, int src_bytes) |
| { |
| int i; |
| u32 v = 0; |
| |
| if (src_bytes > 4) |
| src_bytes = 4; |
| for (i = 0; i < src_bytes; i++) |
| v |= ((u32)src[i]) << ((3 - i) * 8); |
| return v; |
| } |
| |
| static void intel_dp_unpack_aux(u32 src, u8 *dst, int dst_bytes) |
| { |
| int i; |
| if (dst_bytes > 4) |
| dst_bytes = 4; |
| for (i = 0; i < dst_bytes; i++) |
| dst[i] = src >> ((3-i) * 8); |
| } |
| |
| static void |
| intel_dp_init_panel_power_sequencer(struct intel_dp *intel_dp); |
| static void |
| intel_dp_init_panel_power_sequencer_registers(struct intel_dp *intel_dp, |
| bool force_disable_vdd); |
| static void |
| intel_dp_pps_init(struct intel_dp *intel_dp); |
| |
| static intel_wakeref_t |
| pps_lock(struct intel_dp *intel_dp) |
| { |
| struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
| intel_wakeref_t wakeref; |
| |
| /* |
| * See intel_power_sequencer_reset() why we need |
| * a power domain reference here. |
| */ |
| wakeref = intel_display_power_get(dev_priv, |
| intel_aux_power_domain(dp_to_dig_port(intel_dp))); |
| |
| mutex_lock(&dev_priv->pps_mutex); |
| |
| return wakeref; |
| } |
| |
| static intel_wakeref_t |
| pps_unlock(struct intel_dp *intel_dp, intel_wakeref_t wakeref) |
| { |
| struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
| |
| mutex_unlock(&dev_priv->pps_mutex); |
| intel_display_power_put(dev_priv, |
| intel_aux_power_domain(dp_to_dig_port(intel_dp)), |
| wakeref); |
| return 0; |
| } |
| |
| #define with_pps_lock(dp, wf) \ |
| for ((wf) = pps_lock(dp); (wf); (wf) = pps_unlock((dp), (wf))) |
| |
| static void |
| vlv_power_sequencer_kick(struct intel_dp *intel_dp) |
| { |
| struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
| struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| enum pipe pipe = intel_dp->pps_pipe; |
| bool pll_enabled, release_cl_override = false; |
| enum dpio_phy phy = DPIO_PHY(pipe); |
| enum dpio_channel ch = vlv_pipe_to_channel(pipe); |
| u32 DP; |
| |
| if (WARN(I915_READ(intel_dp->output_reg) & DP_PORT_EN, |
| "skipping pipe %c power sequencer kick due to port %c being active\n", |
| pipe_name(pipe), port_name(intel_dig_port->base.port))) |
| return; |
| |
| DRM_DEBUG_KMS("kicking pipe %c power sequencer for port %c\n", |
| pipe_name(pipe), port_name(intel_dig_port->base.port)); |
| |
| /* Preserve the BIOS-computed detected bit. This is |
| * supposed to be read-only. |
| */ |
| DP = I915_READ(intel_dp->output_reg) & DP_DETECTED; |
| DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0; |
| DP |= DP_PORT_WIDTH(1); |
| DP |= DP_LINK_TRAIN_PAT_1; |
| |
| if (IS_CHERRYVIEW(dev_priv)) |
| DP |= DP_PIPE_SEL_CHV(pipe); |
| else |
| DP |= DP_PIPE_SEL(pipe); |
| |
| pll_enabled = I915_READ(DPLL(pipe)) & DPLL_VCO_ENABLE; |
| |
| /* |
| * The DPLL for the pipe must be enabled for this to work. |
| * So enable temporarily it if it's not already enabled. |
| */ |
| if (!pll_enabled) { |
| release_cl_override = IS_CHERRYVIEW(dev_priv) && |
| !chv_phy_powergate_ch(dev_priv, phy, ch, true); |
| |
| if (vlv_force_pll_on(dev_priv, pipe, IS_CHERRYVIEW(dev_priv) ? |
| &chv_dpll[0].dpll : &vlv_dpll[0].dpll)) { |
| DRM_ERROR("Failed to force on pll for pipe %c!\n", |
| pipe_name(pipe)); |
| return; |
| } |
| } |
| |
| /* |
| * Similar magic as in intel_dp_enable_port(). |
| * We _must_ do this port enable + disable trick |
| * to make this power sequencer lock onto the port. |
| * Otherwise even VDD force bit won't work. |
| */ |
| I915_WRITE(intel_dp->output_reg, DP); |
| POSTING_READ(intel_dp->output_reg); |
| |
| I915_WRITE(intel_dp->output_reg, DP | DP_PORT_EN); |
| POSTING_READ(intel_dp->output_reg); |
| |
| I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN); |
| POSTING_READ(intel_dp->output_reg); |
| |
| if (!pll_enabled) { |
| vlv_force_pll_off(dev_priv, pipe); |
| |
| if (release_cl_override) |
| chv_phy_powergate_ch(dev_priv, phy, ch, false); |
| } |
| } |
| |
| static enum pipe vlv_find_free_pps(struct drm_i915_private *dev_priv) |
| { |
| struct intel_encoder *encoder; |
| unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B); |
| |
| /* |
| * We don't have power sequencer currently. |
| * Pick one that's not used by other ports. |
| */ |
| for_each_intel_dp(&dev_priv->drm, encoder) { |
| struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
| |
| if (encoder->type == INTEL_OUTPUT_EDP) { |
| WARN_ON(intel_dp->active_pipe != INVALID_PIPE && |
| intel_dp->active_pipe != intel_dp->pps_pipe); |
| |
| if (intel_dp->pps_pipe != INVALID_PIPE) |
| pipes &= ~(1 << intel_dp->pps_pipe); |
| } else { |
| WARN_ON(intel_dp->pps_pipe != INVALID_PIPE); |
| |
| if (intel_dp->active_pipe != INVALID_PIPE) |
| pipes &= ~(1 << intel_dp->active_pipe); |
| } |
| } |
| |
| if (pipes == 0) |
| return INVALID_PIPE; |
| |
| return ffs(pipes) - 1; |
| } |
| |
| static enum pipe |
| vlv_power_sequencer_pipe(struct intel_dp *intel_dp) |
| { |
| struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
| struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| enum pipe pipe; |
| |
| lockdep_assert_held(&dev_priv->pps_mutex); |
| |
| /* We should never land here with regular DP ports */ |
| WARN_ON(!intel_dp_is_edp(intel_dp)); |
| |
| WARN_ON(intel_dp->active_pipe != INVALID_PIPE && |
| intel_dp->active_pipe != intel_dp->pps_pipe); |
| |
| if (intel_dp->pps_pipe != INVALID_PIPE) |
| return intel_dp->pps_pipe; |
| |
| pipe = vlv_find_free_pps(dev_priv); |
| |
| /* |
| * Didn't find one. This should not happen since there |
| * are two power sequencers and up to two eDP ports. |
| */ |
| if (WARN_ON(pipe == INVALID_PIPE)) |
| pipe = PIPE_A; |
| |
| vlv_steal_power_sequencer(dev_priv, pipe); |
| intel_dp->pps_pipe = pipe; |
| |
| DRM_DEBUG_KMS("picked pipe %c power sequencer for port %c\n", |
| pipe_name(intel_dp->pps_pipe), |
| port_name(intel_dig_port->base.port)); |
| |
| /* init power sequencer on this pipe and port */ |
| intel_dp_init_panel_power_sequencer(intel_dp); |
| intel_dp_init_panel_power_sequencer_registers(intel_dp, true); |
| |
| /* |
| * Even vdd force doesn't work until we've made |
| * the power sequencer lock in on the port. |
| */ |
| vlv_power_sequencer_kick(intel_dp); |
| |
| return intel_dp->pps_pipe; |
| } |
| |
| static int |
| bxt_power_sequencer_idx(struct intel_dp *intel_dp) |
| { |
| struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
| int backlight_controller = dev_priv->vbt.backlight.controller; |
| |
| lockdep_assert_held(&dev_priv->pps_mutex); |
| |
| /* We should never land here with regular DP ports */ |
| WARN_ON(!intel_dp_is_edp(intel_dp)); |
| |
| if (!intel_dp->pps_reset) |
| return backlight_controller; |
| |
| intel_dp->pps_reset = false; |
| |
| /* |
| * Only the HW needs to be reprogrammed, the SW state is fixed and |
| * has been setup during connector init. |
| */ |
| intel_dp_init_panel_power_sequencer_registers(intel_dp, false); |
| |
| return backlight_controller; |
| } |
| |
| typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv, |
| enum pipe pipe); |
| |
| static bool vlv_pipe_has_pp_on(struct drm_i915_private *dev_priv, |
| enum pipe pipe) |
| { |
| return I915_READ(PP_STATUS(pipe)) & PP_ON; |
| } |
| |
| static bool vlv_pipe_has_vdd_on(struct drm_i915_private *dev_priv, |
| enum pipe pipe) |
| { |
| return I915_READ(PP_CONTROL(pipe)) & EDP_FORCE_VDD; |
| } |
| |
| static bool vlv_pipe_any(struct drm_i915_private *dev_priv, |
| enum pipe pipe) |
| { |
| return true; |
| } |
| |
| static enum pipe |
| vlv_initial_pps_pipe(struct drm_i915_private *dev_priv, |
| enum port port, |
| vlv_pipe_check pipe_check) |
| { |
| enum pipe pipe; |
| |
| for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) { |
| u32 port_sel = I915_READ(PP_ON_DELAYS(pipe)) & |
| PANEL_PORT_SELECT_MASK; |
| |
| if (port_sel != PANEL_PORT_SELECT_VLV(port)) |
| continue; |
| |
| if (!pipe_check(dev_priv, pipe)) |
| continue; |
| |
| return pipe; |
| } |
| |
| return INVALID_PIPE; |
| } |
| |
| static void |
| vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp) |
| { |
| struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
| struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| enum port port = intel_dig_port->base.port; |
| |
| lockdep_assert_held(&dev_priv->pps_mutex); |
| |
| /* try to find a pipe with this port selected */ |
| /* first pick one where the panel is on */ |
| intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port, |
| vlv_pipe_has_pp_on); |
| /* didn't find one? pick one where vdd is on */ |
| if (intel_dp->pps_pipe == INVALID_PIPE) |
| intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port, |
| vlv_pipe_has_vdd_on); |
| /* didn't find one? pick one with just the correct port */ |
| if (intel_dp->pps_pipe == INVALID_PIPE) |
| intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port, |
| vlv_pipe_any); |
| |
| /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */ |
| if (intel_dp->pps_pipe == INVALID_PIPE) { |
| DRM_DEBUG_KMS("no initial power sequencer for port %c\n", |
| port_name(port)); |
| return; |
| } |
| |
| DRM_DEBUG_KMS("initial power sequencer for port %c: pipe %c\n", |
| port_name(port), pipe_name(intel_dp->pps_pipe)); |
| |
| intel_dp_init_panel_power_sequencer(intel_dp); |
| intel_dp_init_panel_power_sequencer_registers(intel_dp, false); |
| } |
| |
| void intel_power_sequencer_reset(struct drm_i915_private *dev_priv) |
| { |
| struct intel_encoder *encoder; |
| |
| if (WARN_ON(!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) && |
| !IS_GEN9_LP(dev_priv))) |
| return; |
| |
| /* |
| * We can't grab pps_mutex here due to deadlock with power_domain |
| * mutex when power_domain functions are called while holding pps_mutex. |
| * That also means that in order to use pps_pipe the code needs to |
| * hold both a power domain reference and pps_mutex, and the power domain |
| * reference get/put must be done while _not_ holding pps_mutex. |
| * pps_{lock,unlock}() do these steps in the correct order, so one |
| * should use them always. |
| */ |
| |
| for_each_intel_dp(&dev_priv->drm, encoder) { |
| struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
| |
| WARN_ON(intel_dp->active_pipe != INVALID_PIPE); |
| |
| if (encoder->type != INTEL_OUTPUT_EDP) |
| continue; |
| |
| if (IS_GEN9_LP(dev_priv)) |
| intel_dp->pps_reset = true; |
| else |
| intel_dp->pps_pipe = INVALID_PIPE; |
| } |
| } |
| |
| struct pps_registers { |
| i915_reg_t pp_ctrl; |
| i915_reg_t pp_stat; |
| i915_reg_t pp_on; |
| i915_reg_t pp_off; |
| i915_reg_t pp_div; |
| }; |
| |
| static void intel_pps_get_registers(struct intel_dp *intel_dp, |
| struct pps_registers *regs) |
| { |
| struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
| int pps_idx = 0; |
| |
| memset(regs, 0, sizeof(*regs)); |
| |
| if (IS_GEN9_LP(dev_priv)) |
| pps_idx = bxt_power_sequencer_idx(intel_dp); |
| else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
| pps_idx = vlv_power_sequencer_pipe(intel_dp); |
| |
| regs->pp_ctrl = PP_CONTROL(pps_idx); |
| regs->pp_stat = PP_STATUS(pps_idx); |
| regs->pp_on = PP_ON_DELAYS(pps_idx); |
| regs->pp_off = PP_OFF_DELAYS(pps_idx); |
| |
| /* Cycle delay moved from PP_DIVISOR to PP_CONTROL */ |
| if (IS_GEN9_LP(dev_priv) || INTEL_PCH_TYPE(dev_priv) >= PCH_CNP) |
| regs->pp_div = INVALID_MMIO_REG; |
| else |
| regs->pp_div = PP_DIVISOR(pps_idx); |
| } |
| |
| static i915_reg_t |
| _pp_ctrl_reg(struct intel_dp *intel_dp) |
| { |
| struct pps_registers regs; |
| |
| intel_pps_get_registers(intel_dp, ®s); |
| |
| return regs.pp_ctrl; |
| } |
| |
| static i915_reg_t |
| _pp_stat_reg(struct intel_dp *intel_dp) |
| { |
| struct pps_registers regs; |
| |
| intel_pps_get_registers(intel_dp, ®s); |
| |
| return regs.pp_stat; |
| } |
| |
| /* Reboot notifier handler to shutdown panel power to guarantee T12 timing |
| This function only applicable when panel PM state is not to be tracked */ |
| static int edp_notify_handler(struct notifier_block *this, unsigned long code, |
| void *unused) |
| { |
| struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp), |
| edp_notifier); |
| struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
| intel_wakeref_t wakeref; |
| |
| if (!intel_dp_is_edp(intel_dp) || code != SYS_RESTART) |
| return 0; |
| |
| with_pps_lock(intel_dp, wakeref) { |
| if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
| enum pipe pipe = vlv_power_sequencer_pipe(intel_dp); |
| i915_reg_t pp_ctrl_reg, pp_div_reg; |
| u32 pp_div; |
| |
| pp_ctrl_reg = PP_CONTROL(pipe); |
| pp_div_reg = PP_DIVISOR(pipe); |
| pp_div = I915_READ(pp_div_reg); |
| pp_div &= PP_REFERENCE_DIVIDER_MASK; |
| |
| /* 0x1F write to PP_DIV_REG sets max cycle delay */ |
| I915_WRITE(pp_div_reg, pp_div | 0x1F); |
| I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS); |
| msleep(intel_dp->panel_power_cycle_delay); |
| } |
| } |
| |
| return 0; |
| } |
| |
| static bool edp_have_panel_power(struct intel_dp *intel_dp) |
| { |
| struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
| |
| lockdep_assert_held(&dev_priv->pps_mutex); |
| |
| if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && |
| intel_dp->pps_pipe == INVALID_PIPE) |
| return false; |
| |
| return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0; |
| } |
| |
| static bool edp_have_panel_vdd(struct intel_dp *intel_dp) |
| { |
| struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
| |
| lockdep_assert_held(&dev_priv->pps_mutex); |
| |
| if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && |
| intel_dp->pps_pipe == INVALID_PIPE) |
| return false; |
| |
| return I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD; |
| } |
| |
| static void |
| intel_dp_check_edp(struct intel_dp *intel_dp) |
| { |
| struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
| |
| if (!intel_dp_is_edp(intel_dp)) |
| return; |
| |
| if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) { |
| WARN(1, "eDP powered off while attempting aux channel communication.\n"); |
| DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n", |
| I915_READ(_pp_stat_reg(intel_dp)), |
| I915_READ(_pp_ctrl_reg(intel_dp))); |
| } |
| } |
| |
| static u32 |
| intel_dp_aux_wait_done(struct intel_dp *intel_dp) |
| { |
| struct drm_i915_private *i915 = dp_to_i915(intel_dp); |
| i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg(intel_dp); |
| u32 status; |
| bool done; |
| |
| #define C (((status = intel_uncore_read_notrace(&i915->uncore, ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0) |
| done = wait_event_timeout(i915->gmbus_wait_queue, C, |
| msecs_to_jiffies_timeout(10)); |
| |
| /* just trace the final value */ |
| trace_i915_reg_rw(false, ch_ctl, status, sizeof(status), true); |
| |
| if (!done) |
| DRM_ERROR("dp aux hw did not signal timeout!\n"); |
| #undef C |
| |
| return status; |
| } |
| |
| static u32 g4x_get_aux_clock_divider(struct intel_dp *intel_dp, int index) |
| { |
| struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
| |
| if (index) |
| return 0; |
| |
| /* |
| * The clock divider is based off the hrawclk, and would like to run at |
| * 2MHz. So, take the hrawclk value and divide by 2000 and use that |
| */ |
| return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000); |
| } |
| |
| static u32 ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index) |
| { |
| struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
| struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
| |
| if (index) |
| return 0; |
| |
| /* |
| * The clock divider is based off the cdclk or PCH rawclk, and would |
| * like to run at 2MHz. So, take the cdclk or PCH rawclk value and |
| * divide by 2000 and use that |
| */ |
| if (dig_port->aux_ch == AUX_CH_A) |
| return DIV_ROUND_CLOSEST(dev_priv->cdclk.hw.cdclk, 2000); |
| else |
| return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000); |
| } |
| |
| static u32 hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index) |
| { |
| struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
| struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
| |
| if (dig_port->aux_ch != AUX_CH_A && HAS_PCH_LPT_H(dev_priv)) { |
| /* Workaround for non-ULT HSW */ |
| switch (index) { |
| case 0: return 63; |
| case 1: return 72; |
| default: return 0; |
| } |
| } |
| |
| return ilk_get_aux_clock_divider(intel_dp, index); |
| } |
| |
| static u32 skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index) |
| { |
| /* |
| * SKL doesn't need us to program the AUX clock divider (Hardware will |
| * derive the clock from CDCLK automatically). We still implement the |
| * get_aux_clock_divider vfunc to plug-in into the existing code. |
| */ |
| return index ? 0 : 1; |
| } |
| |
| static u32 g4x_get_aux_send_ctl(struct intel_dp *intel_dp, |
| int send_bytes, |
| u32 aux_clock_divider) |
| { |
| struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| struct drm_i915_private *dev_priv = |
| to_i915(intel_dig_port->base.base.dev); |
| u32 precharge, timeout; |
| |
| if (IS_GEN(dev_priv, 6)) |
| precharge = 3; |
| else |
| precharge = 5; |
| |
| if (IS_BROADWELL(dev_priv)) |
| timeout = DP_AUX_CH_CTL_TIME_OUT_600us; |
| else |
| timeout = DP_AUX_CH_CTL_TIME_OUT_400us; |
| |
| return DP_AUX_CH_CTL_SEND_BUSY | |
| DP_AUX_CH_CTL_DONE | |
| DP_AUX_CH_CTL_INTERRUPT | |
| DP_AUX_CH_CTL_TIME_OUT_ERROR | |
| timeout | |
| DP_AUX_CH_CTL_RECEIVE_ERROR | |
| (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) | |
| (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) | |
| (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT); |
| } |
| |
| static u32 skl_get_aux_send_ctl(struct intel_dp *intel_dp, |
| int send_bytes, |
| u32 unused) |
| { |
| struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| struct drm_i915_private *i915 = |
| to_i915(intel_dig_port->base.base.dev); |
| enum phy phy = intel_port_to_phy(i915, intel_dig_port->base.port); |
| u32 ret; |
| |
| ret = DP_AUX_CH_CTL_SEND_BUSY | |
| DP_AUX_CH_CTL_DONE | |
| DP_AUX_CH_CTL_INTERRUPT | |
| DP_AUX_CH_CTL_TIME_OUT_ERROR | |
| DP_AUX_CH_CTL_TIME_OUT_MAX | |
| DP_AUX_CH_CTL_RECEIVE_ERROR | |
| (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) | |
| DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(32) | |
| DP_AUX_CH_CTL_SYNC_PULSE_SKL(32); |
| |
| if (intel_phy_is_tc(i915, phy) && |
| intel_dig_port->tc_mode == TC_PORT_TBT_ALT) |
| ret |= DP_AUX_CH_CTL_TBT_IO; |
| |
| return ret; |
| } |
| |
| static int |
| intel_dp_aux_xfer(struct intel_dp *intel_dp, |
| const u8 *send, int send_bytes, |
| u8 *recv, int recv_size, |
| u32 aux_send_ctl_flags) |
| { |
| struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| struct drm_i915_private *i915 = |
| to_i915(intel_dig_port->base.base.dev); |
| struct intel_uncore *uncore = &i915->uncore; |
| enum phy phy = intel_port_to_phy(i915, intel_dig_port->base.port); |
| bool is_tc_port = intel_phy_is_tc(i915, phy); |
| i915_reg_t ch_ctl, ch_data[5]; |
| u32 aux_clock_divider; |
| enum intel_display_power_domain aux_domain = |
| intel_aux_power_domain(intel_dig_port); |
| intel_wakeref_t aux_wakeref; |
| intel_wakeref_t pps_wakeref; |
| int i, ret, recv_bytes; |
| int try, clock = 0; |
| u32 status; |
| bool vdd; |
| |
| ch_ctl = intel_dp->aux_ch_ctl_reg(intel_dp); |
| for (i = 0; i < ARRAY_SIZE(ch_data); i++) |
| ch_data[i] = intel_dp->aux_ch_data_reg(intel_dp, i); |
| |
| if (is_tc_port) |
| intel_tc_port_lock(intel_dig_port); |
| |
| aux_wakeref = intel_display_power_get(i915, aux_domain); |
| pps_wakeref = pps_lock(intel_dp); |
| |
| /* |
| * We will be called with VDD already enabled for dpcd/edid/oui reads. |
| * In such cases we want to leave VDD enabled and it's up to upper layers |
| * to turn it off. But for eg. i2c-dev access we need to turn it on/off |
| * ourselves. |
| */ |
| vdd = edp_panel_vdd_on(intel_dp); |
| |
| /* dp aux is extremely sensitive to irq latency, hence request the |
| * lowest possible wakeup latency and so prevent the cpu from going into |
| * deep sleep states. |
| */ |
| pm_qos_update_request(&i915->pm_qos, 0); |
| |
| intel_dp_check_edp(intel_dp); |
| |
| /* Try to wait for any previous AUX channel activity */ |
| for (try = 0; try < 3; try++) { |
| status = intel_uncore_read_notrace(uncore, ch_ctl); |
| if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0) |
| break; |
| msleep(1); |
| } |
| /* just trace the final value */ |
| trace_i915_reg_rw(false, ch_ctl, status, sizeof(status), true); |
| |
| if (try == 3) { |
| static u32 last_status = -1; |
| const u32 status = intel_uncore_read(uncore, ch_ctl); |
| |
| if (status != last_status) { |
| WARN(1, "dp_aux_ch not started status 0x%08x\n", |
| status); |
| last_status = status; |
| } |
| |
| ret = -EBUSY; |
| goto out; |
| } |
| |
| /* Only 5 data registers! */ |
| if (WARN_ON(send_bytes > 20 || recv_size > 20)) { |
| ret = -E2BIG; |
| goto out; |
| } |
| |
| while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) { |
| u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp, |
| send_bytes, |
| aux_clock_divider); |
| |
| send_ctl |= aux_send_ctl_flags; |
| |
| /* Must try at least 3 times according to DP spec */ |
| for (try = 0; try < 5; try++) { |
| /* Load the send data into the aux channel data registers */ |
| for (i = 0; i < send_bytes; i += 4) |
| intel_uncore_write(uncore, |
| ch_data[i >> 2], |
| intel_dp_pack_aux(send + i, |
| send_bytes - i)); |
| |
| /* Send the command and wait for it to complete */ |
| intel_uncore_write(uncore, ch_ctl, send_ctl); |
| |
| status = intel_dp_aux_wait_done(intel_dp); |
| |
| /* Clear done status and any errors */ |
| intel_uncore_write(uncore, |
| ch_ctl, |
| status | |
| DP_AUX_CH_CTL_DONE | |
| DP_AUX_CH_CTL_TIME_OUT_ERROR | |
| DP_AUX_CH_CTL_RECEIVE_ERROR); |
| |
| /* DP CTS 1.2 Core Rev 1.1, 4.2.1.1 & 4.2.1.2 |
| * 400us delay required for errors and timeouts |
| * Timeout errors from the HW already meet this |
| * requirement so skip to next iteration |
| */ |
| if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) |
| continue; |
| |
| if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) { |
| usleep_range(400, 500); |
| continue; |
| } |
| if (status & DP_AUX_CH_CTL_DONE) |
| goto done; |
| } |
| } |
| |
| if ((status & DP_AUX_CH_CTL_DONE) == 0) { |
| DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status); |
| ret = -EBUSY; |
| goto out; |
| } |
| |
| done: |
| /* Check for timeout or receive error. |
| * Timeouts occur when the sink is not connected |
| */ |
| if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) { |
| DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status); |
| ret = -EIO; |
| goto out; |
| } |
| |
| /* Timeouts occur when the device isn't connected, so they're |
| * "normal" -- don't fill the kernel log with these */ |
| if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) { |
| DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status); |
| ret = -ETIMEDOUT; |
| goto out; |
| } |
| |
| /* Unload any bytes sent back from the other side */ |
| recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >> |
| DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT); |
| |
| /* |
| * By BSpec: "Message sizes of 0 or >20 are not allowed." |
| * We have no idea of what happened so we return -EBUSY so |
| * drm layer takes care for the necessary retries. |
| */ |
| if (recv_bytes == 0 || recv_bytes > 20) { |
| DRM_DEBUG_KMS("Forbidden recv_bytes = %d on aux transaction\n", |
| recv_bytes); |
| ret = -EBUSY; |
| goto out; |
| } |
| |
| if (recv_bytes > recv_size) |
| recv_bytes = recv_size; |
| |
| for (i = 0; i < recv_bytes; i += 4) |
| intel_dp_unpack_aux(intel_uncore_read(uncore, ch_data[i >> 2]), |
| recv + i, recv_bytes - i); |
| |
| ret = recv_bytes; |
| out: |
| pm_qos_update_request(&i915->pm_qos, PM_QOS_DEFAULT_VALUE); |
| |
| if (vdd) |
| edp_panel_vdd_off(intel_dp, false); |
| |
| pps_unlock(intel_dp, pps_wakeref); |
| intel_display_power_put_async(i915, aux_domain, aux_wakeref); |
| |
| if (is_tc_port) |
| intel_tc_port_unlock(intel_dig_port); |
| |
| return ret; |
| } |
| |
| #define BARE_ADDRESS_SIZE 3 |
| #define HEADER_SIZE (BARE_ADDRESS_SIZE + 1) |
| |
| static void |
| intel_dp_aux_header(u8 txbuf[HEADER_SIZE], |
| const struct drm_dp_aux_msg *msg) |
| { |
| txbuf[0] = (msg->request << 4) | ((msg->address >> 16) & 0xf); |
| txbuf[1] = (msg->address >> 8) & 0xff; |
| txbuf[2] = msg->address & 0xff; |
| txbuf[3] = msg->size - 1; |
| } |
| |
| static ssize_t |
| intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg) |
| { |
| struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux); |
| u8 txbuf[20], rxbuf[20]; |
| size_t txsize, rxsize; |
| int ret; |
| |
| intel_dp_aux_header(txbuf, msg); |
| |
| switch (msg->request & ~DP_AUX_I2C_MOT) { |
| case DP_AUX_NATIVE_WRITE: |
| case DP_AUX_I2C_WRITE: |
| case DP_AUX_I2C_WRITE_STATUS_UPDATE: |
| txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE; |
| rxsize = 2; /* 0 or 1 data bytes */ |
| |
| if (WARN_ON(txsize > 20)) |
| return -E2BIG; |
| |
| WARN_ON(!msg->buffer != !msg->size); |
| |
| if (msg->buffer) |
| memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size); |
| |
| ret = intel_dp_aux_xfer(intel_dp, txbuf, txsize, |
| rxbuf, rxsize, 0); |
| if (ret > 0) { |
| msg->reply = rxbuf[0] >> 4; |
| |
| if (ret > 1) { |
| /* Number of bytes written in a short write. */ |
| ret = clamp_t(int, rxbuf[1], 0, msg->size); |
| } else { |
| /* Return payload size. */ |
| ret = msg->size; |
| } |
| } |
| break; |
| |
| case DP_AUX_NATIVE_READ: |
| case DP_AUX_I2C_READ: |
| txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE; |
| rxsize = msg->size + 1; |
| |
| if (WARN_ON(rxsize > 20)) |
| return -E2BIG; |
| |
| ret = intel_dp_aux_xfer(intel_dp, txbuf, txsize, |
| rxbuf, rxsize, 0); |
| if (ret > 0) { |
| msg->reply = rxbuf[0] >> 4; |
| /* |
| * Assume happy day, and copy the data. The caller is |
| * expected to check msg->reply before touching it. |
| * |
| * Return payload size. |
| */ |
| ret--; |
| memcpy(msg->buffer, rxbuf + 1, ret); |
| } |
| break; |
| |
| default: |
| ret = -EINVAL; |
| break; |
| } |
| |
| return ret; |
| } |
| |
| |
| static i915_reg_t g4x_aux_ctl_reg(struct intel_dp *intel_dp) |
| { |
| struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
| struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
| enum aux_ch aux_ch = dig_port->aux_ch; |
| |
| switch (aux_ch) { |
| case AUX_CH_B: |
| case AUX_CH_C: |
| case AUX_CH_D: |
| return DP_AUX_CH_CTL(aux_ch); |
| default: |
| MISSING_CASE(aux_ch); |
| return DP_AUX_CH_CTL(AUX_CH_B); |
| } |
| } |
| |
| static i915_reg_t g4x_aux_data_reg(struct intel_dp *intel_dp, int index) |
| { |
| struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
| struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
| enum aux_ch aux_ch = dig_port->aux_ch; |
| |
| switch (aux_ch) { |
| case AUX_CH_B: |
| case AUX_CH_C: |
| case AUX_CH_D: |
| return DP_AUX_CH_DATA(aux_ch, index); |
| default: |
| MISSING_CASE(aux_ch); |
| return DP_AUX_CH_DATA(AUX_CH_B, index); |
| } |
| } |
| |
| static i915_reg_t ilk_aux_ctl_reg(struct intel_dp *intel_dp) |
| { |
| struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
| struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
| enum aux_ch aux_ch = dig_port->aux_ch; |
| |
| switch (aux_ch) { |
| case AUX_CH_A: |
| return DP_AUX_CH_CTL(aux_ch); |
| case AUX_CH_B: |
| case AUX_CH_C: |
| case AUX_CH_D: |
| return PCH_DP_AUX_CH_CTL(aux_ch); |
| default: |
| MISSING_CASE(aux_ch); |
| return DP_AUX_CH_CTL(AUX_CH_A); |
| } |
| } |
| |
| static i915_reg_t ilk_aux_data_reg(struct intel_dp *intel_dp, int index) |
| { |
| struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
| struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
| enum aux_ch aux_ch = dig_port->aux_ch; |
| |
| switch (aux_ch) { |
| case AUX_CH_A: |
| return DP_AUX_CH_DATA(aux_ch, index); |
| case AUX_CH_B: |
| case AUX_CH_C: |
| case AUX_CH_D: |
| return PCH_DP_AUX_CH_DATA(aux_ch, index); |
| default: |
| MISSING_CASE(aux_ch); |
| return DP_AUX_CH_DATA(AUX_CH_A, index); |
| } |
| } |
| |
| static i915_reg_t skl_aux_ctl_reg(struct intel_dp *intel_dp) |
| { |
| struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
| struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
| enum aux_ch aux_ch = dig_port->aux_ch; |
| |
| switch (aux_ch) { |
| case AUX_CH_A: |
| case AUX_CH_B: |
| case AUX_CH_C: |
| case AUX_CH_D: |
| case AUX_CH_E: |
| case AUX_CH_F: |
| return DP_AUX_CH_CTL(aux_ch); |
| default: |
| MISSING_CASE(aux_ch); |
| return DP_AUX_CH_CTL(AUX_CH_A); |
| } |
| } |
| |
| static i915_reg_t skl_aux_data_reg(struct intel_dp *intel_dp, int index) |
| { |
| struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
| struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
| enum aux_ch aux_ch = dig_port->aux_ch; |
| |
| switch (aux_ch) { |
| case AUX_CH_A: |
| case AUX_CH_B: |
| case AUX_CH_C: |
| case AUX_CH_D: |
| case AUX_CH_E: |
| case AUX_CH_F: |
| return DP_AUX_CH_DATA(aux_ch, index); |
| default: |
| MISSING_CASE(aux_ch); |
| return DP_AUX_CH_DATA(AUX_CH_A, index); |
| } |
| } |
| |
| static void |
| intel_dp_aux_fini(struct intel_dp *intel_dp) |
| { |
| kfree(intel_dp->aux.name); |
| } |
| |
| static void |
| intel_dp_aux_init(struct intel_dp *intel_dp) |
| { |
| struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
| struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
| struct intel_encoder *encoder = &dig_port->base; |
| |
| if (INTEL_GEN(dev_priv) >= 9) { |
| intel_dp->aux_ch_ctl_reg = skl_aux_ctl_reg; |
| intel_dp->aux_ch_data_reg = skl_aux_data_reg; |
| } else if (HAS_PCH_SPLIT(dev_priv)) { |
| intel_dp->aux_ch_ctl_reg = ilk_aux_ctl_reg; |
| intel_dp->aux_ch_data_reg = ilk_aux_data_reg; |
| } else { |
| intel_dp->aux_ch_ctl_reg = g4x_aux_ctl_reg; |
| intel_dp->aux_ch_data_reg = g4x_aux_data_reg; |
| } |
| |
| if (INTEL_GEN(dev_priv) >= 9) |
| intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider; |
| else if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) |
| intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider; |
| else if (HAS_PCH_SPLIT(dev_priv)) |
| intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider; |
| else |
| intel_dp->get_aux_clock_divider = g4x_get_aux_clock_divider; |
| |
| if (INTEL_GEN(dev_priv) >= 9) |
| intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl; |
| else |
| intel_dp->get_aux_send_ctl = g4x_get_aux_send_ctl; |
| |
| drm_dp_aux_init(&intel_dp->aux); |
| |
| /* Failure to allocate our preferred name is not critical */ |
| intel_dp->aux.name = kasprintf(GFP_KERNEL, "DPDDC-%c", |
| port_name(encoder->port)); |
| intel_dp->aux.transfer = intel_dp_aux_transfer; |
| } |
| |
| bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp) |
| { |
| int max_rate = intel_dp->source_rates[intel_dp->num_source_rates - 1]; |
| |
| return max_rate >= 540000; |
| } |
| |
| bool intel_dp_source_supports_hbr3(struct intel_dp *intel_dp) |
| { |
| int max_rate = intel_dp->source_rates[intel_dp->num_source_rates - 1]; |
| |
| return max_rate >= 810000; |
| } |
| |
| static void |
| intel_dp_set_clock(struct intel_encoder *encoder, |
| struct intel_crtc_state *pipe_config) |
| { |
| struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
| const struct dp_link_dpll *divisor = NULL; |
| int i, count = 0; |
| |
| if (IS_G4X(dev_priv)) { |
| divisor = g4x_dpll; |
| count = ARRAY_SIZE(g4x_dpll); |
| } else if (HAS_PCH_SPLIT(dev_priv)) { |
| divisor = pch_dpll; |
| count = ARRAY_SIZE(pch_dpll); |
| } else if (IS_CHERRYVIEW(dev_priv)) { |
| divisor = chv_dpll; |
| count = ARRAY_SIZE(chv_dpll); |
| } else if (IS_VALLEYVIEW(dev_priv)) { |
| divisor = vlv_dpll; |
| count = ARRAY_SIZE(vlv_dpll); |
| } |
| |
| if (divisor && count) { |
| for (i = 0; i < count; i++) { |
| if (pipe_config->port_clock == divisor[i].clock) { |
| pipe_config->dpll = divisor[i].dpll; |
| pipe_config->clock_set = true; |
| break; |
| } |
| } |
| } |
| } |
| |
| static void snprintf_int_array(char *str, size_t len, |
| const int *array, int nelem) |
| { |
| int i; |
| |
| str[0] = '\0'; |
| |
| for (i = 0; i < nelem; i++) { |
| int r = snprintf(str, len, "%s%d", i ? ", " : "", array[i]); |
| if (r >= len) |
| return; |
| str += r; |
| len -= r; |
| } |
| } |
| |
| static void intel_dp_print_rates(struct intel_dp *intel_dp) |
| { |
| char str[128]; /* FIXME: too big for stack? */ |
| |
| if ((drm_debug & DRM_UT_KMS) == 0) |
| return; |
| |
| snprintf_int_array(str, sizeof(str), |
| intel_dp->source_rates, intel_dp->num_source_rates); |
| DRM_DEBUG_KMS("source rates: %s\n", str); |
| |
| snprintf_int_array(str, sizeof(str), |
| intel_dp->sink_rates, intel_dp->num_sink_rates); |
| DRM_DEBUG_KMS("sink rates: %s\n", str); |
| |
| snprintf_int_array(str, sizeof(str), |
| intel_dp->common_rates, intel_dp->num_common_rates); |
| DRM_DEBUG_KMS("common rates: %s\n", str); |
| } |
| |
| int |
| intel_dp_max_link_rate(struct intel_dp *intel_dp) |
| { |
| int len; |
| |
| len = intel_dp_common_len_rate_limit(intel_dp, intel_dp->max_link_rate); |
| if (WARN_ON(len <= 0)) |
| return 162000; |
| |
| return intel_dp->common_rates[len - 1]; |
| } |
| |
| int intel_dp_rate_select(struct intel_dp *intel_dp, int rate) |
| { |
| int i = intel_dp_rate_index(intel_dp->sink_rates, |
| intel_dp->num_sink_rates, rate); |
| |
| if (WARN_ON(i < 0)) |
| i = 0; |
| |
| return i; |
| } |
| |
| void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock, |
| u8 *link_bw, u8 *rate_select) |
| { |
| /* eDP 1.4 rate select method. */ |
| if (intel_dp->use_rate_select) { |
| *link_bw = 0; |
| *rate_select = |
| intel_dp_rate_select(intel_dp, port_clock); |
| } else { |
| *link_bw = drm_dp_link_rate_to_bw_code(port_clock); |
| *rate_select = 0; |
| } |
| } |
| |
| static bool intel_dp_source_supports_fec(struct intel_dp *intel_dp, |
| const struct intel_crtc_state *pipe_config) |
| { |
| struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
| |
| return INTEL_GEN(dev_priv) >= 11 && |
| pipe_config->cpu_transcoder != TRANSCODER_A; |
| } |
| |
| static bool intel_dp_supports_fec(struct intel_dp *intel_dp, |
| const struct intel_crtc_state *pipe_config) |
| { |
| return intel_dp_source_supports_fec(intel_dp, pipe_config) && |
| drm_dp_sink_supports_fec(intel_dp->fec_capable); |
| } |
| |
| static bool intel_dp_source_supports_dsc(struct intel_dp *intel_dp, |
| const struct intel_crtc_state *pipe_config) |
| { |
| struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
| |
| return INTEL_GEN(dev_priv) >= 10 && |
| pipe_config->cpu_transcoder != TRANSCODER_A; |
| } |
| |
| static bool intel_dp_supports_dsc(struct intel_dp *intel_dp, |
| const struct intel_crtc_state *pipe_config) |
| { |
| if (!intel_dp_is_edp(intel_dp) && !pipe_config->fec_enable) |
| return false; |
| |
| return intel_dp_source_supports_dsc(intel_dp, pipe_config) && |
| drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd); |
| } |
| |
| static int intel_dp_compute_bpp(struct intel_dp *intel_dp, |
| struct intel_crtc_state *pipe_config) |
| { |
| struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
| struct intel_connector *intel_connector = intel_dp->attached_connector; |
| int bpp, bpc; |
| |
| bpp = pipe_config->pipe_bpp; |
| bpc = drm_dp_downstream_max_bpc(intel_dp->dpcd, intel_dp->downstream_ports); |
| |
| if (bpc > 0) |
| bpp = min(bpp, 3*bpc); |
| |
| if (intel_dp_is_edp(intel_dp)) { |
| /* Get bpp from vbt only for panels that dont have bpp in edid */ |
| if (intel_connector->base.display_info.bpc == 0 && |
| dev_priv->vbt.edp.bpp && dev_priv->vbt.edp.bpp < bpp) { |
| DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n", |
| dev_priv->vbt.edp.bpp); |
| bpp = dev_priv->vbt.edp.bpp; |
| } |
| } |
| |
| return bpp; |
| } |
| |
| /* Adjust link config limits based on compliance test requests. */ |
| void |
| intel_dp_adjust_compliance_config(struct intel_dp *intel_dp, |
| struct intel_crtc_state *pipe_config, |
| struct link_config_limits *limits) |
| { |
| /* For DP Compliance we override the computed bpp for the pipe */ |
| if (intel_dp->compliance.test_data.bpc != 0) { |
| int bpp = 3 * intel_dp->compliance.test_data.bpc; |
| |
| limits->min_bpp = limits->max_bpp = bpp; |
| pipe_config->dither_force_disable = bpp == 6 * 3; |
| |
| DRM_DEBUG_KMS("Setting pipe_bpp to %d\n", bpp); |
| } |
| |
| /* Use values requested by Compliance Test Request */ |
| if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) { |
| int index; |
| |
| /* Validate the compliance test data since max values |
| * might have changed due to link train fallback. |
| */ |
| if (intel_dp_link_params_valid(intel_dp, intel_dp->compliance.test_link_rate, |
| intel_dp->compliance.test_lane_count)) { |
| index = intel_dp_rate_index(intel_dp->common_rates, |
| intel_dp->num_common_rates, |
| intel_dp->compliance.test_link_rate); |
| if (index >= 0) |
| limits->min_clock = limits->max_clock = index; |
| limits->min_lane_count = limits->max_lane_count = |
| intel_dp->compliance.test_lane_count; |
| } |
| } |
| } |
| |
| static int intel_dp_output_bpp(const struct intel_crtc_state *crtc_state, int bpp) |
| { |
| /* |
| * bpp value was assumed to RGB format. And YCbCr 4:2:0 output |
| * format of the number of bytes per pixel will be half the number |
| * of bytes of RGB pixel. |
| */ |
| if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) |
| bpp /= 2; |
| |
| return bpp; |
| } |
| |
| /* Optimize link config in order: max bpp, min clock, min lanes */ |
| static int |
| intel_dp_compute_link_config_wide(struct intel_dp *intel_dp, |
| struct intel_crtc_state *pipe_config, |
| const struct link_config_limits *limits) |
| { |
| struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
| int bpp, clock, lane_count; |
| int mode_rate, link_clock, link_avail; |
| |
| for (bpp = limits->max_bpp; bpp >= limits->min_bpp; bpp -= 2 * 3) { |
| int output_bpp = intel_dp_output_bpp(pipe_config, bpp); |
| |
| mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock, |
| output_bpp); |
| |
| for (clock = limits->min_clock; clock <= limits->max_clock; clock++) { |
| for (lane_count = limits->min_lane_count; |
| lane_count <= limits->max_lane_count; |
| lane_count <<= 1) { |
| link_clock = intel_dp->common_rates[clock]; |
| link_avail = intel_dp_max_data_rate(link_clock, |
| lane_count); |
| |
| if (mode_rate <= link_avail) { |
| pipe_config->lane_count = lane_count; |
| pipe_config->pipe_bpp = bpp; |
| pipe_config->port_clock = link_clock; |
| |
| return 0; |
| } |
| } |
| } |
| } |
| |
| return -EINVAL; |
| } |
| |
| static int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 dsc_max_bpc) |
| { |
| int i, num_bpc; |
| u8 dsc_bpc[3] = {0}; |
| |
| num_bpc = drm_dp_dsc_sink_supported_input_bpcs(intel_dp->dsc_dpcd, |
| dsc_bpc); |
| for (i = 0; i < num_bpc; i++) { |
| if (dsc_max_bpc >= dsc_bpc[i]) |
| return dsc_bpc[i] * 3; |
| } |
| |
| return 0; |
| } |
| |
| static int intel_dp_dsc_compute_config(struct intel_dp *intel_dp, |
| struct intel_crtc_state *pipe_config, |
| struct drm_connector_state *conn_state, |
| struct link_config_limits *limits) |
| { |
| struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
| struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); |
| struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
| u8 dsc_max_bpc; |
| int pipe_bpp; |
| int ret; |
| |
| pipe_config->fec_enable = !intel_dp_is_edp(intel_dp) && |
| intel_dp_supports_fec(intel_dp, pipe_config); |
| |
| if (!intel_dp_supports_dsc(intel_dp, pipe_config)) |
| return -EINVAL; |
| |
| dsc_max_bpc = min_t(u8, DP_DSC_MAX_SUPPORTED_BPC, |
| conn_state->max_requested_bpc); |
| |
| pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, dsc_max_bpc); |
| if (pipe_bpp < DP_DSC_MIN_SUPPORTED_BPC * 3) { |
| DRM_DEBUG_KMS("No DSC support for less than 8bpc\n"); |
| return -EINVAL; |
| } |
| |
| /* |
| * For now enable DSC for max bpp, max link rate, max lane count. |
| * Optimize this later for the minimum possible link rate/lane count |
| * with DSC enabled for the requested mode. |
| */ |
| pipe_config->pipe_bpp = pipe_bpp; |
| pipe_config->port_clock = intel_dp->common_rates[limits->max_clock]; |
| pipe_config->lane_count = limits->max_lane_count; |
| |
| if (intel_dp_is_edp(intel_dp)) { |
| pipe_config->dsc_params.compressed_bpp = |
| min_t(u16, drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd) >> 4, |
| pipe_config->pipe_bpp); |
| pipe_config->dsc_params.slice_count = |
| drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd, |
| true); |
| } else { |
| u16 dsc_max_output_bpp; |
| u8 dsc_dp_slice_count; |
| |
| dsc_max_output_bpp = |
| intel_dp_dsc_get_output_bpp(pipe_config->port_clock, |
| pipe_config->lane_count, |
| adjusted_mode->crtc_clock, |
| adjusted_mode->crtc_hdisplay); |
| dsc_dp_slice_count = |
| intel_dp_dsc_get_slice_count(intel_dp, |
| adjusted_mode->crtc_clock, |
| adjusted_mode->crtc_hdisplay); |
| if (!dsc_max_output_bpp || !dsc_dp_slice_count) { |
| DRM_DEBUG_KMS("Compressed BPP/Slice Count not supported\n"); |
| return -EINVAL; |
| } |
| pipe_config->dsc_params.compressed_bpp = min_t(u16, |
| dsc_max_output_bpp >> 4, |
| pipe_config->pipe_bpp); |
| pipe_config->dsc_params.slice_count = dsc_dp_slice_count; |
| } |
| /* |
| * VDSC engine operates at 1 Pixel per clock, so if peak pixel rate |
| * is greater than the maximum Cdclock and if slice count is even |
| * then we need to use 2 VDSC instances. |
| */ |
| if (adjusted_mode->crtc_clock > dev_priv->max_cdclk_freq) { |
| if (pipe_config->dsc_params.slice_count > 1) { |
| pipe_config->dsc_params.dsc_split = true; |
| } else { |
| DRM_DEBUG_KMS("Cannot split stream to use 2 VDSC instances\n"); |
| return -EINVAL; |
| } |
| } |
| |
| ret = intel_dp_compute_dsc_params(intel_dp, pipe_config); |
| if (ret < 0) { |
| DRM_DEBUG_KMS("Cannot compute valid DSC parameters for Input Bpp = %d " |
| "Compressed BPP = %d\n", |
| pipe_config->pipe_bpp, |
| pipe_config->dsc_params.compressed_bpp); |
| return ret; |
| } |
| |
| pipe_config->dsc_params.compression_enable = true; |
| DRM_DEBUG_KMS("DP DSC computed with Input Bpp = %d " |
| "Compressed Bpp = %d Slice Count = %d\n", |
| pipe_config->pipe_bpp, |
| pipe_config->dsc_params.compressed_bpp, |
| pipe_config->dsc_params.slice_count); |
| |
| return 0; |
| } |
| |
| int intel_dp_min_bpp(const struct intel_crtc_state *crtc_state) |
| { |
| if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_RGB) |
| return 6 * 3; |
| else |
| return 8 * 3; |
| } |
| |
| static int |
| intel_dp_compute_link_config(struct intel_encoder *encoder, |
| struct intel_crtc_state *pipe_config, |
| struct drm_connector_state *conn_state) |
| { |
| struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
| struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
| struct link_config_limits limits; |
| int common_len; |
| int ret; |
| |
| common_len = intel_dp_common_len_rate_limit(intel_dp, |
| intel_dp->max_link_rate); |
| |
| /* No common link rates between source and sink */ |
| WARN_ON(common_len <= 0); |
| |
| limits.min_clock = 0; |
| limits.max_clock = common_len - 1; |
| |
| limits.min_lane_count = 1; |
| limits.max_lane_count = intel_dp_max_lane_count(intel_dp); |
| |
| limits.min_bpp = intel_dp_min_bpp(pipe_config); |
| limits.max_bpp = intel_dp_compute_bpp(intel_dp, pipe_config); |
| |
| if (intel_dp_is_edp(intel_dp)) { |
| /* |
| * Use the maximum clock and number of lanes the eDP panel |
| * advertizes being capable of. The panels are generally |
| * designed to support only a single clock and lane |
| * configuration, and typically these values correspond to the |
| * native resolution of the panel. |
| */ |
| limits.min_lane_count = limits.max_lane_count; |
| limits.min_clock = limits.max_clock; |
| } |
| |
| intel_dp_adjust_compliance_config(intel_dp, pipe_config, &limits); |
| |
| DRM_DEBUG_KMS("DP link computation with max lane count %i " |
| "max rate %d max bpp %d pixel clock %iKHz\n", |
| limits.max_lane_count, |
| intel_dp->common_rates[limits.max_clock], |
| limits.max_bpp, adjusted_mode->crtc_clock); |
| |
| /* |
| * Optimize for slow and wide. This is the place to add alternative |
| * optimization policy. |
| */ |
| ret = intel_dp_compute_link_config_wide(intel_dp, pipe_config, &limits); |
| |
| /* enable compression if the mode doesn't fit available BW */ |
| DRM_DEBUG_KMS("Force DSC en = %d\n", intel_dp->force_dsc_en); |
| if (ret || intel_dp->force_dsc_en) { |
| ret = intel_dp_dsc_compute_config(intel_dp, pipe_config, |
| conn_state, &limits); |
| if (ret < 0) |
| return ret; |
| } |
| |
| if (pipe_config->dsc_params.compression_enable) { |
| DRM_DEBUG_KMS("DP lane count %d clock %d Input bpp %d Compressed bpp %d\n", |
| pipe_config->lane_count, pipe_config->port_clock, |
| pipe_config->pipe_bpp, |
| pipe_config->dsc_params.compressed_bpp); |
| |
| DRM_DEBUG_KMS("DP link rate required %i available %i\n", |
| intel_dp_link_required(adjusted_mode->crtc_clock, |
| pipe_config->dsc_params.compressed_bpp), |
| intel_dp_max_data_rate(pipe_config->port_clock, |
| pipe_config->lane_count)); |
| } else { |
| DRM_DEBUG_KMS("DP lane count %d clock %d bpp %d\n", |
| pipe_config->lane_count, pipe_config->port_clock, |
| pipe_config->pipe_bpp); |
| |
| DRM_DEBUG_KMS("DP link rate required %i available %i\n", |
| intel_dp_link_required(adjusted_mode->crtc_clock, |
| pipe_config->pipe_bpp), |
| intel_dp_max_data_rate(pipe_config->port_clock, |
| pipe_config->lane_count)); |
| } |
| return 0; |
| } |
| |
| static int |
| intel_dp_ycbcr420_config(struct intel_dp *intel_dp, |
| struct drm_connector *connector, |
| struct intel_crtc_state *crtc_state) |
| { |
| const struct drm_display_info *info = &connector->display_info; |
| const struct drm_display_mode *adjusted_mode = |
| &crtc_state->base.adjusted_mode; |
| struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
| int ret; |
| |
| if (!drm_mode_is_420_only(info, adjusted_mode) || |
| !intel_dp_get_colorimetry_status(intel_dp) || |
| !connector->ycbcr_420_allowed) |
| return 0; |
| |
| crtc_state->output_format = INTEL_OUTPUT_FORMAT_YCBCR420; |
| |
| /* YCBCR 420 output conversion needs a scaler */ |
| ret = skl_update_scaler_crtc(crtc_state); |
| if (ret) { |
| DRM_DEBUG_KMS("Scaler allocation for output failed\n"); |
| return ret; |
| } |
| |
| intel_pch_panel_fitting(crtc, crtc_state, DRM_MODE_SCALE_FULLSCREEN); |
| |
| return 0; |
| } |
| |
| bool intel_dp_limited_color_range(const struct intel_crtc_state *crtc_state, |
| const struct drm_connector_state *conn_state) |
| { |
| const struct intel_digital_connector_state *intel_conn_state = |
| to_intel_digital_connector_state(conn_state); |
| const struct drm_display_mode *adjusted_mode = |
| &crtc_state->base.adjusted_mode; |
| |
| if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) { |
| /* |
| * See: |
| * CEA-861-E - 5.1 Default Encoding Parameters |
| * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry |
| */ |
| return crtc_state->pipe_bpp != 18 && |
| drm_default_rgb_quant_range(adjusted_mode) == |
| HDMI_QUANTIZATION_RANGE_LIMITED; |
| } else { |
| return intel_conn_state->broadcast_rgb == |
| INTEL_BROADCAST_RGB_LIMITED; |
| } |
| } |
| |
| int |
| intel_dp_compute_config(struct intel_encoder *encoder, |
| struct intel_crtc_state *pipe_config, |
| struct drm_connector_state *conn_state) |
| { |
| struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
| struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
| struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
| struct intel_lspcon *lspcon = enc_to_intel_lspcon(&encoder->base); |
| enum port port = encoder->port; |
| struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc); |
| struct intel_connector *intel_connector = intel_dp->attached_connector; |
| struct intel_digital_connector_state *intel_conn_state = |
| to_intel_digital_connector_state(conn_state); |
| bool constant_n = drm_dp_has_quirk(&intel_dp->desc, |
| DP_DPCD_QUIRK_CONSTANT_N); |
| int ret = 0, output_bpp; |
| |
| if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv) && port != PORT_A) |
| pipe_config->has_pch_encoder = true; |
| |
| pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; |
| if (lspcon->active) |
| lspcon_ycbcr420_config(&intel_connector->base, pipe_config); |
| else |
| ret = intel_dp_ycbcr420_config(intel_dp, &intel_connector->base, |
| pipe_config); |
| |
| if (ret) |
| return ret; |
| |
| pipe_config->has_drrs = false; |
| if (IS_G4X(dev_priv) || port == PORT_A) |
| pipe_config->has_audio = false; |
| else if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO) |
| pipe_config->has_audio = intel_dp->has_audio; |
| else |
| pipe_config->has_audio = intel_conn_state->force_audio == HDMI_AUDIO_ON; |
| |
| if (intel_dp_is_edp(intel_dp) && intel_connector->panel.fixed_mode) { |
| intel_fixed_panel_mode(intel_connector->panel.fixed_mode, |
| adjusted_mode); |
| |
| if (INTEL_GEN(dev_priv) >= 9) { |
| ret = skl_update_scaler_crtc(pipe_config); |
| if (ret) |
| return ret; |
| } |
| |
| if (HAS_GMCH(dev_priv)) |
| intel_gmch_panel_fitting(intel_crtc, pipe_config, |
| conn_state->scaling_mode); |
| else |
| intel_pch_panel_fitting(intel_crtc, pipe_config, |
| conn_state->scaling_mode); |
| } |
| |
| if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) |
| return -EINVAL; |
| |
| if (HAS_GMCH(dev_priv) && |
| adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) |
| return -EINVAL; |
| |
| if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) |
| return -EINVAL; |
| |
| ret = intel_dp_compute_link_config(encoder, pipe_config, conn_state); |
| if (ret < 0) |
| return ret; |
| |
| pipe_config->limited_color_range = |
| intel_dp_limited_color_range(pipe_config, conn_state); |
| |
| if (pipe_config->dsc_params.compression_enable) |
| output_bpp = pipe_config->dsc_params.compressed_bpp; |
| else |
| output_bpp = intel_dp_output_bpp(pipe_config, pipe_config->pipe_bpp); |
| |
| intel_link_compute_m_n(output_bpp, |
| pipe_config->lane_count, |
| adjusted_mode->crtc_clock, |
| pipe_config->port_clock, |
| &pipe_config->dp_m_n, |
| constant_n, pipe_config->fec_enable); |
| |
| if (intel_connector->panel.downclock_mode != NULL && |
| dev_priv->drrs.type == SEAMLESS_DRRS_SUPPORT) { |
| pipe_config->has_drrs = true; |
| intel_link_compute_m_n(output_bpp, |
| pipe_config->lane_count, |
| intel_connector->panel.downclock_mode->clock, |
| pipe_config->port_clock, |
| &pipe_config->dp_m2_n2, |
| constant_n, pipe_config->fec_enable); |
| } |
| |
| if (!HAS_DDI(dev_priv)) |
| intel_dp_set_clock(encoder, pipe_config); |
| |
| intel_psr_compute_config(intel_dp, pipe_config); |
| |
| return 0; |
| } |
| |
| void intel_dp_set_link_params(struct intel_dp *intel_dp, |
| int link_rate, u8 lane_count, |
| bool link_mst) |
| { |
| intel_dp->link_trained = false; |
| intel_dp->link_rate = link_rate; |
| intel_dp->lane_count = lane_count; |
| intel_dp->link_mst = link_mst; |
| } |
| |
| static void intel_dp_prepare(struct intel_encoder *encoder, |
| const struct intel_crtc_state *pipe_config) |
| { |
| struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
| struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
| enum port port = encoder->port; |
| struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc); |
| const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
| |
| intel_dp_set_link_params(intel_dp, pipe_config->port_clock, |
| pipe_config->lane_count, |
| intel_crtc_has_type(pipe_config, |
| INTEL_OUTPUT_DP_MST)); |
| |
| /* |
| * There are four kinds of DP registers: |
| * |
| * IBX PCH |
| * SNB CPU |
| * IVB CPU |
| * CPT PCH |
| * |
| * IBX PCH and CPU are the same for almost everything, |
| * except that the CPU DP PLL is configured in this |
| * register |
| * |
| * CPT PCH is quite different, having many bits moved |
| * to the TRANS_DP_CTL register instead. That |
| * configuration happens (oddly) in ironlake_pch_enable |
| */ |
| |
| /* Preserve the BIOS-computed detected bit. This is |
| * supposed to be read-only. |
| */ |
| intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED; |
| |
| /* Handle DP bits in common between all three register formats */ |
| intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0; |
| intel_dp->DP |= DP_PORT_WIDTH(pipe_config->lane_count); |
| |
| /* Split out the IBX/CPU vs CPT settings */ |
| |
| if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) { |
| if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
| intel_dp->DP |= DP_SYNC_HS_HIGH; |
| if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) |
| intel_dp->DP |= DP_SYNC_VS_HIGH; |
| intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT; |
| |
| if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) |
| intel_dp->DP |= DP_ENHANCED_FRAMING; |
| |
| intel_dp->DP |= DP_PIPE_SEL_IVB(crtc->pipe); |
| } else if (HAS_PCH_CPT(dev_priv) && port != PORT_A) { |
| u32 trans_dp; |
| |
| intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT; |
| |
| trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe)); |
| if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) |
| trans_dp |= TRANS_DP_ENH_FRAMING; |
| else |
| trans_dp &= ~TRANS_DP_ENH_FRAMING; |
| I915_WRITE(TRANS_DP_CTL(crtc->pipe), trans_dp); |
| } else { |
| if (IS_G4X(dev_priv) && pipe_config->limited_color_range) |
| intel_dp->DP |= DP_COLOR_RANGE_16_235; |
| |
| if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
| intel_dp->DP |= DP_SYNC_HS_HIGH; |
| if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) |
| intel_dp->DP |= DP_SYNC_VS_HIGH; |
| intel_dp->DP |= DP_LINK_TRAIN_OFF; |
| |
| if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) |
| intel_dp->DP |= DP_ENHANCED_FRAMING; |
| |
| if (IS_CHERRYVIEW(dev_priv)) |
| intel_dp->DP |= DP_PIPE_SEL_CHV(crtc->pipe); |
| else |
| intel_dp->DP |= DP_PIPE_SEL(crtc->pipe); |
| } |
| } |
| |
| #define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK) |
| #define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE) |
| |
| #define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0) |
| #define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0) |
| |
| #define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK) |
| #define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE) |
| |
| static void intel_pps_verify_state(struct intel_dp *intel_dp); |
| |
| static void wait_panel_status(struct intel_dp *intel_dp, |
| u32 mask, |
| u32 value) |
| { |
| struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
| i915_reg_t pp_stat_reg, pp_ctrl_reg; |
| |
| lockdep_assert_held(&dev_priv->pps_mutex); |
| |
| intel_pps_verify_state(intel_dp); |
| |
| pp_stat_reg = _pp_stat_reg(intel_dp); |
| pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
| |
| DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n", |
| mask, value, |
| I915_READ(pp_stat_reg), |
| I915_READ(pp_ctrl_reg)); |
| |
| if (intel_de_wait_for_register(dev_priv, pp_stat_reg, |
| mask, value, 5000)) |
| DRM_ERROR("Panel status timeout: status %08x control %08x\n", |
| I915_READ(pp_stat_reg), |
| I915_READ(pp_ctrl_reg)); |
| |
| DRM_DEBUG_KMS("Wait complete\n"); |
| } |
| |
| static void wait_panel_on(struct intel_dp *intel_dp) |
| { |
| DRM_DEBUG_KMS("Wait for panel power on\n"); |
| wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE); |
| } |
| |
| static void wait_panel_off(struct intel_dp *intel_dp) |
| { |
| DRM_DEBUG_KMS("Wait for panel power off time\n"); |
| wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE); |
| } |
| |
| static void wait_panel_power_cycle(struct intel_dp *intel_dp) |
| { |
| ktime_t panel_power_on_time; |
| s64 panel_power_off_duration; |
| |
| DRM_DEBUG_KMS("Wait for panel power cycle\n"); |
| |
| /* take the difference of currrent time and panel power off time |
| * and then make panel wait for t11_t12 if needed. */ |
| panel_power_on_time = ktime_get_boottime(); |
| panel_power_off_duration = ktime_ms_delta(panel_power_on_time, intel_dp->panel_power_off_time); |
| |
| /* When we disable the VDD override bit last we have to do the manual |
| * wait. */ |
| if (panel_power_off_duration < (s64)intel_dp->panel_power_cycle_delay) |
| wait_remaining_ms_from_jiffies(jiffies, |
| intel_dp->panel_power_cycle_delay - panel_power_off_duration); |
| |
| wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE); |
| } |
| |
| static void wait_backlight_on(struct intel_dp *intel_dp) |
| { |
| wait_remaining_ms_from_jiffies(intel_dp->last_power_on, |
| intel_dp->backlight_on_delay); |
| } |
| |
| static void edp_wait_backlight_off(struct intel_dp *intel_dp) |
| { |
| wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off, |
| intel_dp->backlight_off_delay); |
| } |
| |
| /* Read the current pp_control value, unlocking the register if it |
| * is locked |
| */ |
| |
| static u32 ironlake_get_pp_control(struct intel_dp *intel_dp) |
| { |
| struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
| u32 control; |
| |
| lockdep_assert_held(&dev_priv->pps_mutex); |
| |
| control = I915_READ(_pp_ctrl_reg(intel_dp)); |
| if (WARN_ON(!HAS_DDI(dev_priv) && |
| (control & PANEL_UNLOCK_MASK) != PANEL_UNLOCK_REGS)) { |
| control &= ~PANEL_UNLOCK_MASK; |
| control |= PANEL_UNLOCK_REGS; |
| } |
| return control; |
| } |
| |
| /* |
| * Must be paired with edp_panel_vdd_off(). |
| * Must hold pps_mutex around the whole on/off sequence. |
| * Can be nested with intel_edp_panel_vdd_{on,off}() calls. |
| */ |
| static bool edp_panel_vdd_on(struct intel_dp *intel_dp) |
| { |
| struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
| struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| u32 pp; |
| i915_reg_t pp_stat_reg, pp_ctrl_reg; |
| bool need_to_disable = !intel_dp->want_panel_vdd; |
| |
| lockdep_assert_held(&dev_priv->pps_mutex); |
| |
| if (!intel_dp_is_edp(intel_dp)) |
| return false; |
| |
| cancel_delayed_work(&intel_dp->panel_vdd_work); |
| intel_dp->want_panel_vdd = true; |
| |
| if (edp_have_panel_vdd(intel_dp)) |
| return need_to_disable; |
| |
| intel_display_power_get(dev_priv, |
| intel_aux_power_domain(intel_dig_port)); |
| |
| DRM_DEBUG_KMS("Turning eDP port %c VDD on\n", |
| port_name(intel_dig_port->base.port)); |
| |
| if (!edp_have_panel_power(intel_dp)) |
| wait_panel_power_cycle(intel_dp); |
| |
| pp = ironlake_get_pp_control(intel_dp); |
| pp |= EDP_FORCE_VDD; |
| |
| pp_stat_reg = _pp_stat_reg(intel_dp); |
| pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
| |
| I915_WRITE(pp_ctrl_reg, pp); |
| POSTING_READ(pp_ctrl_reg); |
| DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n", |
| I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg)); |
| /* |
| * If the panel wasn't on, delay before accessing aux channel |
| */ |
| if (!edp_have_panel_power(intel_dp)) { |
| DRM_DEBUG_KMS("eDP port %c panel power wasn't enabled\n", |
| port_name(intel_dig_port->base.port)); |
| msleep(intel_dp->panel_power_up_delay); |
| } |
| |
| return need_to_disable; |
| } |
| |
| /* |
| * Must be paired with intel_edp_panel_vdd_off() or |
| * intel_edp_panel_off(). |
| * Nested calls to these functions are not allowed since |
| * we drop the lock. Caller must use some higher level |
| * locking to prevent nested calls from other threads. |
| */ |
| void intel_edp_panel_vdd_on(struct intel_dp *intel_dp) |
| { |
| intel_wakeref_t wakeref; |
| bool vdd; |
| |
| if (!intel_dp_is_edp(intel_dp)) |
| return; |
| |
| vdd = false; |
| with_pps_lock(intel_dp, wakeref) |
| vdd = edp_panel_vdd_on(intel_dp); |
| I915_STATE_WARN(!vdd, "eDP port %c VDD already requested on\n", |
| port_name(dp_to_dig_port(intel_dp)->base.port)); |
| } |
| |
| static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp) |
| { |
| struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
| struct intel_digital_port *intel_dig_port = |
| dp_to_dig_port(intel_dp); |
| u32 pp; |
| i915_reg_t pp_stat_reg, pp_ctrl_reg; |
| |
| lockdep_assert_held(&dev_priv->pps_mutex); |
| |
| WARN_ON(intel_dp->want_panel_vdd); |
| |
| if (!edp_have_panel_vdd(intel_dp)) |
| return; |
| |
| DRM_DEBUG_KMS("Turning eDP port %c VDD off\n", |
| port_name(intel_dig_port->base.port)); |
| |
| pp = ironlake_get_pp_control(intel_dp); |
| pp &= ~EDP_FORCE_VDD; |
| |
| pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
| pp_stat_reg = _pp_stat_reg(intel_dp); |
| |
| I915_WRITE(pp_ctrl_reg, pp); |
| POSTING_READ(pp_ctrl_reg); |
| |
| /* Make sure sequencer is idle before allowing subsequent activity */ |
| DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n", |
| I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg)); |
| |
| if ((pp & PANEL_POWER_ON) == 0) |
| intel_dp->panel_power_off_time = ktime_get_boottime(); |
| |
| intel_display_power_put_unchecked(dev_priv, |
| intel_aux_power_domain(intel_dig_port)); |
| } |
| |
| static void edp_panel_vdd_work(struct work_struct *__work) |
| { |
| struct intel_dp *intel_dp = |
| container_of(to_delayed_work(__work), |
| struct intel_dp, panel_vdd_work); |
| intel_wakeref_t wakeref; |
| |
| with_pps_lock(intel_dp, wakeref) { |
| if (!intel_dp->want_panel_vdd) |
| edp_panel_vdd_off_sync(intel_dp); |
| } |
| } |
| |
| static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp) |
| { |
| unsigned long delay; |
| |
| /* |
| * Queue the timer to fire a long time from now (relative to the power |
| * down delay) to keep the panel power up across a sequence of |
| * operations. |
| */ |
| delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5); |
| schedule_delayed_work(&intel_dp->panel_vdd_work, delay); |
| } |
| |
| /* |
| * Must be paired with edp_panel_vdd_on(). |
| * Must hold pps_mutex around the whole on/off sequence. |
| * Can be nested with intel_edp_panel_vdd_{on,off}() calls. |
| */ |
| static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync) |
| { |
| struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
| |
| lockdep_assert_held(&dev_priv->pps_mutex); |
| |
| if (!intel_dp_is_edp(intel_dp)) |
| return; |
| |
| I915_STATE_WARN(!intel_dp->want_panel_vdd, "eDP port %c VDD not forced on", |
| port_name(dp_to_dig_port(intel_dp)->base.port)); |
| |
| intel_dp->want_panel_vdd = false; |
| |
| if (sync) |
| edp_panel_vdd_off_sync(intel_dp); |
| else |
| edp_panel_vdd_schedule_off(intel_dp); |
| } |
| |
| static void edp_panel_on(struct intel_dp *intel_dp) |
| { |
| struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
| u32 pp; |
| i915_reg_t pp_ctrl_reg; |
| |
| lockdep_assert_held(&dev_priv->pps_mutex); |
| |
| if (!intel_dp_is_edp(intel_dp)) |
| return; |
| |
| DRM_DEBUG_KMS("Turn eDP port %c panel power on\n", |
| port_name(dp_to_dig_port(intel_dp)->base.port)); |
| |
| if (WARN(edp_have_panel_power(intel_dp), |
| "eDP port %c panel power already on\n", |
| port_name(dp_to_dig_port(intel_dp)->base.port))) |
| return; |
| |
| wait_panel_power_cycle(intel_dp); |
| |
| pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
| pp = ironlake_get_pp_control(intel_dp); |
| if (IS_GEN(dev_priv, 5)) { |
| /* ILK workaround: disable reset around power sequence */ |
| pp &= ~PANEL_POWER_RESET; |
| I915_WRITE(pp_ctrl_reg, pp); |
| POSTING_READ(pp_ctrl_reg); |
| } |
| |
| pp |= PANEL_POWER_ON; |
| if (!IS_GEN(dev_priv, 5)) |
| pp |= PANEL_POWER_RESET; |
| |
| I915_WRITE(pp_ctrl_reg, pp); |
| POSTING_READ(pp_ctrl_reg); |
| |
| wait_panel_on(intel_dp); |
| intel_dp->last_power_on = jiffies; |
| |
| if (IS_GEN(dev_priv, 5)) { |
| pp |= PANEL_POWER_RESET; /* restore panel reset bit */ |
| I915_WRITE(pp_ctrl_reg, pp); |
| POSTING_READ(pp_ctrl_reg); |
| } |
| } |
| |
| void intel_edp_panel_on(struct intel_dp *intel_dp) |
| { |
| intel_wakeref_t wakeref; |
| |
| if (!intel_dp_is_edp(intel_dp)) |
| return; |
| |
| with_pps_lock(intel_dp, wakeref) |
| edp_panel_on(intel_dp); |
| } |
| |
| |
| static void edp_panel_off(struct intel_dp *intel_dp) |
| { |
| struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
| struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
| u32 pp; |
| i915_reg_t pp_ctrl_reg; |
| |
| lockdep_assert_held(&dev_priv->pps_mutex); |
| |
| if (!intel_dp_is_edp(intel_dp)) |
| return; |
|