arch/mips/boot/dts/mobileye/eyeq5.dtsi

// SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
/*
* Copyright 2023 Mobileye Vision Technologies Ltd.
*/

#include <dt-bindings/interrupt-controller/mips-gic.h>

#include "eyeq5-fixed-clocks.dtsi"

/ {
	#address-cells = <2>;
	#size-cells = <2>;
	cpus {
		#address-cells = <1>;
		#size-cells = <0>;
		cpu@0 {
			device_type = "cpu";
			compatible = "img,i6500";
			reg = <0>;
			clocks = <&core0_clk>;
		};
	};

	reserved-memory {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		/* These reserved memory regions are also defined in bootmanager
		* for configuring inbound translation for BARS, don't change
		* these without syncing with bootmanager
		*/
		shmem0_reserved: shmem@804000000 {
			reg = <0x8 0x04000000 0x0 0x1000000>;
		};
		shmem1_reserved: shmem@805000000 {
			reg = <0x8 0x05000000 0x0 0x1000000>;
		};
		pci0_msi_reserved: pci0-msi@806000000 {
			reg = <0x8 0x06000000 0x0 0x100000>;
		};
		pci1_msi_reserved: pci1-msi@806100000 {
			reg = <0x8 0x06100000 0x0 0x100000>;
		};

		mini_coredump0_reserved: mini-coredump0@806200000 {
			reg = <0x8 0x06200000 0x0 0x100000>;
		};
		mhm_reserved_0: the-mhm-reserved-0@0 {
			reg = <0x8 0x00000000 0x0 0x0000800>;
		};
	};

	aliases {
		serial0 = &uart0;
		serial1 = &uart1;
		serial2 = &uart2;
	};

	cpu_intc: interrupt-controller {
		compatible = "mti,cpu-interrupt-controller";
		interrupt-controller;
		#address-cells = <0>;
		#interrupt-cells = <1>;
	};

	soc: soc {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;
		compatible = "simple-bus";

		uart0: serial@800000 {
			compatible = "arm,pl011", "arm,primecell";
			reg = <0 0x800000 0x0 0x1000>;
			reg-io-width = <4>;
			interrupt-parent = <&gic>;
			interrupts = <GIC_SHARED 6 IRQ_TYPE_LEVEL_HIGH>;
			clocks  = <&uart_clk>, <&occ_periph>;
			clock-names = "uartclk", "apb_pclk";
		};

		uart1: serial@900000 {
			compatible = "arm,pl011", "arm,primecell";
			reg = <0 0x900000 0x0 0x1000>;
			reg-io-width = <4>;
			interrupt-parent = <&gic>;
			interrupts = <GIC_SHARED 6 IRQ_TYPE_LEVEL_HIGH>;
			clocks  = <&uart_clk>, <&occ_periph>;
			clock-names = "uartclk", "apb_pclk";
		};

		uart2: serial@a00000 {
			compatible = "arm,pl011", "arm,primecell";
			reg = <0 0xa00000 0x0 0x1000>;
			reg-io-width = <4>;
			interrupt-parent = <&gic>;
			interrupts = <GIC_SHARED 6 IRQ_TYPE_LEVEL_HIGH>;
			clocks  = <&uart_clk>, <&occ_periph>;
			clock-names = "uartclk", "apb_pclk";
		};

		gic: interrupt-controller@140000 {
			compatible = "mti,gic";
			reg = <0x0 0x140000 0x0 0x20000>;
			interrupt-controller;
			#interrupt-cells = <3>;

			/*
			* Declare the interrupt-parent even though the mti,gic
			* binding doesn't require it, such that the kernel can
			* figure out that cpu_intc is the root interrupt
			* controller & should be probed first.
			*/
			interrupt-parent = <&cpu_intc>;

			timer {
				compatible = "mti,gic-timer";
				interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
				clocks = <&core0_clk>;
			};
		};
	};
};