arch/arm/boot/dts/imx6ul-phytec-phyboard-segin-full.dts

// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright (C) 2016 PHYTEC Messtechnik GmbH
 * Author: Christian Hemp <c.hemp@phytec.de>
 */

/dts-v1/;
#include "imx6ul-phytec-pcl063.dtsi"
#include "imx6ul-phytec-phyboard-segin.dtsi"
#include "imx6ul-phytec-peb-eval-01.dtsi"

/ {
	model = "Phytec phyBOARD-Segin i.MX6 UltraLite Full Featured";
	compatible = "phytec,imx6ul-pbacd10", "phytec,imx6ul-pcl063", "fsl,imx6ul";
};

&adc1 {
	status = "okay";
};

&can1 {
	status = "okay";
};

&tlv320 {
	status = "okay";
};

&ecspi3 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_ecspi3>;
	cs-gpios = <&gpio1 20 GPIO_ACTIVE_HIGH>;
	status = "okay";
};

&fec2 {
	status = "okay";
};

&i2c_rtc {
	status = "okay";
};

&reg_can1_en {
	status = "okay";
};

&reg_sound_1v8 {
	status = "okay";
};

&reg_sound_3v3 {
	status = "okay";
};

&sai2 {
	status = "okay";
};

&sound {
	status = "okay";
};

&uart5 {
	status = "okay";
};

&usbotg1 {
	status = "okay";
};

&usbotg2 {
	status = "okay";
};

&usdhc1 {
	status = "okay";
};

&iomuxc {
	pinctrl_ecspi3: ecspi3grp {
		fsl,pins = <
			MX6UL_PAD_UART2_RTS_B__ECSPI3_MISO	0x10b0
			MX6UL_PAD_UART2_CTS_B__ECSPI3_MOSI	0x10b0
			MX6UL_PAD_UART2_RX_DATA__ECSPI3_SCLK	0x10b0
			MX6UL_PAD_UART2_TX_DATA__GPIO1_IO20	0x10b0
		>;
	};
};