| /* SPDX-License-Identifier: GPL-2.0 |
| * |
| * Copyright 2016-2018 HabanaLabs, Ltd. |
| * All Rights Reserved. |
| * |
| */ |
| |
| /************************************ |
| ** This is an auto-generated file ** |
| ** DO NOT EDIT BELOW ** |
| ************************************/ |
| |
| #ifndef ASIC_REG_DMA_IF_W_S_DOWN_CH1_REGS_H_ |
| #define ASIC_REG_DMA_IF_W_S_DOWN_CH1_REGS_H_ |
| |
| /* |
| ***************************************** |
| * DMA_IF_W_S_DOWN_CH1 (Prototype: RTR_CTRL) |
| ***************************************** |
| */ |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_PERM_SEL 0x482108 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_0 0x482114 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_1 0x482118 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_2 0x48211C |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_3 0x482120 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_4 0x482124 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_5 0x482128 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_6 0x48212C |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_7 0x482130 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_8 0x482134 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_9 0x482138 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_10 0x48213C |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_11 0x482140 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_12 0x482144 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_13 0x482148 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_14 0x48214C |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_15 0x482150 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_16 0x482154 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_17 0x482158 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_18 0x48215C |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_19 0x482160 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_20 0x482164 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_21 0x482168 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_22 0x48216C |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_23 0x482170 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_24 0x482174 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_25 0x482178 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_26 0x48217C |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_27 0x482180 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_SRAM_POLY_H3_0 0x482184 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_SRAM_POLY_H3_1 0x482188 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_SRAM_POLY_H3_2 0x48218C |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_SRAM_POLY_H3_3 0x482190 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_SRAM_POLY_H3_4 0x482194 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_SRAM_POLY_H3_5 0x482198 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_SRAM_POLY_H3_6 0x48219C |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_SRAM_POLY_H3_7 0x4821A0 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_SRAM_POLY_H3_8 0x4821A4 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_SRAM_POLY_H3_9 0x4821A8 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_SRAM_POLY_H3_10 0x4821AC |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_SRAM_POLY_H3_11 0x4821B0 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_SRAM_POLY_H3_12 0x4821B4 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_SRAM_POLY_H3_13 0x4821B8 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_SRAM_POLY_H3_14 0x4821BC |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_SCRAM_SRAM_EN 0x48226C |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RL_HBM_EN 0x482274 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RL_HBM_SAT 0x482278 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RL_HBM_RST 0x48227C |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RL_HBM_TIMEOUT 0x482280 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_SCRAM_HBM_EN 0x482284 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RL_PCI_EN 0x482288 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RL_PCI_SAT 0x48228C |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RL_PCI_RST 0x482290 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RL_PCI_TIMEOUT 0x482294 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RL_SRAM_EN 0x48229C |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RL_SRAM_SAT 0x4822A0 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RL_SRAM_RST 0x4822A4 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RL_SRAM_TIMEOUT 0x4822AC |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RL_SRAM_RED 0x4822B4 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_E2E_HBM_EN 0x4822EC |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_E2E_PCI_EN 0x4822F0 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_E2E_HBM_WR_SIZE 0x4822F4 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_E2E_PCI_WR_SIZE 0x4822F8 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_E2E_AW_PCI_CTR_SET_EN 0x482404 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_E2E_AW_PCI_CTR_SET 0x482408 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_E2E_AW_PCI_CTR_WRAP 0x48240C |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_E2E_AW_PCI_CTR_CNT 0x482410 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_E2E_AW_HBM_CTR_SET_EN 0x482414 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_E2E_AW_HBM_CTR_SET 0x482418 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_E2E_HBM_RD_SIZE 0x48241C |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_E2E_PCI_RD_SIZE 0x482420 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_E2E_AR_PCI_CTR_SET_EN 0x482424 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_E2E_AR_PCI_CTR_SET 0x482428 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_E2E_AR_PCI_CTR_WRAP 0x48242C |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_E2E_AR_PCI_CTR_CNT 0x482430 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_E2E_AR_HBM_CTR_SET_EN 0x482434 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_E2E_AR_HBM_CTR_SET 0x482438 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_NL_HBM_SEL_0 0x482450 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_NL_HBM_SEL_1 0x482454 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_NON_LIN_EN 0x482480 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_NL_SRAM_BANK_0 0x482500 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_NL_SRAM_BANK_1 0x482504 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_NL_SRAM_BANK_2 0x482508 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_NL_SRAM_BANK_3 0x48250C |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_NL_SRAM_BANK_4 0x482510 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_NL_SRAM_OFFSET_0 0x482514 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_NL_SRAM_OFFSET_1 0x482520 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_NL_SRAM_OFFSET_2 0x482524 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_NL_SRAM_OFFSET_3 0x482528 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_NL_SRAM_OFFSET_4 0x48252C |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_NL_SRAM_OFFSET_5 0x482530 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_NL_SRAM_OFFSET_6 0x482534 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_NL_SRAM_OFFSET_7 0x482538 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_NL_SRAM_OFFSET_8 0x48253C |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_NL_SRAM_OFFSET_9 0x482540 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_NL_HBM_OFFSET_0 0x482550 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_NL_HBM_OFFSET_1 0x482554 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_NL_HBM_OFFSET_2 0x482558 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_NL_HBM_OFFSET_3 0x48255C |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_NL_HBM_OFFSET_4 0x482560 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_NL_HBM_OFFSET_5 0x482564 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_NL_HBM_OFFSET_6 0x482568 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_NL_HBM_OFFSET_7 0x48256C |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_NL_HBM_OFFSET_8 0x482570 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_NL_HBM_OFFSET_9 0x482574 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_NL_HBM_OFFSET_10 0x482578 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_NL_HBM_OFFSET_11 0x48257C |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_NL_HBM_OFFSET_12 0x482580 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_NL_HBM_OFFSET_13 0x482584 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_NL_HBM_OFFSET_14 0x482588 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_NL_HBM_OFFSET_15 0x48258C |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_NL_HBM_OFFSET_16 0x482590 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_NL_HBM_OFFSET_17 0x482594 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_NL_HBM_OFFSET_18 0x482598 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_0 0x4825E4 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_1 0x4825E8 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_2 0x4825EC |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_3 0x4825F0 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_4 0x4825F4 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_5 0x4825F8 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_6 0x4825FC |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_7 0x482600 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_8 0x482604 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_9 0x482608 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_10 0x48260C |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_11 0x482610 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_12 0x482614 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_13 0x482618 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_14 0x48261C |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_15 0x482620 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_0 0x482624 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_1 0x482628 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_2 0x48262C |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_3 0x482630 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_4 0x482634 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_5 0x482638 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_6 0x48263C |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_7 0x482640 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_8 0x482644 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_9 0x482648 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_10 0x48264C |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_11 0x482650 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_12 0x482654 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_13 0x482658 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_14 0x48265C |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_15 0x482660 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_0 0x482664 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_1 0x482668 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_2 0x48266C |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_3 0x482670 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_4 0x482674 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_5 0x482678 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_6 0x48267C |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_7 0x482680 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_8 0x482684 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_9 0x482688 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_10 0x48268C |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_11 0x482690 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_12 0x482694 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_13 0x482698 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_14 0x48269C |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_15 0x4826A0 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_0 0x4826A4 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_1 0x4826A8 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_2 0x4826AC |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_3 0x4826B0 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_4 0x4826B4 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_5 0x4826B8 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_6 0x4826BC |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_7 0x4826C0 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_8 0x4826C4 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_9 0x4826C8 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_10 0x4826CC |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_11 0x4826D0 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_12 0x4826D4 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_13 0x4826D8 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_14 0x4826DC |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_15 0x4826E0 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_0 0x4826E4 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_1 0x4826E8 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_2 0x4826EC |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_3 0x4826F0 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_4 0x4826F4 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_5 0x4826F8 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_6 0x4826FC |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_7 0x482700 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_8 0x482704 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_9 0x482708 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_10 0x48270C |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_11 0x482710 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_12 0x482714 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_13 0x482718 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_14 0x48271C |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_15 0x482720 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_0 0x482724 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_1 0x482728 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_2 0x48272C |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_3 0x482730 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_4 0x482734 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_5 0x482738 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_6 0x48273C |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_7 0x482740 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_8 0x482744 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_9 0x482748 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_10 0x48274C |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_11 0x482750 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_12 0x482754 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_13 0x482758 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_14 0x48275C |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_15 0x482760 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_0 0x482764 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_1 0x482768 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_2 0x48276C |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_3 0x482770 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_4 0x482774 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_5 0x482778 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_6 0x48277C |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_7 0x482780 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_8 0x482784 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_9 0x482788 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_10 0x48278C |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_11 0x482790 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_12 0x482794 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_13 0x482798 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_14 0x48279C |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_15 0x4827A0 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_0 0x4827A4 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_1 0x4827A8 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_2 0x4827AC |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_3 0x4827B0 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_4 0x4827B4 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_5 0x4827B8 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_6 0x4827BC |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_7 0x4827C0 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_8 0x4827C4 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_9 0x4827C8 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_10 0x4827CC |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_11 0x4827D0 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_12 0x4827D4 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_13 0x4827D8 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_14 0x4827DC |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_15 0x4827E0 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_0 0x482824 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_1 0x482828 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_2 0x48282C |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_3 0x482830 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_4 0x482834 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_5 0x482838 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_6 0x48283C |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_7 0x482840 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_8 0x482844 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_9 0x482848 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_10 0x48284C |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_11 0x482850 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_12 0x482854 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_13 0x482858 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_14 0x48285C |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_15 0x482860 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_0 0x482864 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_1 0x482868 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_2 0x48286C |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_3 0x482870 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_4 0x482874 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_5 0x482878 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_6 0x48287C |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_7 0x482880 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_8 0x482884 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_9 0x482888 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_10 0x48288C |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_11 0x482890 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_12 0x482894 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_13 0x482898 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_14 0x48289C |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_15 0x4828A0 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_0 0x4828A4 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_1 0x4828A8 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_2 0x4828AC |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_3 0x4828B0 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_4 0x4828B4 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_5 0x4828B8 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_6 0x4828BC |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_7 0x4828C0 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_8 0x4828C4 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_9 0x4828C8 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_10 0x4828CC |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_11 0x4828D0 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_12 0x4828D4 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_13 0x4828D8 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_14 0x4828DC |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_15 0x4828E0 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_0 0x4828E4 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_1 0x4828E8 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_2 0x4828EC |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_3 0x4828F0 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_4 0x4828F4 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_5 0x4828F8 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_6 0x4828FC |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_7 0x482900 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_8 0x482904 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_9 0x482908 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_10 0x48290C |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_11 0x482910 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_12 0x482914 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_13 0x482918 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_14 0x48291C |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_15 0x482920 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_0 0x482924 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_1 0x482928 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_2 0x48292C |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_3 0x482930 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_4 0x482934 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_5 0x482938 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_6 0x48293C |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_7 0x482940 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_8 0x482944 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_9 0x482948 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_10 0x48294C |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_11 0x482950 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_12 0x482954 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_13 0x482958 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_14 0x48295C |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_15 0x482960 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_0 0x482964 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_1 0x482968 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_2 0x48296C |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_3 0x482970 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_4 0x482974 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_5 0x482978 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_6 0x48297C |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_7 0x482980 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_8 0x482984 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_9 0x482988 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_10 0x48298C |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_11 0x482990 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_12 0x482994 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_13 0x482998 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_14 0x48299C |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_15 0x4829A0 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_0 0x4829A4 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_1 0x4829A8 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_2 0x4829AC |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_3 0x4829B0 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_4 0x4829B4 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_5 0x4829B8 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_6 0x4829BC |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_7 0x4829C0 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_8 0x4829C4 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_9 0x4829C8 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_10 0x4829CC |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_11 0x4829D0 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_12 0x4829D4 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_13 0x4829D8 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_14 0x4829DC |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_15 0x4829E0 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_0 0x4829E4 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_1 0x4829E8 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_2 0x4829EC |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_3 0x4829F0 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_4 0x4829F4 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_5 0x4829F8 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_6 0x4829FC |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_7 0x482A00 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_8 0x482A04 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_9 0x482A08 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_10 0x482A0C |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_11 0x482A10 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_12 0x482A14 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_13 0x482A18 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_14 0x482A1C |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_15 0x482A20 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_HIT_AW 0x482A64 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_HIT_AR 0x482A68 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_HIT_AW 0x482A6C |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_HIT_AR 0x482A70 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RGL_CFG 0x482B64 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RGL_SHIFT 0x482B68 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RGL_EXPECTED_LAT_0 0x482B6C |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RGL_EXPECTED_LAT_1 0x482B70 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RGL_EXPECTED_LAT_2 0x482B74 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RGL_EXPECTED_LAT_3 0x482B78 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RGL_EXPECTED_LAT_4 0x482B7C |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RGL_EXPECTED_LAT_5 0x482B80 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RGL_EXPECTED_LAT_6 0x482B84 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RGL_EXPECTED_LAT_7 0x482B88 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RGL_TOKEN_0 0x482BAC |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RGL_TOKEN_1 0x482BB0 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RGL_TOKEN_2 0x482BB4 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RGL_TOKEN_3 0x482BB8 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RGL_TOKEN_4 0x482BBC |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RGL_TOKEN_5 0x482BC0 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RGL_TOKEN_6 0x482BC4 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RGL_TOKEN_7 0x482BC8 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RGL_BANK_ID_0 0x482BEC |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RGL_BANK_ID_1 0x482BF0 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RGL_BANK_ID_2 0x482BF4 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RGL_BANK_ID_3 0x482BF8 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RGL_BANK_ID_4 0x482BFC |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RGL_BANK_ID_5 0x482C00 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RGL_BANK_ID_6 0x482C04 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RGL_BANK_ID_7 0x482C08 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_RGL_WDT 0x482C2C |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_E2E_AR_HBM0_CH0_CTR_WRAP 0x482C30 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_E2E_AR_HBM0_CH1_CTR_WRAP 0x482C34 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_E2E_AR_HBM1_CH0_CTR_WRAP 0x482C38 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_E2E_AR_HBM1_CH1_CTR_WRAP 0x482C3C |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_E2E_AR_HBM2_CH0_CTR_WRAP 0x482C40 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_E2E_AR_HBM2_CH1_CTR_WRAP 0x482C44 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_E2E_AR_HBM3_CH0_CTR_WRAP 0x482C48 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_E2E_AR_HBM3_CH1_CTR_WRAP 0x482C4C |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_E2E_AR_HBM0_CH0_CTR_CNT 0x482C50 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_E2E_AR_HBM0_CH1_CTR_CNT 0x482C54 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_E2E_AR_HBM1_CH0_CTR_CNT 0x482C58 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_E2E_AR_HBM1_CH1_CTR_CNT 0x482C5C |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_E2E_AR_HBM2_CH0_CTR_CNT 0x482C60 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_E2E_AR_HBM2_CH1_CTR_CNT 0x482C64 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_E2E_AR_HBM3_CH0_CTR_CNT 0x482C68 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_E2E_AR_HBM3_CH1_CTR_CNT 0x482C6C |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_E2E_AW_HBM0_CH0_CTR_WRAP 0x482C70 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_E2E_AW_HBM0_CH1_CTR_WRAP 0x482C74 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_E2E_AW_HBM1_CH0_CTR_WRAP 0x482C78 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_E2E_AW_HBM1_CH1_CTR_WRAP 0x482C7C |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_E2E_AW_HBM2_CH0_CTR_WRAP 0x482C80 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_E2E_AW_HBM2_CH1_CTR_WRAP 0x482C84 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_E2E_AW_HBM3_CH0_CTR_WRAP 0x482C88 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_E2E_AW_HBM3_CH1_CTR_WRAP 0x482C8C |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_E2E_AW_HBM0_CH0_CTR_CNT 0x482C90 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_E2E_AW_HBM0_CH1_CTR_CNT 0x482C94 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_E2E_AW_HBM1_CH0_CTR_CNT 0x482C98 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_E2E_AW_HBM1_CH1_CTR_CNT 0x482C9C |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_E2E_AW_HBM2_CH0_CTR_CNT 0x482CA0 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_E2E_AW_HBM2_CH1_CTR_CNT 0x482CA4 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_E2E_AW_HBM3_CH0_CTR_CNT 0x482CA8 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_E2E_AW_HBM3_CH1_CTR_CNT 0x482CAC |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_NL_HBM_PC_SEL_0 0x482CB0 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_NL_HBM_PC_SEL_1 0x482CB4 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_NL_HBM_PC_SEL_2 0x482CB8 |
| |
| #define mmDMA_IF_W_S_DOWN_CH1_NL_HBM_PC_SEL_3 0x482CBC |
| |
| #endif /* ASIC_REG_DMA_IF_W_S_DOWN_CH1_REGS_H_ */ |
